drivers/usb/chipidea/ci.h

   1 /*
   2  * ci.h - common structures, functions, and macros of the ChipIdea driver
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  14 #define __DRIVERS_USB_CHIPIDEA_CI_H
  15
  16 #include <linux/list.h>
  17 #include <linux/irqreturn.h>
  18 #include <linux/usb.h>
  19 #include <linux/usb/gadget.h>
  20
  21 /******************************************************************************
  22  * DEFINE
  23  *****************************************************************************/
  24 #define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */
  25 #define ENDPT_MAX          32
  26
  27 /******************************************************************************
  28  * STRUCTURES
  29  *****************************************************************************/
  30 /**
  31  * struct ci13xxx_ep - endpoint representation
  32  * @ep: endpoint structure for gadget drivers
  33  * @dir: endpoint direction (TX/RX)
  34  * @num: endpoint number
  35  * @type: endpoint type
  36  * @name: string description of the endpoint
  37  * @qh: queue head for this endpoint
  38  * @wedge: is the endpoint wedged
  39  * @ci: pointer to the controller
  40  * @lock: pointer to controller's spinlock
  41  * @td_pool: pointer to controller's TD pool
  42  */
  43 struct ci13xxx_ep {
  44         struct usb_ep                           ep;
  45         u8                                      dir;
  46         u8                                      num;
  47         u8                                      type;
  48         char                                    name[16];
  49         struct {
  50                 struct list_head        queue;
  51                 struct ci13xxx_qh       *ptr;
  52                 dma_addr_t              dma;
  53         }                                       qh;
  54         int                                     wedge;
  55
  56         /* global resources */
  57         struct ci13xxx                          *ci;
  58         spinlock_t                              *lock;
  59         struct dma_pool                         *td_pool;
  60 };
  61
  62 enum ci_role {
  63         CI_ROLE_HOST = 0,
  64         CI_ROLE_GADGET,
  65         CI_ROLE_END,
  66 };
  67
  68 /**
  69  * struct ci_role_driver - host/gadget role driver
  70  * start: start this role
  71  * stop: stop this role
  72  * irq: irq handler for this role
  73  * name: role name string (host/gadget)
  74  */
  75 struct ci_role_driver {
  76         int             (*start)(struct ci13xxx *);
  77         void            (*stop)(struct ci13xxx *);
  78         irqreturn_t     (*irq)(struct ci13xxx *);
  79         const char      *name;
  80 };
  81
  82 /**
  83  * struct hw_bank - hardware register mapping representation
  84  * @lpm: set if the device is LPM capable
  85  * @phys: physical address of the controller's registers
  86  * @abs: absolute address of the beginning of register window
  87  * @cap: capability registers
  88  * @op: operational registers
  89  * @size: size of the register window
  90  * @regmap: register lookup table
  91  */
  92 struct hw_bank {
  93         unsigned        lpm;
  94         resource_size_t phys;
  95         void __iomem    *abs;
  96         void __iomem    *cap;
  97         void __iomem    *op;
  98         size_t          size;
  99         void __iomem    **regmap;
 100 };
 101
 102 /**
 103  * struct ci13xxx - chipidea device representation
 104  * @dev: pointer to parent device
 105  * @lock: access synchronization
 106  * @hw_bank: hardware register mapping
 107  * @irq: IRQ number
 108  * @roles: array of supported roles for this controller
 109  * @role: current role
 110  * @is_otg: if the device is otg-capable
 111  * @work: work for role changing
 112  * @wq: workqueue thread
 113  * @qh_pool: allocation pool for queue heads
 114  * @td_pool: allocation pool for transfer descriptors
 115  * @gadget: device side representation for peripheral controller
 116  * @driver: gadget driver
 117  * @hw_ep_max: total number of endpoints supported by hardware
 118  * @ci13xxx_ep: array of endpoints
 119  * @ep0_dir: ep0 direction
 120  * @ep0out: pointer to ep0 OUT endpoint
 121  * @ep0in: pointer to ep0 IN endpoint
 122  * @status: ep0 status request
 123  * @setaddr: if we should set the address on status completion
 124  * @address: usb address received from the host
 125  * @remote_wakeup: host-enabled remote wakeup
 126  * @suspended: suspended by host
 127  * @test_mode: the selected test mode
 128  * @platdata: platform specific information supplied by parent device
 129  * @vbus_active: is VBUS active
 130  * @transceiver: pointer to USB PHY, if any
 131  * @hcd: pointer to usb_hcd for ehci host driver
 132  */
 133 struct ci13xxx {
 134         struct device                   *dev;
 135         spinlock_t                      lock;
 136         struct hw_bank                  hw_bank;
 137         int                             irq;
 138         struct ci_role_driver           *roles[CI_ROLE_END];
 139         enum ci_role                    role;
 140         bool                            is_otg;
 141         struct work_struct              work;
 142         struct work_struct              vbus_work;
 143         struct workqueue_struct         *wq;
 144
 145         struct dma_pool                 *qh_pool;
 146         struct dma_pool                 *td_pool;
 147
 148         struct usb_gadget               gadget;
 149         struct usb_gadget_driver        *driver;
 150         unsigned                        hw_ep_max;
 151         struct ci13xxx_ep               ci13xxx_ep[ENDPT_MAX];
 152         u32                             ep0_dir;
 153         struct ci13xxx_ep               *ep0out, *ep0in;
 154
 155         struct usb_request              *status;
 156         bool                            setaddr;
 157         u8                              address;
 158         u8                              remote_wakeup;
 159         u8                              suspended;
 160         u8                              test_mode;
 161
 162         struct ci13xxx_platform_data    *platdata;
 163         int                             vbus_active;
 164         /* FIXME: some day, we'll not use global phy */
 165         bool                            global_phy;
 166         struct usb_phy                  *transceiver;
 167         struct usb_hcd                  *hcd;
 168 };
 169
 170 static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
 171 {
 172         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 173         return ci->roles[ci->role];
 174 }
 175
 176 static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
 177 {
 178         int ret;
 179
 180         if (role >= CI_ROLE_END)
 181                 return -EINVAL;
 182
 183         if (!ci->roles[role])
 184                 return -ENXIO;
 185
 186         ret = ci->roles[role]->start(ci);
 187         if (!ret)
 188                 ci->role = role;
 189         return ret;
 190 }
 191
 192 static inline void ci_role_stop(struct ci13xxx *ci)
 193 {
 194         enum ci_role role = ci->role;
 195
 196         if (role == CI_ROLE_END)
 197                 return;
 198
 199         ci->role = CI_ROLE_END;
 200
 201         ci->roles[role]->stop(ci);
 202 }
 203
 204 /******************************************************************************
 205  * REGISTERS
 206  *****************************************************************************/
 207 /* register size */
 208 #define REG_BITS   (32)
 209
 210 /* register indices */
 211 enum ci13xxx_regs {
 212         CAP_CAPLENGTH,
 213         CAP_HCCPARAMS,
 214         CAP_DCCPARAMS,
 215         CAP_TESTMODE,
 216         CAP_LAST = CAP_TESTMODE,
 217         OP_USBCMD,
 218         OP_USBSTS,
 219         OP_USBINTR,
 220         OP_DEVICEADDR,
 221         OP_ENDPTLISTADDR,
 222         OP_PORTSC,
 223         OP_DEVLC,
 224         OP_OTGSC,
 225         OP_USBMODE,
 226         OP_ENDPTSETUPSTAT,
 227         OP_ENDPTPRIME,
 228         OP_ENDPTFLUSH,
 229         OP_ENDPTSTAT,
 230         OP_ENDPTCOMPLETE,
 231         OP_ENDPTCTRL,
 232         /* endptctrl1..15 follow */
 233         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
 234 };
 235
 236 /**
 237  * ffs_nr: find first (least significant) bit set
 238  * @x: the word to search
 239  *
 240  * This function returns bit number (instead of position)
 241  */
 242 static inline int ffs_nr(u32 x)
 243 {
 244         int n = ffs(x);
 245
 246         return n ? n-1 : 32;
 247 }
 248
 249 /**
 250  * hw_read: reads from a hw register
 251  * @reg:  register index
 252  * @mask: bitfield mask
 253  *
 254  * This function returns register contents
 255  */
 256 static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
 257 {
 258         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 259 }
 260
 261 /**
 262  * hw_write: writes to a hw register
 263  * @reg:  register index
 264  * @mask: bitfield mask
 265  * @data: new value
 266  */
 267 static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
 268                             u32 mask, u32 data)
 269 {
 270         if (~mask)
 271                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 272                         | (data & mask);
 273
 274         iowrite32(data, ci->hw_bank.regmap[reg]);
 275 }
 276
 277 /**
 278  * hw_test_and_clear: tests & clears a hw register
 279  * @reg:  register index
 280  * @mask: bitfield mask
 281  *
 282  * This function returns register contents
 283  */
 284 static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
 285                                     u32 mask)
 286 {
 287         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 288
 289         iowrite32(val, ci->hw_bank.regmap[reg]);
 290         return val;
 291 }
 292
 293 /**
 294  * hw_test_and_write: tests & writes a hw register
 295  * @reg:  register index
 296  * @mask: bitfield mask
 297  * @data: new value
 298  *
 299  * This function returns register contents
 300  */
 301 static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
 302                                     u32 mask, u32 data)
 303 {
 304         u32 val = hw_read(ci, reg, ~0);
 305
 306         hw_write(ci, reg, mask, data);
 307         return (val & mask) >> ffs_nr(mask);
 308 }
 309
 310 int hw_device_reset(struct ci13xxx *ci, u32 mode);
 311
 312 int hw_port_test_set(struct ci13xxx *ci, u8 mode);
 313
 314 u8 hw_port_test_get(struct ci13xxx *ci);
 315
 316 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */