drivers/clk/renesas/clk-rz.c

   1 /*
   2  * rz Core CPG Clocks
   3  *
   4  * Copyright (C) 2013 Ideas On Board SPRL
   5  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/clk/renesas.h>
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/slab.h>
  19
  20 struct rz_cpg {
  21         struct clk_onecell_data data;
  22         void __iomem *reg;
  23 };
  24
  25 #define CPG_FRQCR       0x10
  26 #define CPG_FRQCR2      0x14
  27
  28 #define PPR0            0xFCFE3200
  29 #define PIBC0           0xFCFE7000
  30
  31 #define MD_CLK(x)       ((x >> 2) & 1)  /* P0_2 */
  32
  33 /* -----------------------------------------------------------------------------
  34  * Initialization
  35  */
  36
  37 static u16 __init rz_cpg_read_mode_pins(void)
  38 {
  39         void __iomem *ppr0, *pibc0;
  40         u16 modes;
  41
  42         ppr0 = ioremap_nocache(PPR0, 2);
  43         pibc0 = ioremap_nocache(PIBC0, 2);
  44         BUG_ON(!ppr0 || !pibc0);
  45         iowrite16(4, pibc0);    /* enable input buffer */
  46         modes = ioread16(ppr0);
  47         iounmap(ppr0);
  48         iounmap(pibc0);
  49
  50         return modes;
  51 }
  52
  53 static struct clk * __init
  54 rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
  55 {
  56         u32 val;
  57         unsigned mult;
  58         static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
  59
  60         if (strcmp(name, "pll") == 0) {
  61                 unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
  62                 const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
  63
  64                 mult = cpg_mode ? (32 / 4) : 30;
  65
  66                 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
  67         }
  68
  69         /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
  70         if (!cpg->reg)
  71                 return ERR_PTR(-ENXIO);
  72
  73         /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
  74          * and the constraint that always g <= i. To get the rz platform started,
  75          * let them run at fixed current speed and implement the details later.
  76          */
  77         if (strcmp(name, "i") == 0)
  78                 val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
  79         else if (strcmp(name, "g") == 0)
  80                 val = clk_readl(cpg->reg + CPG_FRQCR2) & 3;
  81         else
  82                 return ERR_PTR(-EINVAL);
  83
  84         mult = frqcr_tab[val];
  85         return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
  86 }
  87
  88 static void __init rz_cpg_clocks_init(struct device_node *np)
  89 {
  90         struct rz_cpg *cpg;
  91         struct clk **clks;
  92         unsigned i;
  93         int num_clks;
  94
  95         num_clks = of_property_count_strings(np, "clock-output-names");
  96         if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
  97                 return;
  98
  99         cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
 100         clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
 101         BUG_ON(!cpg || !clks);
 102
 103         cpg->data.clks = clks;
 104         cpg->data.clk_num = num_clks;
 105
 106         cpg->reg = of_iomap(np, 0);
 107
 108         for (i = 0; i < num_clks; ++i) {
 109                 const char *name;
 110                 struct clk *clk;
 111
 112                 of_property_read_string_index(np, "clock-output-names", i, &name);
 113
 114                 clk = rz_cpg_register_clock(np, cpg, name);
 115                 if (IS_ERR(clk))
 116                         pr_err("%s: failed to register %s %s clock (%ld)\n",
 117                                __func__, np->name, name, PTR_ERR(clk));
 118                 else
 119                         cpg->data.clks[i] = clk;
 120         }
 121
 122         of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
 123
 124         cpg_mstp_add_clk_domain(np);
 125 }
 126 CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);