drivers/spi/spi-bcm63xx.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   5  * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/completion.h>
  27 #include <linux/err.h>
  28 #include <linux/pm_runtime.h>
  29
  30 /* BCM 6338/6348 SPI core */
  31 #define SPI_6348_RSET_SIZE              64
  32 #define SPI_6348_CMD                    0x00    /* 16-bits register */
  33 #define SPI_6348_INT_STATUS             0x02
  34 #define SPI_6348_INT_MASK_ST            0x03
  35 #define SPI_6348_INT_MASK               0x04
  36 #define SPI_6348_ST                     0x05
  37 #define SPI_6348_CLK_CFG                0x06
  38 #define SPI_6348_FILL_BYTE              0x07
  39 #define SPI_6348_MSG_TAIL               0x09
  40 #define SPI_6348_RX_TAIL                0x0b
  41 #define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
  42 #define SPI_6348_MSG_CTL_WIDTH          8
  43 #define SPI_6348_MSG_DATA               0x41
  44 #define SPI_6348_MSG_DATA_SIZE          0x3f
  45 #define SPI_6348_RX_DATA                0x80
  46 #define SPI_6348_RX_DATA_SIZE           0x3f
  47
  48 /* BCM 3368/6358/6262/6368 SPI core */
  49 #define SPI_6358_RSET_SIZE              1804
  50 #define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
  51 #define SPI_6358_MSG_CTL_WIDTH          16
  52 #define SPI_6358_MSG_DATA               0x02
  53 #define SPI_6358_MSG_DATA_SIZE          0x21e
  54 #define SPI_6358_RX_DATA                0x400
  55 #define SPI_6358_RX_DATA_SIZE           0x220
  56 #define SPI_6358_CMD                    0x700   /* 16-bits register */
  57 #define SPI_6358_INT_STATUS             0x702
  58 #define SPI_6358_INT_MASK_ST            0x703
  59 #define SPI_6358_INT_MASK               0x704
  60 #define SPI_6358_ST                     0x705
  61 #define SPI_6358_CLK_CFG                0x706
  62 #define SPI_6358_FILL_BYTE              0x707
  63 #define SPI_6358_MSG_TAIL               0x709
  64 #define SPI_6358_RX_TAIL                0x70B
  65
  66 /* Shared SPI definitions */
  67
  68 /* Message configuration */
  69 #define SPI_FD_RW                       0x00
  70 #define SPI_HD_W                        0x01
  71 #define SPI_HD_R                        0x02
  72 #define SPI_BYTE_CNT_SHIFT              0
  73 #define SPI_6348_MSG_TYPE_SHIFT         6
  74 #define SPI_6358_MSG_TYPE_SHIFT         14
  75
  76 /* Command */
  77 #define SPI_CMD_NOOP                    0x00
  78 #define SPI_CMD_SOFT_RESET              0x01
  79 #define SPI_CMD_HARD_RESET              0x02
  80 #define SPI_CMD_START_IMMEDIATE         0x03
  81 #define SPI_CMD_COMMAND_SHIFT           0
  82 #define SPI_CMD_COMMAND_MASK            0x000f
  83 #define SPI_CMD_DEVICE_ID_SHIFT         4
  84 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
  85 #define SPI_CMD_ONE_BYTE_SHIFT          11
  86 #define SPI_CMD_ONE_WIRE_SHIFT          12
  87 #define SPI_DEV_ID_0                    0
  88 #define SPI_DEV_ID_1                    1
  89 #define SPI_DEV_ID_2                    2
  90 #define SPI_DEV_ID_3                    3
  91
  92 /* Interrupt mask */
  93 #define SPI_INTR_CMD_DONE               0x01
  94 #define SPI_INTR_RX_OVERFLOW            0x02
  95 #define SPI_INTR_TX_UNDERFLOW           0x04
  96 #define SPI_INTR_TX_OVERFLOW            0x08
  97 #define SPI_INTR_RX_UNDERFLOW           0x10
  98 #define SPI_INTR_CLEAR_ALL              0x1f
  99
 100 /* Status */
 101 #define SPI_RX_EMPTY                    0x02
 102 #define SPI_CMD_BUSY                    0x04
 103 #define SPI_SERIAL_BUSY                 0x08
 104
 105 /* Clock configuration */
 106 #define SPI_CLK_20MHZ                   0x00
 107 #define SPI_CLK_0_391MHZ                0x01
 108 #define SPI_CLK_0_781MHZ                0x02    /* default */
 109 #define SPI_CLK_1_563MHZ                0x03
 110 #define SPI_CLK_3_125MHZ                0x04
 111 #define SPI_CLK_6_250MHZ                0x05
 112 #define SPI_CLK_12_50MHZ                0x06
 113 #define SPI_CLK_MASK                    0x07
 114 #define SPI_SSOFFTIME_MASK              0x38
 115 #define SPI_SSOFFTIME_SHIFT             3
 116 #define SPI_BYTE_SWAP                   0x80
 117
 118 enum bcm63xx_regs_spi {
 119         SPI_CMD,
 120         SPI_INT_STATUS,
 121         SPI_INT_MASK_ST,
 122         SPI_INT_MASK,
 123         SPI_ST,
 124         SPI_CLK_CFG,
 125         SPI_FILL_BYTE,
 126         SPI_MSG_TAIL,
 127         SPI_RX_TAIL,
 128         SPI_MSG_CTL,
 129         SPI_MSG_DATA,
 130         SPI_RX_DATA,
 131         SPI_MSG_TYPE_SHIFT,
 132         SPI_MSG_CTL_WIDTH,
 133         SPI_MSG_DATA_SIZE,
 134 };
 135
 136 #define BCM63XX_SPI_MAX_PREPEND         15
 137
 138 #define BCM63XX_SPI_MAX_CS              8
 139 #define BCM63XX_SPI_BUS_NUM             0
 140
 141 struct bcm63xx_spi {
 142         struct completion       done;
 143
 144         void __iomem            *regs;
 145         int                     irq;
 146
 147         /* Platform data */
 148         const unsigned long     *reg_offsets;
 149         unsigned                fifo_size;
 150         unsigned int            msg_type_shift;
 151         unsigned int            msg_ctl_width;
 152
 153         /* data iomem */
 154         u8 __iomem              *tx_io;
 155         const u8 __iomem        *rx_io;
 156
 157         struct clk              *clk;
 158         struct platform_device  *pdev;
 159 };
 160
 161 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 162                                unsigned int offset)
 163 {
 164         return readb(bs->regs + bs->reg_offsets[offset]);
 165 }
 166
 167 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 168                                 unsigned int offset)
 169 {
 170 #ifdef CONFIG_CPU_BIG_ENDIAN
 171         return ioread16be(bs->regs + bs->reg_offsets[offset]);
 172 #else
 173         return readw(bs->regs + bs->reg_offsets[offset]);
 174 #endif
 175 }
 176
 177 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
 178                                   u8 value, unsigned int offset)
 179 {
 180         writeb(value, bs->regs + bs->reg_offsets[offset]);
 181 }
 182
 183 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
 184                                   u16 value, unsigned int offset)
 185 {
 186 #ifdef CONFIG_CPU_BIG_ENDIAN
 187         iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
 188 #else
 189         writew(value, bs->regs + bs->reg_offsets[offset]);
 190 #endif
 191 }
 192
 193 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
 194         { 20000000, SPI_CLK_20MHZ },
 195         { 12500000, SPI_CLK_12_50MHZ },
 196         {  6250000, SPI_CLK_6_250MHZ },
 197         {  3125000, SPI_CLK_3_125MHZ },
 198         {  1563000, SPI_CLK_1_563MHZ },
 199         {   781000, SPI_CLK_0_781MHZ },
 200         {   391000, SPI_CLK_0_391MHZ }
 201 };
 202
 203 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
 204                                       struct spi_transfer *t)
 205 {
 206         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 207         u8 clk_cfg, reg;
 208         int i;
 209
 210         /* Default to lowest clock configuration */
 211         clk_cfg = SPI_CLK_0_391MHZ;
 212
 213         /* Find the closest clock configuration */
 214         for (i = 0; i < SPI_CLK_MASK; i++) {
 215                 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 216                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 217                         break;
 218                 }
 219         }
 220
 221         /* clear existing clock configuration bits of the register */
 222         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 223         reg &= ~SPI_CLK_MASK;
 224         reg |= clk_cfg;
 225
 226         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 227         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 228                 clk_cfg, t->speed_hz);
 229 }
 230
 231 /* the spi->mode bits understood by this driver: */
 232 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 233
 234 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 235                                 unsigned int num_transfers)
 236 {
 237         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 238         u16 msg_ctl;
 239         u16 cmd;
 240         unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 241         struct spi_transfer *t = first;
 242         bool do_rx = false;
 243         bool do_tx = false;
 244
 245         /* Disable the CMD_DONE interrupt */
 246         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 247
 248         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 249                 t->tx_buf, t->rx_buf, t->len);
 250
 251         if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 252                 prepend_len = t->len;
 253
 254         /* prepare the buffer */
 255         for (i = 0; i < num_transfers; i++) {
 256                 if (t->tx_buf) {
 257                         do_tx = true;
 258                         memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 259
 260                         /* don't prepend more than one tx */
 261                         if (t != first)
 262                                 prepend_len = 0;
 263                 }
 264
 265                 if (t->rx_buf) {
 266                         do_rx = true;
 267                         /* prepend is half-duplex write only */
 268                         if (t == first)
 269                                 prepend_len = 0;
 270                 }
 271
 272                 len += t->len;
 273
 274                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 275                                transfer_list);
 276         }
 277
 278         reinit_completion(&bs->done);
 279
 280         /* Fill in the Message control register */
 281         msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 282
 283         if (do_rx && do_tx && prepend_len == 0)
 284                 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 285         else if (do_rx)
 286                 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 287         else if (do_tx)
 288                 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 289
 290         switch (bs->msg_ctl_width) {
 291         case 8:
 292                 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 293                 break;
 294         case 16:
 295                 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 296                 break;
 297         }
 298
 299         /* Issue the transfer */
 300         cmd = SPI_CMD_START_IMMEDIATE;
 301         cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 302         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 303         bcm_spi_writew(bs, cmd, SPI_CMD);
 304
 305         /* Enable the CMD_DONE interrupt */
 306         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 307
 308         timeout = wait_for_completion_timeout(&bs->done, HZ);
 309         if (!timeout)
 310                 return -ETIMEDOUT;
 311
 312         if (!do_rx)
 313                 return 0;
 314
 315         len = 0;
 316         t = first;
 317         /* Read out all the data */
 318         for (i = 0; i < num_transfers; i++) {
 319                 if (t->rx_buf)
 320                         memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 321
 322                 if (t != first || prepend_len == 0)
 323                         len += t->len;
 324
 325                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 326                                transfer_list);
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 333                                         struct spi_message *m)
 334 {
 335         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 336         struct spi_transfer *t, *first = NULL;
 337         struct spi_device *spi = m->spi;
 338         int status = 0;
 339         unsigned int n_transfers = 0, total_len = 0;
 340         bool can_use_prepend = false;
 341
 342         /*
 343          * This SPI controller does not support keeping CS active after a
 344          * transfer.
 345          * Work around this by merging as many transfers we can into one big
 346          * full-duplex transfers.
 347          */
 348         list_for_each_entry(t, &m->transfers, transfer_list) {
 349                 if (!first)
 350                         first = t;
 351
 352                 n_transfers++;
 353                 total_len += t->len;
 354
 355                 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 356                     first->len <= BCM63XX_SPI_MAX_PREPEND)
 357                         can_use_prepend = true;
 358                 else if (can_use_prepend && t->tx_buf)
 359                         can_use_prepend = false;
 360
 361                 /* we can only transfer one fifo worth of data */
 362                 if ((can_use_prepend &&
 363                      total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 364                     (!can_use_prepend && total_len > bs->fifo_size)) {
 365                         dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 366                                 total_len, bs->fifo_size);
 367                         status = -EINVAL;
 368                         goto exit;
 369                 }
 370
 371                 /* all combined transfers have to have the same speed */
 372                 if (t->speed_hz != first->speed_hz) {
 373                         dev_err(&spi->dev, "unable to change speed between transfers\n");
 374                         status = -EINVAL;
 375                         goto exit;
 376                 }
 377
 378                 /* CS will be deasserted directly after transfer */
 379                 if (t->delay_usecs) {
 380                         dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 381                         status = -EINVAL;
 382                         goto exit;
 383                 }
 384
 385                 if (t->cs_change ||
 386                     list_is_last(&t->transfer_list, &m->transfers)) {
 387                         /* configure adapter for a new transfer */
 388                         bcm63xx_spi_setup_transfer(spi, first);
 389
 390                         /* send the data */
 391                         status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 392                         if (status)
 393                                 goto exit;
 394
 395                         m->actual_length += total_len;
 396
 397                         first = NULL;
 398                         n_transfers = 0;
 399                         total_len = 0;
 400                         can_use_prepend = false;
 401                 }
 402         }
 403 exit:
 404         m->status = status;
 405         spi_finalize_current_message(master);
 406
 407         return 0;
 408 }
 409
 410 /* This driver supports single master mode only. Hence
 411  * CMD_DONE is the only interrupt we care about
 412  */
 413 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 414 {
 415         struct spi_master *master = (struct spi_master *)dev_id;
 416         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 417         u8 intr;
 418
 419         /* Read interupts and clear them immediately */
 420         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 421         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 422         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 423
 424         /* A transfer completed */
 425         if (intr & SPI_INTR_CMD_DONE)
 426                 complete(&bs->done);
 427
 428         return IRQ_HANDLED;
 429 }
 430
 431 static const unsigned long bcm6348_spi_reg_offsets[] = {
 432         [SPI_CMD]               = SPI_6348_CMD,
 433         [SPI_INT_STATUS]        = SPI_6348_INT_STATUS,
 434         [SPI_INT_MASK_ST]       = SPI_6348_INT_MASK_ST,
 435         [SPI_INT_MASK]          = SPI_6348_INT_MASK,
 436         [SPI_ST]                = SPI_6348_ST,
 437         [SPI_CLK_CFG]           = SPI_6348_CLK_CFG,
 438         [SPI_FILL_BYTE]         = SPI_6348_FILL_BYTE,
 439         [SPI_MSG_TAIL]          = SPI_6348_MSG_TAIL,
 440         [SPI_RX_TAIL]           = SPI_6348_RX_TAIL,
 441         [SPI_MSG_CTL]           = SPI_6348_MSG_CTL,
 442         [SPI_MSG_DATA]          = SPI_6348_MSG_DATA,
 443         [SPI_RX_DATA]           = SPI_6348_RX_DATA,
 444         [SPI_MSG_TYPE_SHIFT]    = SPI_6348_MSG_TYPE_SHIFT,
 445         [SPI_MSG_CTL_WIDTH]     = SPI_6348_MSG_CTL_WIDTH,
 446         [SPI_MSG_DATA_SIZE]     = SPI_6348_MSG_DATA_SIZE,
 447 };
 448
 449 static const unsigned long bcm6358_spi_reg_offsets[] = {
 450         [SPI_CMD]               = SPI_6358_CMD,
 451         [SPI_INT_STATUS]        = SPI_6358_INT_STATUS,
 452         [SPI_INT_MASK_ST]       = SPI_6358_INT_MASK_ST,
 453         [SPI_INT_MASK]          = SPI_6358_INT_MASK,
 454         [SPI_ST]                = SPI_6358_ST,
 455         [SPI_CLK_CFG]           = SPI_6358_CLK_CFG,
 456         [SPI_FILL_BYTE]         = SPI_6358_FILL_BYTE,
 457         [SPI_MSG_TAIL]          = SPI_6358_MSG_TAIL,
 458         [SPI_RX_TAIL]           = SPI_6358_RX_TAIL,
 459         [SPI_MSG_CTL]           = SPI_6358_MSG_CTL,
 460         [SPI_MSG_DATA]          = SPI_6358_MSG_DATA,
 461         [SPI_RX_DATA]           = SPI_6358_RX_DATA,
 462         [SPI_MSG_TYPE_SHIFT]    = SPI_6358_MSG_TYPE_SHIFT,
 463         [SPI_MSG_CTL_WIDTH]     = SPI_6358_MSG_CTL_WIDTH,
 464         [SPI_MSG_DATA_SIZE]     = SPI_6358_MSG_DATA_SIZE,
 465 };
 466
 467 static const struct platform_device_id bcm63xx_spi_dev_match[] = {
 468         {
 469                 .name = "bcm6348-spi",
 470                 .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
 471         },
 472         {
 473                 .name = "bcm6358-spi",
 474                 .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
 475         },
 476         {
 477         },
 478 };
 479
 480 static int bcm63xx_spi_probe(struct platform_device *pdev)
 481 {
 482         struct resource *r;
 483         const unsigned long *bcm63xx_spireg;
 484         struct device *dev = &pdev->dev;
 485         int irq;
 486         struct spi_master *master;
 487         struct clk *clk;
 488         struct bcm63xx_spi *bs;
 489         int ret;
 490
 491         if (!pdev->id_entry->driver_data)
 492                 return -EINVAL;
 493
 494         bcm63xx_spireg = (const unsigned long *)pdev->id_entry->driver_data;
 495
 496         irq = platform_get_irq(pdev, 0);
 497         if (irq < 0) {
 498                 dev_err(dev, "no irq\n");
 499                 return -ENXIO;
 500         }
 501
 502         clk = devm_clk_get(dev, "spi");
 503         if (IS_ERR(clk)) {
 504                 dev_err(dev, "no clock for device\n");
 505                 return PTR_ERR(clk);
 506         }
 507
 508         master = spi_alloc_master(dev, sizeof(*bs));
 509         if (!master) {
 510                 dev_err(dev, "out of memory\n");
 511                 return -ENOMEM;
 512         }
 513
 514         bs = spi_master_get_devdata(master);
 515         init_completion(&bs->done);
 516
 517         platform_set_drvdata(pdev, master);
 518         bs->pdev = pdev;
 519
 520         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 521         bs->regs = devm_ioremap_resource(&pdev->dev, r);
 522         if (IS_ERR(bs->regs)) {
 523                 ret = PTR_ERR(bs->regs);
 524                 goto out_err;
 525         }
 526
 527         bs->irq = irq;
 528         bs->clk = clk;
 529         bs->reg_offsets = bcm63xx_spireg;
 530         bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
 531
 532         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 533                                                         pdev->name, master);
 534         if (ret) {
 535                 dev_err(dev, "unable to request irq\n");
 536                 goto out_err;
 537         }
 538
 539         master->bus_num = BCM63XX_SPI_BUS_NUM;
 540         master->num_chipselect = BCM63XX_SPI_MAX_CS;
 541         master->transfer_one_message = bcm63xx_spi_transfer_one;
 542         master->mode_bits = MODEBITS;
 543         master->bits_per_word_mask = SPI_BPW_MASK(8);
 544         master->auto_runtime_pm = true;
 545         bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
 546         bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
 547         bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
 548         bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
 549
 550         /* Initialize hardware */
 551         ret = clk_prepare_enable(bs->clk);
 552         if (ret)
 553                 goto out_err;
 554
 555         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 556
 557         /* register and we are done */
 558         ret = devm_spi_register_master(dev, master);
 559         if (ret) {
 560                 dev_err(dev, "spi register failed\n");
 561                 goto out_clk_disable;
 562         }
 563
 564         dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
 565                  r, irq, bs->fifo_size);
 566
 567         return 0;
 568
 569 out_clk_disable:
 570         clk_disable_unprepare(clk);
 571 out_err:
 572         spi_master_put(master);
 573         return ret;
 574 }
 575
 576 static int bcm63xx_spi_remove(struct platform_device *pdev)
 577 {
 578         struct spi_master *master = platform_get_drvdata(pdev);
 579         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 580
 581         /* reset spi block */
 582         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 583
 584         /* HW shutdown */
 585         clk_disable_unprepare(bs->clk);
 586
 587         return 0;
 588 }
 589
 590 #ifdef CONFIG_PM_SLEEP
 591 static int bcm63xx_spi_suspend(struct device *dev)
 592 {
 593         struct spi_master *master = dev_get_drvdata(dev);
 594         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 595
 596         spi_master_suspend(master);
 597
 598         clk_disable_unprepare(bs->clk);
 599
 600         return 0;
 601 }
 602
 603 static int bcm63xx_spi_resume(struct device *dev)
 604 {
 605         struct spi_master *master = dev_get_drvdata(dev);
 606         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 607         int ret;
 608
 609         ret = clk_prepare_enable(bs->clk);
 610         if (ret)
 611                 return ret;
 612
 613         spi_master_resume(master);
 614
 615         return 0;
 616 }
 617 #endif
 618
 619 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 620         SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
 621 };
 622
 623 static struct platform_driver bcm63xx_spi_driver = {
 624         .driver = {
 625                 .name   = "bcm63xx-spi",
 626                 .pm     = &bcm63xx_spi_pm_ops,
 627         },
 628         .id_table       = bcm63xx_spi_dev_match,
 629         .probe          = bcm63xx_spi_probe,
 630         .remove         = bcm63xx_spi_remove,
 631 };
 632
 633 module_platform_driver(bcm63xx_spi_driver);
 634
 635 MODULE_ALIAS("platform:bcm63xx_spi");
 636 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 637 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 638 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 639 MODULE_LICENSE("GPL");