arch/sh/mm/tlb-sh4.c

   1 /*
   2  * arch/sh/mm/tlb-sh4.c
   3  *
   4  * SH-4 specific TLB operations
   5  *
   6  * Copyright (C) 1999  Niibe Yutaka
   7  * Copyright (C) 2002 - 2007 Paul Mundt
   8  *
   9  * Released under the terms of the GNU GPL v2.0.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/io.h>
  14 #include <asm/system.h>
  15 #include <asm/mmu_context.h>
  16 #include <asm/cacheflush.h>
  17
  18 void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  19 {
  20         unsigned long flags, pteval, vpn;
  21
  22         /*
  23          * Handle debugger faulting in for debugee.
  24          */
  25         if (vma && current->active_mm != vma->vm_mm)
  26                 return;
  27
  28         local_irq_save(flags);
  29
  30         /* Set PTEH register */
  31         vpn = (address & MMU_VPN_MASK) | get_asid();
  32         __raw_writel(vpn, MMU_PTEH);
  33
  34         pteval = pte.pte_low;
  35
  36         /* Set PTEA register */
  37 #ifdef CONFIG_X2TLB
  38         /*
  39          * For the extended mode TLB this is trivial, only the ESZ and
  40          * EPR bits need to be written out to PTEA, with the remainder of
  41          * the protection bits (with the exception of the compat-mode SZ
  42          * and PR bits, which are cleared) being written out in PTEL.
  43          */
  44         __raw_writel(pte.pte_high, MMU_PTEA);
  45 #else
  46         if (cpu_data->flags & CPU_HAS_PTEA) {
  47                 /* The last 3 bits and the first one of pteval contains
  48                  * the PTEA timing control and space attribute bits
  49                  */
  50                 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
  51         }
  52 #endif
  53
  54         /* Set PTEL register */
  55         pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
  56 #ifdef CONFIG_CACHE_WRITETHROUGH
  57         pteval |= _PAGE_WT;
  58 #endif
  59         /* conveniently, we want all the software flags to be 0 anyway */
  60         __raw_writel(pteval, MMU_PTEL);
  61
  62         /* Load the TLB */
  63         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
  64         local_irq_restore(flags);
  65 }
  66
  67 void local_flush_tlb_one(unsigned long asid, unsigned long page)
  68 {
  69         unsigned long addr, data;
  70
  71         /*
  72          * NOTE: PTEH.ASID should be set to this MM
  73          *       _AND_ we need to write ASID to the array.
  74          *
  75          * It would be simple if we didn't need to set PTEH.ASID...
  76          */
  77         addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
  78         data = page | asid; /* VALID bit is off */
  79         jump_to_uncached();
  80         __raw_writel(data, addr);
  81         back_to_cached();
  82 }
  83
  84 void local_flush_tlb_all(void)
  85 {
  86         unsigned long flags, status;
  87         int i;
  88
  89         /*
  90          * Flush all the TLB.
  91          */
  92         local_irq_save(flags);
  93         jump_to_uncached();
  94
  95         status = __raw_readl(MMUCR);
  96         status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
  97
  98         if (status == 0)
  99                 status = MMUCR_URB_NENTRIES;
 100
 101         for (i = 0; i < status; i++)
 102                 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
 103
 104         for (i = 0; i < 4; i++)
 105                 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
 106
 107         back_to_cached();
 108         ctrl_barrier();
 109         local_irq_restore(flags);
 110 }