?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: ep93xx: move timer to its own file
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_nx2.c
blob000c57e4d03389768bfb31f901c1600a82f95dfc
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8 #include <linux/vmalloc.h>
9 #include <linux/delay.h>
10
11 #include "qla_def.h"
12 #include "qla_gbl.h"
13
14 #include <linux/delay.h>
15
16 #define TIMEOUT_100_MS 100
17
18 /* 8044 Flash Read/Write functions */
19 uint32_t
20 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
21 {
22 return readl((void __iomem *) (ha->nx_pcibase + addr));
23 }
24
25 void
26 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
27 {
28 writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
29 }
30
31 int
32 qla8044_rd_direct(struct scsi_qla_host *vha,
33 const uint32_t crb_reg)
34 {
35 struct qla_hw_data *ha = vha->hw;
36
37 if (crb_reg < CRB_REG_INDEX_MAX)
38 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
39 else
40 return QLA_FUNCTION_FAILED;
41 }
42
43 void
44 qla8044_wr_direct(struct scsi_qla_host *vha,
45 const uint32_t crb_reg,
46 const uint32_t value)
47 {
48 struct qla_hw_data *ha = vha->hw;
49
50 if (crb_reg < CRB_REG_INDEX_MAX)
51 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
52 }
53
54 static int
55 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
56 {
57 uint32_t val;
58 int ret_val = QLA_SUCCESS;
59 struct qla_hw_data *ha = vha->hw;
60
61 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
62 val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
63
64 if (val != addr) {
65 ql_log(ql_log_warn, vha, 0xb087,
66 "%s: Failed to set register window : "
67 "addr written 0x%x, read 0x%x!\n",
68 __func__, addr, val);
69 ret_val = QLA_FUNCTION_FAILED;
70 }
71 return ret_val;
72 }
73
74 static int
75 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
76 {
77 int ret_val = QLA_SUCCESS;
78 struct qla_hw_data *ha = vha->hw;
79
80 ret_val = qla8044_set_win_base(vha, addr);
81 if (!ret_val)
82 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
83 else
84 ql_log(ql_log_warn, vha, 0xb088,
85 "%s: failed read of addr 0x%x!\n", __func__, addr);
86 return ret_val;
87 }
88
89 static int
90 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
91 {
92 int ret_val = QLA_SUCCESS;
93 struct qla_hw_data *ha = vha->hw;
94
95 ret_val = qla8044_set_win_base(vha, addr);
96 if (!ret_val)
97 qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
98 else
99 ql_log(ql_log_warn, vha, 0xb089,
100 "%s: failed wrt to addr 0x%x, data 0x%x\n",
101 __func__, addr, data);
102 return ret_val;
103 }
104
105 /*
106 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
107 *
108 * @ha : Pointer to adapter structure
109 * @raddr : CRB address to read from
110 * @waddr : CRB address to write to
111 *
112 */
113 static void
114 qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
115 uint32_t raddr, uint32_t waddr)
116 {
117 uint32_t value;
118
119 qla8044_rd_reg_indirect(vha, raddr, &value);
120 qla8044_wr_reg_indirect(vha, waddr, value);
121 }
122
123 static int
124 qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1,
125 uint32_t mask)
126 {
127 unsigned long timeout;
128 uint32_t temp;
129
130 /* jiffies after 100ms */
131 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
132 do {
133 qla8044_rd_reg_indirect(vha, addr1, &temp);
134 if ((temp & mask) != 0)
135 break;
136 if (time_after_eq(jiffies, timeout)) {
137 ql_log(ql_log_warn, vha, 0xb151,
138 "Error in processing rdmdio entry\n");
139 return -1;
140 }
141 } while (1);
142
143 return 0;
144 }
145
146 static uint32_t
147 qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha,
148 uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr)
149 {
150 uint32_t temp;
151 int ret = 0;
152
153 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
154 if (ret == -1)
155 return -1;
156
157 temp = (0x40000000 | addr);
158 qla8044_wr_reg_indirect(vha, addr1, temp);
159
160 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
161 if (ret == -1)
162 return 0;
163
164 qla8044_rd_reg_indirect(vha, addr3, &ret);
165
166 return ret;
167 }
168
169
170 static int
171 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha,
172 uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask)
173 {
174 unsigned long timeout;
175 uint32_t temp;
176
177 /* jiffies after 100 msecs */
178 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
179 do {
180 temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2);
181 if ((temp & 0x1) != 1)
182 break;
183 if (time_after_eq(jiffies, timeout)) {
184 ql_log(ql_log_warn, vha, 0xb152,
185 "Error in processing mdiobus idle\n");
186 return -1;
187 }
188 } while (1);
189
190 return 0;
191 }
192
193 static int
194 qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1,
195 uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value)
196 {
197 int ret = 0;
198
199 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
200 if (ret == -1)
201 return -1;
202
203 qla8044_wr_reg_indirect(vha, addr3, value);
204 qla8044_wr_reg_indirect(vha, addr1, addr);
205
206 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
207 if (ret == -1)
208 return -1;
209
210 return 0;
211 }
212 /*
213 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
214 * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
215 *
216 * @vha : Pointer to adapter structure
217 * @raddr : CRB address to read from
218 * @waddr : CRB address to write to
219 * @p_rmw_hdr : header with shift/or/xor values.
220 *
221 */
222 static void
223 qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
224 uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
225 {
226 uint32_t value;
227
228 if (p_rmw_hdr->index_a)
229 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
230 else
231 qla8044_rd_reg_indirect(vha, raddr, &value);
232 value &= p_rmw_hdr->test_mask;
233 value <<= p_rmw_hdr->shl;
234 value >>= p_rmw_hdr->shr;
235 value |= p_rmw_hdr->or_value;
236 value ^= p_rmw_hdr->xor_value;
237 qla8044_wr_reg_indirect(vha, waddr, value);
238 return;
239 }
240
241 static inline void
242 qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
243 {
244 uint32_t qsnt_state;
245 struct qla_hw_data *ha = vha->hw;
246
247 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
248 qsnt_state |= (1 << ha->portnum);
249 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
250 ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
251 __func__, vha->host_no, qsnt_state);
252 }
253
254 void
255 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
256 {
257 uint32_t qsnt_state;
258 struct qla_hw_data *ha = vha->hw;
259
260 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
261 qsnt_state &= ~(1 << ha->portnum);
262 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
263 ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
264 __func__, vha->host_no, qsnt_state);
265 }
266
267 /**
268 *
269 * qla8044_lock_recovery - Recovers the idc_lock.
270 * @ha : Pointer to adapter structure
271 *
272 * Lock Recovery Register
273 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
274 * valid if bits 1..0 are set by driver doing lock recovery.
275 * 1-0 1 - Driver intends to force unlock the IDC lock.
276 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
277 * this field after force unlocking the IDC lock.
278 *
279 * Lock Recovery process
280 * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
281 * greater than 0, then wait for the other driver to unlock otherwise
282 * move to the next step.
283 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
284 * register bits 1..0 and also set the function# in bits 5..2.
285 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
286 * Wait for the other driver to perform lock recovery if the function
287 * number in bits 5..2 has changed, otherwise move to the next step.
288 * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
289 * leaving your function# in bits 5..2.
290 * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
291 * the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
292 **/
293 static int
294 qla8044_lock_recovery(struct scsi_qla_host *vha)
295 {
296 uint32_t lock = 0, lockid;
297 struct qla_hw_data *ha = vha->hw;
298
299 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
300
301 /* Check for other Recovery in progress, go wait */
302 if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
303 return QLA_FUNCTION_FAILED;
304
305 /* Intent to Recover */
306 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
307 (ha->portnum <<
308 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
309 msleep(200);
310
311 /* Check Intent to Recover is advertised */
312 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
313 if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
314 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
315 return QLA_FUNCTION_FAILED;
316
317 ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
318 , __func__, ha->portnum);
319
320 /* Proceed to Recover */
321 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
322 (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
323 PROCEED_TO_RECOVER);
324
325 /* Force Unlock() */
326 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
327 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
328
329 /* Clear bits 0-5 in IDC_RECOVERY register*/
330 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
331
332 /* Get lock() */
333 lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
334 if (lock) {
335 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
336 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
337 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
338 return QLA_SUCCESS;
339 } else
340 return QLA_FUNCTION_FAILED;
341 }
342
343 int
344 qla8044_idc_lock(struct qla_hw_data *ha)
345 {
346 uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
347 uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
348 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
349
350 while (status == 0) {
351 /* acquire semaphore5 from PCI HW block */
352 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
353
354 if (status) {
355 /* Increment Counter (8-31) and update func_num (0-7) on
356 * getting a successful lock */
357 lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
358 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
359 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
360 break;
361 }
362
363 if (timeout == 0)
364 first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
365
366 if (++timeout >=
367 (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
368 tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
369 func_num = tmo_owner & 0xFF;
370 lock_cnt = tmo_owner >> 8;
371 ql_log(ql_log_warn, vha, 0xb114,
372 "%s: Lock by func %d failed after 2s, lock held "
373 "by func %d, lock count %d, first_owner %d\n",
374 __func__, ha->portnum, func_num, lock_cnt,
375 (first_owner & 0xFF));
376 if (first_owner != tmo_owner) {
377 /* Some other driver got lock,
378 * OR same driver got lock again (counter
379 * value changed), when we were waiting for
380 * lock. Retry for another 2 sec */
381 ql_dbg(ql_dbg_p3p, vha, 0xb115,
382 "%s: %d: IDC lock failed\n",
383 __func__, ha->portnum);
384 timeout = 0;
385 } else {
386 /* Same driver holding lock > 2sec.
387 * Force Recovery */
388 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
389 /* Recovered and got lock */
390 ret_val = QLA_SUCCESS;
391 ql_dbg(ql_dbg_p3p, vha, 0xb116,
392 "%s:IDC lock Recovery by %d"
393 "successful...\n", __func__,
394 ha->portnum);
395 }
396 /* Recovery Failed, some other function
397 * has the lock, wait for 2secs
398 * and retry
399 */
400 ql_dbg(ql_dbg_p3p, vha, 0xb08a,
401 "%s: IDC lock Recovery by %d "
402 "failed, Retrying timeout\n", __func__,
403 ha->portnum);
404 timeout = 0;
405 }
406 }
407 msleep(QLA8044_DRV_LOCK_MSLEEP);
408 }
409 return ret_val;
410 }
411
412 void
413 qla8044_idc_unlock(struct qla_hw_data *ha)
414 {
415 int id;
416 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
417
418 id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
419
420 if ((id & 0xFF) != ha->portnum) {
421 ql_log(ql_log_warn, vha, 0xb118,
422 "%s: IDC Unlock by %d failed, lock owner is %d!\n",
423 __func__, ha->portnum, (id & 0xFF));
424 return;
425 }
426
427 /* Keep lock counter value, update the ha->func_num to 0xFF */
428 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
429 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
430 }
431
432 /* 8044 Flash Lock/Unlock functions */
433 static int
434 qla8044_flash_lock(scsi_qla_host_t *vha)
435 {
436 int lock_owner;
437 int timeout = 0;
438 uint32_t lock_status = 0;
439 int ret_val = QLA_SUCCESS;
440 struct qla_hw_data *ha = vha->hw;
441
442 while (lock_status == 0) {
443 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
444 if (lock_status)
445 break;
446
447 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
448 lock_owner = qla8044_rd_reg(ha,
449 QLA8044_FLASH_LOCK_ID);
450 ql_log(ql_log_warn, vha, 0xb113,
451 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
452 __func__, ha->portnum, lock_owner);
453 ret_val = QLA_FUNCTION_FAILED;
454 break;
455 }
456 msleep(20);
457 }
458 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
459 return ret_val;
460 }
461
462 static void
463 qla8044_flash_unlock(scsi_qla_host_t *vha)
464 {
465 int ret_val;
466 struct qla_hw_data *ha = vha->hw;
467
468 /* Reading FLASH_UNLOCK register unlocks the Flash */
469 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
470 ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
471 }
472
473
474 static
475 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
476 {
477
478 if (qla8044_flash_lock(vha)) {
479 /* Someone else is holding the lock. */
480 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
481 }
482
483 /*
484 * Either we got the lock, or someone
485 * else died while holding it.
486 * In either case, unlock.
487 */
488 qla8044_flash_unlock(vha);
489 }
490
491 /*
492 * Address and length are byte address
493 */
494 static int
495 qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,
496 uint32_t flash_addr, int u32_word_count)
497 {
498 int i, ret_val = QLA_SUCCESS;
499 uint32_t u32_word;
500
501 if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
502 ret_val = QLA_FUNCTION_FAILED;
503 goto exit_lock_error;
504 }
505
506 if (flash_addr & 0x03) {
507 ql_log(ql_log_warn, vha, 0xb117,
508 "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
509 ret_val = QLA_FUNCTION_FAILED;
510 goto exit_flash_read;
511 }
512
513 for (i = 0; i < u32_word_count; i++) {
514 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
515 (flash_addr & 0xFFFF0000))) {
516 ql_log(ql_log_warn, vha, 0xb119,
517 "%s: failed to write addr 0x%x to "
518 "FLASH_DIRECT_WINDOW\n! ",
519 __func__, flash_addr);
520 ret_val = QLA_FUNCTION_FAILED;
521 goto exit_flash_read;
522 }
523
524 ret_val = qla8044_rd_reg_indirect(vha,
525 QLA8044_FLASH_DIRECT_DATA(flash_addr),
526 &u32_word);
527 if (ret_val != QLA_SUCCESS) {
528 ql_log(ql_log_warn, vha, 0xb08c,
529 "%s: failed to read addr 0x%x!\n",
530 __func__, flash_addr);
531 goto exit_flash_read;
532 }
533
534 *(uint32_t *)p_data = u32_word;
535 p_data = p_data + 4;
536 flash_addr = flash_addr + 4;
537 }
538
539 exit_flash_read:
540 qla8044_flash_unlock(vha);
541
542 exit_lock_error:
543 return ret_val;
544 }
545
546 /*
547 * Address and length are byte address
548 */
549 uint8_t *
550 qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
551 uint32_t offset, uint32_t length)
552 {
553 scsi_block_requests(vha->host);
554 if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
555 != QLA_SUCCESS) {
556 ql_log(ql_log_warn, vha, 0xb08d,
557 "%s: Failed to read from flash\n",
558 __func__);
559 }
560 scsi_unblock_requests(vha->host);
561 return buf;
562 }
563
564 inline int
565 qla8044_need_reset(struct scsi_qla_host *vha)
566 {
567 uint32_t drv_state, drv_active;
568 int rval;
569 struct qla_hw_data *ha = vha->hw;
570
571 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
572 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
573
574 rval = drv_state & (1 << ha->portnum);
575
576 if (ha->flags.eeh_busy && drv_active)
577 rval = 1;
578 return rval;
579 }
580
581 /*
582 * qla8044_write_list - Write the value (p_entry->arg2) to address specified
583 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
584 * entries.
585 *
586 * @vha : Pointer to adapter structure
587 * @p_hdr : reset_entry header for WRITE_LIST opcode.
588 *
589 */
590 static void
591 qla8044_write_list(struct scsi_qla_host *vha,
592 struct qla8044_reset_entry_hdr *p_hdr)
593 {
594 struct qla8044_entry *p_entry;
595 uint32_t i;
596
597 p_entry = (struct qla8044_entry *)((char *)p_hdr +
598 sizeof(struct qla8044_reset_entry_hdr));
599
600 for (i = 0; i < p_hdr->count; i++, p_entry++) {
601 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
602 if (p_hdr->delay)
603 udelay((uint32_t)(p_hdr->delay));
604 }
605 }
606
607 /*
608 * qla8044_read_write_list - Read from address specified by p_entry->arg1,
609 * write value read to address specified by p_entry->arg2, for all entries in
610 * header with delay of p_hdr->delay between entries.
611 *
612 * @vha : Pointer to adapter structure
613 * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
614 *
615 */
616 static void
617 qla8044_read_write_list(struct scsi_qla_host *vha,
618 struct qla8044_reset_entry_hdr *p_hdr)
619 {
620 struct qla8044_entry *p_entry;
621 uint32_t i;
622
623 p_entry = (struct qla8044_entry *)((char *)p_hdr +
624 sizeof(struct qla8044_reset_entry_hdr));
625
626 for (i = 0; i < p_hdr->count; i++, p_entry++) {
627 qla8044_read_write_crb_reg(vha, p_entry->arg1,
628 p_entry->arg2);
629 if (p_hdr->delay)
630 udelay((uint32_t)(p_hdr->delay));
631 }
632 }
633
634 /*
635 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
636 * value read ANDed with test_mask is equal to test_result.
637 *
638 * @ha : Pointer to adapter structure
639 * @addr : CRB register address
640 * @duration : Poll for total of "duration" msecs
641 * @test_mask : Mask value read with "test_mask"
642 * @test_result : Compare (value&test_mask) with test_result.
643 *
644 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
645 */
646 static int
647 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
648 int duration, uint32_t test_mask, uint32_t test_result)
649 {
650 uint32_t value;
651 int timeout_error;
652 uint8_t retries;
653 int ret_val = QLA_SUCCESS;
654
655 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
656 if (ret_val == QLA_FUNCTION_FAILED) {
657 timeout_error = 1;
658 goto exit_poll_reg;
659 }
660
661 /* poll every 1/10 of the total duration */
662 retries = duration/10;
663
664 do {
665 if ((value & test_mask) != test_result) {
666 timeout_error = 1;
667 msleep(duration/10);
668 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
669 if (ret_val == QLA_FUNCTION_FAILED) {
670 timeout_error = 1;
671 goto exit_poll_reg;
672 }
673 } else {
674 timeout_error = 0;
675 break;
676 }
677 } while (retries--);
678
679 exit_poll_reg:
680 if (timeout_error) {
681 vha->reset_tmplt.seq_error++;
682 ql_log(ql_log_fatal, vha, 0xb090,
683 "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
684 __func__, value, test_mask, test_result);
685 }
686
687 return timeout_error;
688 }
689
690 /*
691 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
692 * register specified by p_entry->arg1 and compare (value AND test_mask) with
693 * test_result to validate it. Wait for p_hdr->delay between processing entries.
694 *
695 * @ha : Pointer to adapter structure
696 * @p_hdr : reset_entry header for POLL_LIST opcode.
697 *
698 */
699 static void
700 qla8044_poll_list(struct scsi_qla_host *vha,
701 struct qla8044_reset_entry_hdr *p_hdr)
702 {
703 long delay;
704 struct qla8044_entry *p_entry;
705 struct qla8044_poll *p_poll;
706 uint32_t i;
707 uint32_t value;
708
709 p_poll = (struct qla8044_poll *)
710 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
711
712 /* Entries start after 8 byte qla8044_poll, poll header contains
713 * the test_mask, test_value.
714 */
715 p_entry = (struct qla8044_entry *)((char *)p_poll +
716 sizeof(struct qla8044_poll));
717
718 delay = (long)p_hdr->delay;
719
720 if (!delay) {
721 for (i = 0; i < p_hdr->count; i++, p_entry++)
722 qla8044_poll_reg(vha, p_entry->arg1,
723 delay, p_poll->test_mask, p_poll->test_value);
724 } else {
725 for (i = 0; i < p_hdr->count; i++, p_entry++) {
726 if (delay) {
727 if (qla8044_poll_reg(vha,
728 p_entry->arg1, delay,
729 p_poll->test_mask,
730 p_poll->test_value)) {
731 /*If
732 * (data_read&test_mask != test_value)
733 * read TIMEOUT_ADDR (arg1) and
734 * ADDR (arg2) registers
735 */
736 qla8044_rd_reg_indirect(vha,
737 p_entry->arg1, &value);
738 qla8044_rd_reg_indirect(vha,
739 p_entry->arg2, &value);
740 }
741 }
742 }
743 }
744 }
745
746 /*
747 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
748 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
749 * expires.
750 *
751 * @vha : Pointer to adapter structure
752 * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
753 *
754 */
755 static void
756 qla8044_poll_write_list(struct scsi_qla_host *vha,
757 struct qla8044_reset_entry_hdr *p_hdr)
758 {
759 long delay;
760 struct qla8044_quad_entry *p_entry;
761 struct qla8044_poll *p_poll;
762 uint32_t i;
763
764 p_poll = (struct qla8044_poll *)((char *)p_hdr +
765 sizeof(struct qla8044_reset_entry_hdr));
766
767 p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
768 sizeof(struct qla8044_poll));
769
770 delay = (long)p_hdr->delay;
771
772 for (i = 0; i < p_hdr->count; i++, p_entry++) {
773 qla8044_wr_reg_indirect(vha,
774 p_entry->dr_addr, p_entry->dr_value);
775 qla8044_wr_reg_indirect(vha,
776 p_entry->ar_addr, p_entry->ar_value);
777 if (delay) {
778 if (qla8044_poll_reg(vha,
779 p_entry->ar_addr, delay,
780 p_poll->test_mask,
781 p_poll->test_value)) {
782 ql_dbg(ql_dbg_p3p, vha, 0xb091,
783 "%s: Timeout Error: poll list, ",
784 __func__);
785 ql_dbg(ql_dbg_p3p, vha, 0xb092,
786 "item_num %d, entry_num %d\n", i,
787 vha->reset_tmplt.seq_index);
788 }
789 }
790 }
791 }
792
793 /*
794 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
795 * value, write value to p_entry->arg2. Process entries with p_hdr->delay
796 * between entries.
797 *
798 * @vha : Pointer to adapter structure
799 * @p_hdr : header with shift/or/xor values.
800 *
801 */
802 static void
803 qla8044_read_modify_write(struct scsi_qla_host *vha,
804 struct qla8044_reset_entry_hdr *p_hdr)
805 {
806 struct qla8044_entry *p_entry;
807 struct qla8044_rmw *p_rmw_hdr;
808 uint32_t i;
809
810 p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
811 sizeof(struct qla8044_reset_entry_hdr));
812
813 p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
814 sizeof(struct qla8044_rmw));
815
816 for (i = 0; i < p_hdr->count; i++, p_entry++) {
817 qla8044_rmw_crb_reg(vha, p_entry->arg1,
818 p_entry->arg2, p_rmw_hdr);
819 if (p_hdr->delay)
820 udelay((uint32_t)(p_hdr->delay));
821 }
822 }
823
824 /*
825 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
826 * two entries of a sequence.
827 *
828 * @vha : Pointer to adapter structure
829 * @p_hdr : Common reset entry header.
830 *
831 */
832 static
833 void qla8044_pause(struct scsi_qla_host *vha,
834 struct qla8044_reset_entry_hdr *p_hdr)
835 {
836 if (p_hdr->delay)
837 mdelay((uint32_t)((long)p_hdr->delay));
838 }
839
840 /*
841 * qla8044_template_end - Indicates end of reset sequence processing.
842 *
843 * @vha : Pointer to adapter structure
844 * @p_hdr : Common reset entry header.
845 *
846 */
847 static void
848 qla8044_template_end(struct scsi_qla_host *vha,
849 struct qla8044_reset_entry_hdr *p_hdr)
850 {
851 vha->reset_tmplt.template_end = 1;
852
853 if (vha->reset_tmplt.seq_error == 0) {
854 ql_dbg(ql_dbg_p3p, vha, 0xb093,
855 "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
856 } else {
857 ql_log(ql_log_fatal, vha, 0xb094,
858 "%s: Reset sequence completed with some timeout "
859 "errors.\n", __func__);
860 }
861 }
862
863 /*
864 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
865 * if (value & test_mask != test_value) re-read till timeout value expires,
866 * read dr_addr register and assign to reset_tmplt.array.
867 *
868 * @vha : Pointer to adapter structure
869 * @p_hdr : Common reset entry header.
870 *
871 */
872 static void
873 qla8044_poll_read_list(struct scsi_qla_host *vha,
874 struct qla8044_reset_entry_hdr *p_hdr)
875 {
876 long delay;
877 int index;
878 struct qla8044_quad_entry *p_entry;
879 struct qla8044_poll *p_poll;
880 uint32_t i;
881 uint32_t value;
882
883 p_poll = (struct qla8044_poll *)
884 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
885
886 p_entry = (struct qla8044_quad_entry *)
887 ((char *)p_poll + sizeof(struct qla8044_poll));
888
889 delay = (long)p_hdr->delay;
890
891 for (i = 0; i < p_hdr->count; i++, p_entry++) {
892 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
893 p_entry->ar_value);
894 if (delay) {
895 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
896 p_poll->test_mask, p_poll->test_value)) {
897 ql_dbg(ql_dbg_p3p, vha, 0xb095,
898 "%s: Timeout Error: poll "
899 "list, ", __func__);
900 ql_dbg(ql_dbg_p3p, vha, 0xb096,
901 "Item_num %d, "
902 "entry_num %d\n", i,
903 vha->reset_tmplt.seq_index);
904 } else {
905 index = vha->reset_tmplt.array_index;
906 qla8044_rd_reg_indirect(vha,
907 p_entry->dr_addr, &value);
908 vha->reset_tmplt.array[index++] = value;
909 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
910 vha->reset_tmplt.array_index = 1;
911 }
912 }
913 }
914 }
915
916 /*
917 * qla8031_process_reset_template - Process all entries in reset template
918 * till entry with SEQ_END opcode, which indicates end of the reset template
919 * processing. Each entry has a Reset Entry header, entry opcode/command, with
920 * size of the entry, number of entries in sub-sequence and delay in microsecs
921 * or timeout in millisecs.
922 *
923 * @ha : Pointer to adapter structure
924 * @p_buff : Common reset entry header.
925 *
926 */
927 static void
928 qla8044_process_reset_template(struct scsi_qla_host *vha,
929 char *p_buff)
930 {
931 int index, entries;
932 struct qla8044_reset_entry_hdr *p_hdr;
933 char *p_entry = p_buff;
934
935 vha->reset_tmplt.seq_end = 0;
936 vha->reset_tmplt.template_end = 0;
937 entries = vha->reset_tmplt.hdr->entries;
938 index = vha->reset_tmplt.seq_index;
939
940 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) {
941 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
942 switch (p_hdr->cmd) {
943 case OPCODE_NOP:
944 break;
945 case OPCODE_WRITE_LIST:
946 qla8044_write_list(vha, p_hdr);
947 break;
948 case OPCODE_READ_WRITE_LIST:
949 qla8044_read_write_list(vha, p_hdr);
950 break;
951 case OPCODE_POLL_LIST:
952 qla8044_poll_list(vha, p_hdr);
953 break;
954 case OPCODE_POLL_WRITE_LIST:
955 qla8044_poll_write_list(vha, p_hdr);
956 break;
957 case OPCODE_READ_MODIFY_WRITE:
958 qla8044_read_modify_write(vha, p_hdr);
959 break;
960 case OPCODE_SEQ_PAUSE:
961 qla8044_pause(vha, p_hdr);
962 break;
963 case OPCODE_SEQ_END:
964 vha->reset_tmplt.seq_end = 1;
965 break;
966 case OPCODE_TMPL_END:
967 qla8044_template_end(vha, p_hdr);
968 break;
969 case OPCODE_POLL_READ_LIST:
970 qla8044_poll_read_list(vha, p_hdr);
971 break;
972 default:
973 ql_log(ql_log_fatal, vha, 0xb097,
974 "%s: Unknown command ==> 0x%04x on "
975 "entry = %d\n", __func__, p_hdr->cmd, index);
976 break;
977 }
978 /*
979 *Set pointer to next entry in the sequence.
980 */
981 p_entry += p_hdr->size;
982 }
983 vha->reset_tmplt.seq_index = index;
984 }
985
986 static void
987 qla8044_process_init_seq(struct scsi_qla_host *vha)
988 {
989 qla8044_process_reset_template(vha,
990 vha->reset_tmplt.init_offset);
991 if (vha->reset_tmplt.seq_end != 1)
992 ql_log(ql_log_fatal, vha, 0xb098,
993 "%s: Abrupt INIT Sub-Sequence end.\n",
994 __func__);
995 }
996
997 static void
998 qla8044_process_stop_seq(struct scsi_qla_host *vha)
999 {
1000 vha->reset_tmplt.seq_index = 0;
1001 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
1002 if (vha->reset_tmplt.seq_end != 1)
1003 ql_log(ql_log_fatal, vha, 0xb099,
1004 "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
1005 }
1006
1007 static void
1008 qla8044_process_start_seq(struct scsi_qla_host *vha)
1009 {
1010 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
1011 if (vha->reset_tmplt.template_end != 1)
1012 ql_log(ql_log_fatal, vha, 0xb09a,
1013 "%s: Abrupt START Sub-Sequence end.\n",
1014 __func__);
1015 }
1016
1017 static int
1018 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
1019 uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
1020 {
1021 uint32_t i;
1022 uint32_t u32_word;
1023 uint32_t flash_offset;
1024 uint32_t addr = flash_addr;
1025 int ret_val = QLA_SUCCESS;
1026
1027 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
1028
1029 if (addr & 0x3) {
1030 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
1031 __func__, addr);
1032 ret_val = QLA_FUNCTION_FAILED;
1033 goto exit_lockless_read;
1034 }
1035
1036 ret_val = qla8044_wr_reg_indirect(vha,
1037 QLA8044_FLASH_DIRECT_WINDOW, (addr));
1038
1039 if (ret_val != QLA_SUCCESS) {
1040 ql_log(ql_log_fatal, vha, 0xb09c,
1041 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
1042 __func__, addr);
1043 goto exit_lockless_read;
1044 }
1045
1046 /* Check if data is spread across multiple sectors */
1047 if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
1048 (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1049 /* Multi sector read */
1050 for (i = 0; i < u32_word_count; i++) {
1051 ret_val = qla8044_rd_reg_indirect(vha,
1052 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1053 if (ret_val != QLA_SUCCESS) {
1054 ql_log(ql_log_fatal, vha, 0xb09d,
1055 "%s: failed to read addr 0x%x!\n",
1056 __func__, addr);
1057 goto exit_lockless_read;
1058 }
1059 *(uint32_t *)p_data = u32_word;
1060 p_data = p_data + 4;
1061 addr = addr + 4;
1062 flash_offset = flash_offset + 4;
1063 if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
1064 /* This write is needed once for each sector */
1065 ret_val = qla8044_wr_reg_indirect(vha,
1066 QLA8044_FLASH_DIRECT_WINDOW, (addr));
1067 if (ret_val != QLA_SUCCESS) {
1068 ql_log(ql_log_fatal, vha, 0xb09f,
1069 "%s: failed to write addr "
1070 "0x%x to FLASH_DIRECT_WINDOW!\n",
1071 __func__, addr);
1072 goto exit_lockless_read;
1073 }
1074 flash_offset = 0;
1075 }
1076 }
1077 } else {
1078 /* Single sector read */
1079 for (i = 0; i < u32_word_count; i++) {
1080 ret_val = qla8044_rd_reg_indirect(vha,
1081 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1082 if (ret_val != QLA_SUCCESS) {
1083 ql_log(ql_log_fatal, vha, 0xb0a0,
1084 "%s: failed to read addr 0x%x!\n",
1085 __func__, addr);
1086 goto exit_lockless_read;
1087 }
1088 *(uint32_t *)p_data = u32_word;
1089 p_data = p_data + 4;
1090 addr = addr + 4;
1091 }
1092 }
1093
1094 exit_lockless_read:
1095 return ret_val;
1096 }
1097
1098 /*
1099 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1100 *
1101 * @vha : Pointer to adapter structure
1102 * addr : Flash address to write to
1103 * data : Data to be written
1104 * count : word_count to be written
1105 *
1106 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1107 */
1108 static int
1109 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1110 uint64_t addr, uint32_t *data, uint32_t count)
1111 {
1112 int i, j, ret_val = QLA_SUCCESS;
1113 uint32_t agt_ctrl;
1114 unsigned long flags;
1115 struct qla_hw_data *ha = vha->hw;
1116
1117 /* Only 128-bit aligned access */
1118 if (addr & 0xF) {
1119 ret_val = QLA_FUNCTION_FAILED;
1120 goto exit_ms_mem_write;
1121 }
1122 write_lock_irqsave(&ha->hw_lock, flags);
1123
1124 /* Write address */
1125 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1126 if (ret_val == QLA_FUNCTION_FAILED) {
1127 ql_log(ql_log_fatal, vha, 0xb0a1,
1128 "%s: write to AGT_ADDR_HI failed!\n", __func__);
1129 goto exit_ms_mem_write_unlock;
1130 }
1131
1132 for (i = 0; i < count; i++, addr += 16) {
1133 if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET,
1134 QLA8044_ADDR_QDR_NET_MAX)) ||
1135 (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET,
1136 QLA8044_ADDR_DDR_NET_MAX)))) {
1137 ret_val = QLA_FUNCTION_FAILED;
1138 goto exit_ms_mem_write_unlock;
1139 }
1140
1141 ret_val = qla8044_wr_reg_indirect(vha,
1142 MD_MIU_TEST_AGT_ADDR_LO, addr);
1143
1144 /* Write data */
1145 ret_val += qla8044_wr_reg_indirect(vha,
1146 MD_MIU_TEST_AGT_WRDATA_LO, *data++);
1147 ret_val += qla8044_wr_reg_indirect(vha,
1148 MD_MIU_TEST_AGT_WRDATA_HI, *data++);
1149 ret_val += qla8044_wr_reg_indirect(vha,
1150 MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
1151 ret_val += qla8044_wr_reg_indirect(vha,
1152 MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
1153 if (ret_val == QLA_FUNCTION_FAILED) {
1154 ql_log(ql_log_fatal, vha, 0xb0a2,
1155 "%s: write to AGT_WRDATA failed!\n",
1156 __func__);
1157 goto exit_ms_mem_write_unlock;
1158 }
1159
1160 /* Check write status */
1161 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1162 MIU_TA_CTL_WRITE_ENABLE);
1163 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1164 MIU_TA_CTL_WRITE_START);
1165 if (ret_val == QLA_FUNCTION_FAILED) {
1166 ql_log(ql_log_fatal, vha, 0xb0a3,
1167 "%s: write to AGT_CTRL failed!\n", __func__);
1168 goto exit_ms_mem_write_unlock;
1169 }
1170
1171 for (j = 0; j < MAX_CTL_CHECK; j++) {
1172 ret_val = qla8044_rd_reg_indirect(vha,
1173 MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
1174 if (ret_val == QLA_FUNCTION_FAILED) {
1175 ql_log(ql_log_fatal, vha, 0xb0a4,
1176 "%s: failed to read "
1177 "MD_MIU_TEST_AGT_CTRL!\n", __func__);
1178 goto exit_ms_mem_write_unlock;
1179 }
1180 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1181 break;
1182 }
1183
1184 /* Status check failed */
1185 if (j >= MAX_CTL_CHECK) {
1186 ql_log(ql_log_fatal, vha, 0xb0a5,
1187 "%s: MS memory write failed!\n",
1188 __func__);
1189 ret_val = QLA_FUNCTION_FAILED;
1190 goto exit_ms_mem_write_unlock;
1191 }
1192 }
1193
1194 exit_ms_mem_write_unlock:
1195 write_unlock_irqrestore(&ha->hw_lock, flags);
1196
1197 exit_ms_mem_write:
1198 return ret_val;
1199 }
1200
1201 static int
1202 qla8044_copy_bootloader(struct scsi_qla_host *vha)
1203 {
1204 uint8_t *p_cache;
1205 uint32_t src, count, size;
1206 uint64_t dest;
1207 int ret_val = QLA_SUCCESS;
1208 struct qla_hw_data *ha = vha->hw;
1209
1210 src = QLA8044_BOOTLOADER_FLASH_ADDR;
1211 dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
1212 size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
1213
1214 /* 128 bit alignment check */
1215 if (size & 0xF)
1216 size = (size + 16) & ~0xF;
1217
1218 /* 16 byte count */
1219 count = size/16;
1220
1221 p_cache = vmalloc(size);
1222 if (p_cache == NULL) {
1223 ql_log(ql_log_fatal, vha, 0xb0a6,
1224 "%s: Failed to allocate memory for "
1225 "boot loader cache\n", __func__);
1226 ret_val = QLA_FUNCTION_FAILED;
1227 goto exit_copy_bootloader;
1228 }
1229
1230 ret_val = qla8044_lockless_flash_read_u32(vha, src,
1231 p_cache, size/sizeof(uint32_t));
1232 if (ret_val == QLA_FUNCTION_FAILED) {
1233 ql_log(ql_log_fatal, vha, 0xb0a7,
1234 "%s: Error reading F/W from flash!!!\n", __func__);
1235 goto exit_copy_error;
1236 }
1237 ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1238 __func__);
1239
1240 /* 128 bit/16 byte write to MS memory */
1241 ret_val = qla8044_ms_mem_write_128b(vha, dest,
1242 (uint32_t *)p_cache, count);
1243 if (ret_val == QLA_FUNCTION_FAILED) {
1244 ql_log(ql_log_fatal, vha, 0xb0a9,
1245 "%s: Error writing F/W to MS !!!\n", __func__);
1246 goto exit_copy_error;
1247 }
1248 ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1249 "%s: Wrote F/W (size %d) to MS !!!\n",
1250 __func__, size);
1251
1252 exit_copy_error:
1253 vfree(p_cache);
1254
1255 exit_copy_bootloader:
1256 return ret_val;
1257 }
1258
1259 static int
1260 qla8044_restart(struct scsi_qla_host *vha)
1261 {
1262 int ret_val = QLA_SUCCESS;
1263 struct qla_hw_data *ha = vha->hw;
1264
1265 qla8044_process_stop_seq(vha);
1266
1267 /* Collect minidump */
1268 if (ql2xmdenable)
1269 qla8044_get_minidump(vha);
1270 else
1271 ql_log(ql_log_fatal, vha, 0xb14c,
1272 "Minidump disabled.\n");
1273
1274 qla8044_process_init_seq(vha);
1275
1276 if (qla8044_copy_bootloader(vha)) {
1277 ql_log(ql_log_fatal, vha, 0xb0ab,
1278 "%s: Copy bootloader, firmware restart failed!\n",
1279 __func__);
1280 ret_val = QLA_FUNCTION_FAILED;
1281 goto exit_restart;
1282 }
1283
1284 /*
1285 * Loads F/W from flash
1286 */
1287 qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
1288
1289 qla8044_process_start_seq(vha);
1290
1291 exit_restart:
1292 return ret_val;
1293 }
1294
1295 /*
1296 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1297 * initialized.
1298 *
1299 * @ha : Pointer to adapter structure
1300 *
1301 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1302 */
1303 static int
1304 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1305 {
1306 uint32_t val, ret_val = QLA_FUNCTION_FAILED;
1307 int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
1308 struct qla_hw_data *ha = vha->hw;
1309
1310 do {
1311 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
1312 if (val == PHAN_INITIALIZE_COMPLETE) {
1313 ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1314 "%s: Command Peg initialization "
1315 "complete! state=0x%x\n", __func__, val);
1316 ret_val = QLA_SUCCESS;
1317 break;
1318 }
1319 msleep(CRB_CMDPEG_CHECK_DELAY);
1320 } while (--retries);
1321
1322 return ret_val;
1323 }
1324
1325 static int
1326 qla8044_start_firmware(struct scsi_qla_host *vha)
1327 {
1328 int ret_val = QLA_SUCCESS;
1329
1330 if (qla8044_restart(vha)) {
1331 ql_log(ql_log_fatal, vha, 0xb0ad,
1332 "%s: Restart Error!!!, Need Reset!!!\n",
1333 __func__);
1334 ret_val = QLA_FUNCTION_FAILED;
1335 goto exit_start_fw;
1336 } else
1337 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1338 "%s: Restart done!\n", __func__);
1339
1340 ret_val = qla8044_check_cmd_peg_status(vha);
1341 if (ret_val) {
1342 ql_log(ql_log_fatal, vha, 0xb0b0,
1343 "%s: Peg not initialized!\n", __func__);
1344 ret_val = QLA_FUNCTION_FAILED;
1345 }
1346
1347 exit_start_fw:
1348 return ret_val;
1349 }
1350
1351 void
1352 qla8044_clear_drv_active(struct qla_hw_data *ha)
1353 {
1354 uint32_t drv_active;
1355 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
1356
1357 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1358 drv_active &= ~(1 << (ha->portnum));
1359
1360 ql_log(ql_log_info, vha, 0xb0b1,
1361 "%s(%ld): drv_active: 0x%08x\n",
1362 __func__, vha->host_no, drv_active);
1363
1364 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1365 }
1366
1367 /*
1368 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1369 * @ha: pointer to adapter structure
1370 *
1371 * Note: IDC lock must be held upon entry
1372 **/
1373 static int
1374 qla8044_device_bootstrap(struct scsi_qla_host *vha)
1375 {
1376 int rval = QLA_FUNCTION_FAILED;
1377 int i;
1378 uint32_t old_count = 0, count = 0;
1379 int need_reset = 0;
1380 uint32_t idc_ctrl;
1381 struct qla_hw_data *ha = vha->hw;
1382
1383 need_reset = qla8044_need_reset(vha);
1384
1385 if (!need_reset) {
1386 old_count = qla8044_rd_direct(vha,
1387 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1388
1389 for (i = 0; i < 10; i++) {
1390 msleep(200);
1391
1392 count = qla8044_rd_direct(vha,
1393 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1394 if (count != old_count) {
1395 rval = QLA_SUCCESS;
1396 goto dev_ready;
1397 }
1398 }
1399 qla8044_flash_lock_recovery(vha);
1400 } else {
1401 /* We are trying to perform a recovery here. */
1402 if (ha->flags.isp82xx_fw_hung)
1403 qla8044_flash_lock_recovery(vha);
1404 }
1405
1406 /* set to DEV_INITIALIZING */
1407 ql_log(ql_log_info, vha, 0xb0b2,
1408 "%s: HW State: INITIALIZING\n", __func__);
1409 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1410 QLA8XXX_DEV_INITIALIZING);
1411
1412 qla8044_idc_unlock(ha);
1413 rval = qla8044_start_firmware(vha);
1414 qla8044_idc_lock(ha);
1415
1416 if (rval != QLA_SUCCESS) {
1417 ql_log(ql_log_info, vha, 0xb0b3,
1418 "%s: HW State: FAILED\n", __func__);
1419 qla8044_clear_drv_active(ha);
1420 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1421 QLA8XXX_DEV_FAILED);
1422 return rval;
1423 }
1424
1425 /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1426 * device goes to INIT state. */
1427 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1428 if (idc_ctrl & GRACEFUL_RESET_BIT1) {
1429 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
1430 (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1431 ha->fw_dumped = 0;
1432 }
1433
1434 dev_ready:
1435 ql_log(ql_log_info, vha, 0xb0b4,
1436 "%s: HW State: READY\n", __func__);
1437 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1438
1439 return rval;
1440 }
1441
1442 /*-------------------------Reset Sequence Functions-----------------------*/
1443 static void
1444 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1445 {
1446 u8 *phdr;
1447
1448 if (!vha->reset_tmplt.buff) {
1449 ql_log(ql_log_fatal, vha, 0xb0b5,
1450 "%s: Error Invalid reset_seq_template\n", __func__);
1451 return;
1452 }
1453
1454 phdr = vha->reset_tmplt.buff;
1455 ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1456 "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1457 "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1458 "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1459 *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
1460 *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
1461 *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
1462 *(phdr+13), *(phdr+14), *(phdr+15));
1463 }
1464
1465 /*
1466 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1467 *
1468 * @ha : Pointer to adapter structure
1469 *
1470 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1471 */
1472 static int
1473 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1474 {
1475 uint32_t sum = 0;
1476 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1477 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1478
1479 while (u16_count-- > 0)
1480 sum += *buff++;
1481
1482 while (sum >> 16)
1483 sum = (sum & 0xFFFF) + (sum >> 16);
1484
1485 /* checksum of 0 indicates a valid template */
1486 if (~sum) {
1487 return QLA_SUCCESS;
1488 } else {
1489 ql_log(ql_log_fatal, vha, 0xb0b7,
1490 "%s: Reset seq checksum failed\n", __func__);
1491 return QLA_FUNCTION_FAILED;
1492 }
1493 }
1494
1495 /*
1496 * qla8044_read_reset_template - Read Reset Template from Flash, validate
1497 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1498 *
1499 * @ha : Pointer to adapter structure
1500 */
1501 void
1502 qla8044_read_reset_template(struct scsi_qla_host *vha)
1503 {
1504 uint8_t *p_buff;
1505 uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1506
1507 vha->reset_tmplt.seq_error = 0;
1508 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1509 if (vha->reset_tmplt.buff == NULL) {
1510 ql_log(ql_log_fatal, vha, 0xb0b8,
1511 "%s: Failed to allocate reset template resources\n",
1512 __func__);
1513 goto exit_read_reset_template;
1514 }
1515
1516 p_buff = vha->reset_tmplt.buff;
1517 addr = QLA8044_RESET_TEMPLATE_ADDR;
1518
1519 tmplt_hdr_def_size =
1520 sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
1521
1522 ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1523 "%s: Read template hdr size %d from Flash\n",
1524 __func__, tmplt_hdr_def_size);
1525
1526 /* Copy template header from flash */
1527 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1528 ql_log(ql_log_fatal, vha, 0xb0ba,
1529 "%s: Failed to read reset template\n", __func__);
1530 goto exit_read_template_error;
1531 }
1532
1533 vha->reset_tmplt.hdr =
1534 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1535
1536 /* Validate the template header size and signature */
1537 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1538 if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
1539 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1540 ql_log(ql_log_fatal, vha, 0xb0bb,
1541 "%s: Template Header size invalid %d "
1542 "tmplt_hdr_def_size %d!!!\n", __func__,
1543 tmplt_hdr_size, tmplt_hdr_def_size);
1544 goto exit_read_template_error;
1545 }
1546
1547 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1548 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1549 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1550 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1551
1552 ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1553 "%s: Read rest of the template size %d\n",
1554 __func__, vha->reset_tmplt.hdr->size);
1555
1556 /* Copy rest of the template */
1557 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1558 ql_log(ql_log_fatal, vha, 0xb0bd,
1559 "%s: Failed to read reset tempelate\n", __func__);
1560 goto exit_read_template_error;
1561 }
1562
1563 /* Integrity check */
1564 if (qla8044_reset_seq_checksum_test(vha)) {
1565 ql_log(ql_log_fatal, vha, 0xb0be,
1566 "%s: Reset Seq checksum failed!\n", __func__);
1567 goto exit_read_template_error;
1568 }
1569
1570 ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1571 "%s: Reset Seq checksum passed! Get stop, "
1572 "start and init seq offsets\n", __func__);
1573
1574 /* Get STOP, START, INIT sequence offsets */
1575 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1576 vha->reset_tmplt.hdr->init_seq_offset;
1577
1578 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1579 vha->reset_tmplt.hdr->start_seq_offset;
1580
1581 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1582 vha->reset_tmplt.hdr->hdr_size;
1583
1584 qla8044_dump_reset_seq_hdr(vha);
1585
1586 goto exit_read_reset_template;
1587
1588 exit_read_template_error:
1589 vfree(vha->reset_tmplt.buff);
1590
1591 exit_read_reset_template:
1592 return;
1593 }
1594
1595 void
1596 qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1597 {
1598 uint32_t idc_ctrl;
1599 struct qla_hw_data *ha = vha->hw;
1600
1601 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1602 idc_ctrl |= DONTRESET_BIT0;
1603 ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1604 "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
1605 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1606 }
1607
1608 inline void
1609 qla8044_set_rst_ready(struct scsi_qla_host *vha)
1610 {
1611 uint32_t drv_state;
1612 struct qla_hw_data *ha = vha->hw;
1613
1614 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1615
1616 /* For ISP8044, drv_active register has 1 bit per function,
1617 * shift 1 by func_num to set a bit for the function.*/
1618 drv_state |= (1 << ha->portnum);
1619
1620 ql_log(ql_log_info, vha, 0xb0c1,
1621 "%s(%ld): drv_state: 0x%08x\n",
1622 __func__, vha->host_no, drv_state);
1623 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1624 }
1625
1626 /**
1627 * qla8044_need_reset_handler - Code to start reset sequence
1628 * @ha: pointer to adapter structure
1629 *
1630 * Note: IDC lock must be held upon entry
1631 **/
1632 static void
1633 qla8044_need_reset_handler(struct scsi_qla_host *vha)
1634 {
1635 uint32_t dev_state = 0, drv_state, drv_active;
1636 unsigned long reset_timeout;
1637 struct qla_hw_data *ha = vha->hw;
1638
1639 ql_log(ql_log_fatal, vha, 0xb0c2,
1640 "%s: Performing ISP error recovery\n", __func__);
1641
1642 if (vha->flags.online) {
1643 qla8044_idc_unlock(ha);
1644 qla2x00_abort_isp_cleanup(vha);
1645 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1646 ha->isp_ops->nvram_config(vha);
1647 qla8044_idc_lock(ha);
1648 }
1649
1650 dev_state = qla8044_rd_direct(vha,
1651 QLA8044_CRB_DEV_STATE_INDEX);
1652 drv_state = qla8044_rd_direct(vha,
1653 QLA8044_CRB_DRV_STATE_INDEX);
1654 drv_active = qla8044_rd_direct(vha,
1655 QLA8044_CRB_DRV_ACTIVE_INDEX);
1656
1657 ql_log(ql_log_info, vha, 0xb0c5,
1658 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x dev_state = 0x%x\n",
1659 __func__, vha->host_no, drv_state, drv_active, dev_state);
1660
1661 qla8044_set_rst_ready(vha);
1662
1663 /* wait for 10 seconds for reset ack from all functions */
1664 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1665
1666 do {
1667 if (time_after_eq(jiffies, reset_timeout)) {
1668 ql_log(ql_log_info, vha, 0xb0c4,
1669 "%s: Function %d: Reset Ack Timeout!, drv_state: 0x%08x, drv_active: 0x%08x\n",
1670 __func__, ha->portnum, drv_state, drv_active);
1671 break;
1672 }
1673
1674 qla8044_idc_unlock(ha);
1675 msleep(1000);
1676 qla8044_idc_lock(ha);
1677
1678 dev_state = qla8044_rd_direct(vha,
1679 QLA8044_CRB_DEV_STATE_INDEX);
1680 drv_state = qla8044_rd_direct(vha,
1681 QLA8044_CRB_DRV_STATE_INDEX);
1682 drv_active = qla8044_rd_direct(vha,
1683 QLA8044_CRB_DRV_ACTIVE_INDEX);
1684 } while (((drv_state & drv_active) != drv_active) &&
1685 (dev_state == QLA8XXX_DEV_NEED_RESET));
1686
1687 /* Remove IDC participation of functions not acknowledging */
1688 if (drv_state != drv_active) {
1689 ql_log(ql_log_info, vha, 0xb0c7,
1690 "%s(%ld): Function %d turning off drv_active of non-acking function 0x%x\n",
1691 __func__, vha->host_no, ha->portnum,
1692 (drv_active ^ drv_state));
1693 drv_active = drv_active & drv_state;
1694 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1695 drv_active);
1696 } else {
1697 /*
1698 * Reset owner should execute reset recovery,
1699 * if all functions acknowledged
1700 */
1701 if ((ha->flags.nic_core_reset_owner) &&
1702 (dev_state == QLA8XXX_DEV_NEED_RESET)) {
1703 ha->flags.nic_core_reset_owner = 0;
1704 qla8044_device_bootstrap(vha);
1705 return;
1706 }
1707 }
1708
1709 /* Exit if non active function */
1710 if (!(drv_active & (1 << ha->portnum))) {
1711 ha->flags.nic_core_reset_owner = 0;
1712 return;
1713 }
1714
1715 /*
1716 * Execute Reset Recovery if Reset Owner or Function 7
1717 * is the only active function
1718 */
1719 if (ha->flags.nic_core_reset_owner ||
1720 ((drv_state & drv_active) == QLA8044_FUN7_ACTIVE_INDEX)) {
1721 ha->flags.nic_core_reset_owner = 0;
1722 qla8044_device_bootstrap(vha);
1723 }
1724 }
1725
1726 static void
1727 qla8044_set_drv_active(struct scsi_qla_host *vha)
1728 {
1729 uint32_t drv_active;
1730 struct qla_hw_data *ha = vha->hw;
1731
1732 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1733
1734 /* For ISP8044, drv_active register has 1 bit per function,
1735 * shift 1 by func_num to set a bit for the function.*/
1736 drv_active |= (1 << ha->portnum);
1737
1738 ql_log(ql_log_info, vha, 0xb0c8,
1739 "%s(%ld): drv_active: 0x%08x\n",
1740 __func__, vha->host_no, drv_active);
1741 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1742 }
1743
1744 static int
1745 qla8044_check_drv_active(struct scsi_qla_host *vha)
1746 {
1747 uint32_t drv_active;
1748 struct qla_hw_data *ha = vha->hw;
1749
1750 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1751 if (drv_active & (1 << ha->portnum))
1752 return QLA_SUCCESS;
1753 else
1754 return QLA_TEST_FAILED;
1755 }
1756
1757 static void
1758 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1759 {
1760 uint32_t idc_ctrl;
1761 struct qla_hw_data *ha = vha->hw;
1762
1763 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1764 idc_ctrl &= ~DONTRESET_BIT0;
1765 ql_log(ql_log_info, vha, 0xb0c9,
1766 "%s: idc_ctrl = %d\n", __func__,
1767 idc_ctrl);
1768 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1769 }
1770
1771 static int
1772 qla8044_set_idc_ver(struct scsi_qla_host *vha)
1773 {
1774 int idc_ver;
1775 uint32_t drv_active;
1776 int rval = QLA_SUCCESS;
1777 struct qla_hw_data *ha = vha->hw;
1778
1779 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1780 if (drv_active == (1 << ha->portnum)) {
1781 idc_ver = qla8044_rd_direct(vha,
1782 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1783 idc_ver &= (~0xFF);
1784 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
1785 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1786 idc_ver);
1787 ql_log(ql_log_info, vha, 0xb0ca,
1788 "%s: IDC version updated to %d\n",
1789 __func__, idc_ver);
1790 } else {
1791 idc_ver = qla8044_rd_direct(vha,
1792 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1793 idc_ver &= 0xFF;
1794 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
1795 ql_log(ql_log_info, vha, 0xb0cb,
1796 "%s: qla4xxx driver IDC version %d "
1797 "is not compatible with IDC version %d "
1798 "of other drivers!\n",
1799 __func__, QLA8044_IDC_VER_MAJ_VALUE,
1800 idc_ver);
1801 rval = QLA_FUNCTION_FAILED;
1802 goto exit_set_idc_ver;
1803 }
1804 }
1805
1806 /* Update IDC_MINOR_VERSION */
1807 idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
1808 idc_ver &= ~(0x03 << (ha->portnum * 2));
1809 idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
1810 qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
1811
1812 exit_set_idc_ver:
1813 return rval;
1814 }
1815
1816 static int
1817 qla8044_update_idc_reg(struct scsi_qla_host *vha)
1818 {
1819 uint32_t drv_active;
1820 int rval = QLA_SUCCESS;
1821 struct qla_hw_data *ha = vha->hw;
1822
1823 if (vha->flags.init_done)
1824 goto exit_update_idc_reg;
1825
1826 qla8044_idc_lock(ha);
1827 qla8044_set_drv_active(vha);
1828
1829 drv_active = qla8044_rd_direct(vha,
1830 QLA8044_CRB_DRV_ACTIVE_INDEX);
1831
1832 /* If we are the first driver to load and
1833 * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1834 if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
1835 qla8044_clear_idc_dontreset(vha);
1836
1837 rval = qla8044_set_idc_ver(vha);
1838 if (rval == QLA_FUNCTION_FAILED)
1839 qla8044_clear_drv_active(ha);
1840 qla8044_idc_unlock(ha);
1841
1842 exit_update_idc_reg:
1843 return rval;
1844 }
1845
1846 /**
1847 * qla8044_need_qsnt_handler - Code to start qsnt
1848 * @ha: pointer to adapter structure
1849 **/
1850 static void
1851 qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1852 {
1853 unsigned long qsnt_timeout;
1854 uint32_t drv_state, drv_active, dev_state;
1855 struct qla_hw_data *ha = vha->hw;
1856
1857 if (vha->flags.online)
1858 qla2x00_quiesce_io(vha);
1859 else
1860 return;
1861
1862 qla8044_set_qsnt_ready(vha);
1863
1864 /* Wait for 30 secs for all functions to ack qsnt mode */
1865 qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
1866 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1867 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1868
1869 /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1870 position is at bit 1 and drv active is at bit 0 */
1871 drv_active = drv_active << 1;
1872
1873 while (drv_state != drv_active) {
1874 if (time_after_eq(jiffies, qsnt_timeout)) {
1875 /* Other functions did not ack, changing state to
1876 * DEV_READY
1877 */
1878 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1879 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1880 QLA8XXX_DEV_READY);
1881 qla8044_clear_qsnt_ready(vha);
1882 ql_log(ql_log_info, vha, 0xb0cc,
1883 "Timeout waiting for quiescent ack!!!\n");
1884 return;
1885 }
1886 qla8044_idc_unlock(ha);
1887 msleep(1000);
1888 qla8044_idc_lock(ha);
1889
1890 drv_state = qla8044_rd_direct(vha,
1891 QLA8044_CRB_DRV_STATE_INDEX);
1892 drv_active = qla8044_rd_direct(vha,
1893 QLA8044_CRB_DRV_ACTIVE_INDEX);
1894 drv_active = drv_active << 1;
1895 }
1896
1897 /* All functions have Acked. Set quiescent state */
1898 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1899
1900 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
1901 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1902 QLA8XXX_DEV_QUIESCENT);
1903 ql_log(ql_log_info, vha, 0xb0cd,
1904 "%s: HW State: QUIESCENT\n", __func__);
1905 }
1906 }
1907
1908 /*
1909 * qla8044_device_state_handler - Adapter state machine
1910 * @ha: pointer to host adapter structure.
1911 *
1912 * Note: IDC lock must be UNLOCKED upon entry
1913 **/
1914 int
1915 qla8044_device_state_handler(struct scsi_qla_host *vha)
1916 {
1917 uint32_t dev_state;
1918 int rval = QLA_SUCCESS;
1919 unsigned long dev_init_timeout;
1920 struct qla_hw_data *ha = vha->hw;
1921
1922 rval = qla8044_update_idc_reg(vha);
1923 if (rval == QLA_FUNCTION_FAILED)
1924 goto exit_error;
1925
1926 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1927 ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1928 "Device state is 0x%x = %s\n",
1929 dev_state, dev_state < MAX_STATES ?
1930 qdev_state(dev_state) : "Unknown");
1931
1932 /* wait for 30 seconds for device to go ready */
1933 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
1934
1935 qla8044_idc_lock(ha);
1936
1937 while (1) {
1938 if (time_after_eq(jiffies, dev_init_timeout)) {
1939 if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
1940 ql_log(ql_log_warn, vha, 0xb0cf,
1941 "%s: Device Init Failed 0x%x = %s\n",
1942 QLA2XXX_DRIVER_NAME, dev_state,
1943 dev_state < MAX_STATES ?
1944 qdev_state(dev_state) : "Unknown");
1945 qla8044_wr_direct(vha,
1946 QLA8044_CRB_DEV_STATE_INDEX,
1947 QLA8XXX_DEV_FAILED);
1948 }
1949 }
1950
1951 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1952 ql_log(ql_log_info, vha, 0xb0d0,
1953 "Device state is 0x%x = %s\n",
1954 dev_state, dev_state < MAX_STATES ?
1955 qdev_state(dev_state) : "Unknown");
1956
1957 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1958 switch (dev_state) {
1959 case QLA8XXX_DEV_READY:
1960 ha->flags.nic_core_reset_owner = 0;
1961 goto exit;
1962 case QLA8XXX_DEV_COLD:
1963 rval = qla8044_device_bootstrap(vha);
1964 break;
1965 case QLA8XXX_DEV_INITIALIZING:
1966 qla8044_idc_unlock(ha);
1967 msleep(1000);
1968 qla8044_idc_lock(ha);
1969 break;
1970 case QLA8XXX_DEV_NEED_RESET:
1971 /* For ISP8044, if NEED_RESET is set by any driver,
1972 * it should be honored, irrespective of IDC_CTRL
1973 * DONTRESET_BIT0 */
1974 qla8044_need_reset_handler(vha);
1975 break;
1976 case QLA8XXX_DEV_NEED_QUIESCENT:
1977 /* idc locked/unlocked in handler */
1978 qla8044_need_qsnt_handler(vha);
1979
1980 /* Reset the init timeout after qsnt handler */
1981 dev_init_timeout = jiffies +
1982 (ha->fcoe_reset_timeout * HZ);
1983 break;
1984 case QLA8XXX_DEV_QUIESCENT:
1985 ql_log(ql_log_info, vha, 0xb0d1,
1986 "HW State: QUIESCENT\n");
1987
1988 qla8044_idc_unlock(ha);
1989 msleep(1000);
1990 qla8044_idc_lock(ha);
1991
1992 /* Reset the init timeout after qsnt handler */
1993 dev_init_timeout = jiffies +
1994 (ha->fcoe_reset_timeout * HZ);
1995 break;
1996 case QLA8XXX_DEV_FAILED:
1997 ha->flags.nic_core_reset_owner = 0;
1998 qla8044_idc_unlock(ha);
1999 qla8xxx_dev_failed_handler(vha);
2000 rval = QLA_FUNCTION_FAILED;
2001 qla8044_idc_lock(ha);
2002 goto exit;
2003 default:
2004 qla8044_idc_unlock(ha);
2005 qla8xxx_dev_failed_handler(vha);
2006 rval = QLA_FUNCTION_FAILED;
2007 qla8044_idc_lock(ha);
2008 goto exit;
2009 }
2010 }
2011 exit:
2012 qla8044_idc_unlock(ha);
2013
2014 exit_error:
2015 return rval;
2016 }
2017
2018 /**
2019 * qla4_8xxx_check_temp - Check the ISP82XX temperature.
2020 * @ha: adapter block pointer.
2021 *
2022 * Note: The caller should not hold the idc lock.
2023 **/
2024 static int
2025 qla8044_check_temp(struct scsi_qla_host *vha)
2026 {
2027 uint32_t temp, temp_state, temp_val;
2028 int status = QLA_SUCCESS;
2029
2030 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2031 temp_state = qla82xx_get_temp_state(temp);
2032 temp_val = qla82xx_get_temp_val(temp);
2033
2034 if (temp_state == QLA82XX_TEMP_PANIC) {
2035 ql_log(ql_log_warn, vha, 0xb0d2,
2036 "Device temperature %d degrees C"
2037 " exceeds maximum allowed. Hardware has been shut"
2038 " down\n", temp_val);
2039 status = QLA_FUNCTION_FAILED;
2040 return status;
2041 } else if (temp_state == QLA82XX_TEMP_WARN) {
2042 ql_log(ql_log_warn, vha, 0xb0d3,
2043 "Device temperature %d"
2044 " degrees C exceeds operating range."
2045 " Immediate action needed.\n", temp_val);
2046 }
2047 return 0;
2048 }
2049
2050 int qla8044_read_temperature(scsi_qla_host_t *vha)
2051 {
2052 uint32_t temp;
2053
2054 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2055 return qla82xx_get_temp_val(temp);
2056 }
2057
2058 /**
2059 * qla8044_check_fw_alive - Check firmware health
2060 * @ha: Pointer to host adapter structure.
2061 *
2062 * Context: Interrupt
2063 **/
2064 int
2065 qla8044_check_fw_alive(struct scsi_qla_host *vha)
2066 {
2067 uint32_t fw_heartbeat_counter;
2068 uint32_t halt_status1, halt_status2;
2069 int status = QLA_SUCCESS;
2070
2071 fw_heartbeat_counter = qla8044_rd_direct(vha,
2072 QLA8044_PEG_ALIVE_COUNTER_INDEX);
2073
2074 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
2075 if (fw_heartbeat_counter == 0xffffffff) {
2076 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
2077 "scsi%ld: %s: Device in frozen "
2078 "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
2079 vha->host_no, __func__);
2080 return status;
2081 }
2082
2083 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
2084 vha->seconds_since_last_heartbeat++;
2085 /* FW not alive after 2 seconds */
2086 if (vha->seconds_since_last_heartbeat == 2) {
2087 vha->seconds_since_last_heartbeat = 0;
2088 halt_status1 = qla8044_rd_direct(vha,
2089 QLA8044_PEG_HALT_STATUS1_INDEX);
2090 halt_status2 = qla8044_rd_direct(vha,
2091 QLA8044_PEG_HALT_STATUS2_INDEX);
2092
2093 ql_log(ql_log_info, vha, 0xb0d5,
2094 "scsi(%ld): %s, ISP8044 "
2095 "Dumping hw/fw registers:\n"
2096 " PEG_HALT_STATUS1: 0x%x, "
2097 "PEG_HALT_STATUS2: 0x%x,\n",
2098 vha->host_no, __func__, halt_status1,
2099 halt_status2);
2100 status = QLA_FUNCTION_FAILED;
2101 }
2102 } else
2103 vha->seconds_since_last_heartbeat = 0;
2104
2105 vha->fw_heartbeat_counter = fw_heartbeat_counter;
2106 return status;
2107 }
2108
2109 void
2110 qla8044_watchdog(struct scsi_qla_host *vha)
2111 {
2112 uint32_t dev_state, halt_status;
2113 int halt_status_unrecoverable = 0;
2114 struct qla_hw_data *ha = vha->hw;
2115
2116 /* don't poll if reset is going on or FW hang in quiescent state */
2117 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
2118 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2119 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2120
2121 if (qla8044_check_fw_alive(vha)) {
2122 ha->flags.isp82xx_fw_hung = 1;
2123 ql_log(ql_log_warn, vha, 0xb10a,
2124 "Firmware hung.\n");
2125 qla82xx_clear_pending_mbx(vha);
2126 }
2127
2128 if (qla8044_check_temp(vha)) {
2129 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2130 ha->flags.isp82xx_fw_hung = 1;
2131 qla2xxx_wake_dpc(vha);
2132 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
2133 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2134 ql_log(ql_log_info, vha, 0xb0d6,
2135 "%s: HW State: NEED RESET!\n",
2136 __func__);
2137 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2138 qla2xxx_wake_dpc(vha);
2139 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
2140 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2141 ql_log(ql_log_info, vha, 0xb0d7,
2142 "%s: HW State: NEED QUIES detected!\n",
2143 __func__);
2144 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2145 qla2xxx_wake_dpc(vha);
2146 } else {
2147 /* Check firmware health */
2148 if (ha->flags.isp82xx_fw_hung) {
2149 halt_status = qla8044_rd_direct(vha,
2150 QLA8044_PEG_HALT_STATUS1_INDEX);
2151 if (halt_status &
2152 QLA8044_HALT_STATUS_FW_RESET) {
2153 ql_log(ql_log_fatal, vha,
2154 0xb0d8, "%s: Firmware "
2155 "error detected device "
2156 "is being reset\n",
2157 __func__);
2158 } else if (halt_status &
2159 QLA8044_HALT_STATUS_UNRECOVERABLE) {
2160 halt_status_unrecoverable = 1;
2161 }
2162
2163 /* Since we cannot change dev_state in interrupt
2164 * context, set appropriate DPC flag then wakeup
2165 * DPC */
2166 if (halt_status_unrecoverable) {
2167 set_bit(ISP_UNRECOVERABLE,
2168 &vha->dpc_flags);
2169 } else {
2170 if (dev_state ==
2171 QLA8XXX_DEV_QUIESCENT) {
2172 set_bit(FCOE_CTX_RESET_NEEDED,
2173 &vha->dpc_flags);
2174 ql_log(ql_log_info, vha, 0xb0d9,
2175 "%s: FW CONTEXT Reset "
2176 "needed!\n", __func__);
2177 } else {
2178 ql_log(ql_log_info, vha,
2179 0xb0da, "%s: "
2180 "detect abort needed\n",
2181 __func__);
2182 set_bit(ISP_ABORT_NEEDED,
2183 &vha->dpc_flags);
2184 }
2185 }
2186 qla2xxx_wake_dpc(vha);
2187 }
2188 }
2189
2190 }
2191 }
2192
2193 static int
2194 qla8044_minidump_process_control(struct scsi_qla_host *vha,
2195 struct qla8044_minidump_entry_hdr *entry_hdr)
2196 {
2197 struct qla8044_minidump_entry_crb *crb_entry;
2198 uint32_t read_value, opcode, poll_time, addr, index;
2199 uint32_t crb_addr, rval = QLA_SUCCESS;
2200 unsigned long wtime;
2201 struct qla8044_minidump_template_hdr *tmplt_hdr;
2202 int i;
2203 struct qla_hw_data *ha = vha->hw;
2204
2205 ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2206 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2207 ha->md_tmplt_hdr;
2208 crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
2209
2210 crb_addr = crb_entry->addr;
2211 for (i = 0; i < crb_entry->op_count; i++) {
2212 opcode = crb_entry->crb_ctrl.opcode;
2213
2214 if (opcode & QLA82XX_DBG_OPCODE_WR) {
2215 qla8044_wr_reg_indirect(vha, crb_addr,
2216 crb_entry->value_1);
2217 opcode &= ~QLA82XX_DBG_OPCODE_WR;
2218 }
2219
2220 if (opcode & QLA82XX_DBG_OPCODE_RW) {
2221 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2222 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2223 opcode &= ~QLA82XX_DBG_OPCODE_RW;
2224 }
2225
2226 if (opcode & QLA82XX_DBG_OPCODE_AND) {
2227 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2228 read_value &= crb_entry->value_2;
2229 opcode &= ~QLA82XX_DBG_OPCODE_AND;
2230 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2231 read_value |= crb_entry->value_3;
2232 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2233 }
2234 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2235 }
2236 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2237 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2238 read_value |= crb_entry->value_3;
2239 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2240 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2241 }
2242 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
2243 poll_time = crb_entry->crb_strd.poll_timeout;
2244 wtime = jiffies + poll_time;
2245 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2246
2247 do {
2248 if ((read_value & crb_entry->value_2) ==
2249 crb_entry->value_1) {
2250 break;
2251 } else if (time_after_eq(jiffies, wtime)) {
2252 /* capturing dump failed */
2253 rval = QLA_FUNCTION_FAILED;
2254 break;
2255 } else {
2256 qla8044_rd_reg_indirect(vha,
2257 crb_addr, &read_value);
2258 }
2259 } while (1);
2260 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
2261 }
2262
2263 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
2264 if (crb_entry->crb_strd.state_index_a) {
2265 index = crb_entry->crb_strd.state_index_a;
2266 addr = tmplt_hdr->saved_state_array[index];
2267 } else {
2268 addr = crb_addr;
2269 }
2270
2271 qla8044_rd_reg_indirect(vha, addr, &read_value);
2272 index = crb_entry->crb_ctrl.state_index_v;
2273 tmplt_hdr->saved_state_array[index] = read_value;
2274 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
2275 }
2276
2277 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
2278 if (crb_entry->crb_strd.state_index_a) {
2279 index = crb_entry->crb_strd.state_index_a;
2280 addr = tmplt_hdr->saved_state_array[index];
2281 } else {
2282 addr = crb_addr;
2283 }
2284
2285 if (crb_entry->crb_ctrl.state_index_v) {
2286 index = crb_entry->crb_ctrl.state_index_v;
2287 read_value =
2288 tmplt_hdr->saved_state_array[index];
2289 } else {
2290 read_value = crb_entry->value_1;
2291 }
2292
2293 qla8044_wr_reg_indirect(vha, addr, read_value);
2294 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
2295 }
2296
2297 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
2298 index = crb_entry->crb_ctrl.state_index_v;
2299 read_value = tmplt_hdr->saved_state_array[index];
2300 read_value <<= crb_entry->crb_ctrl.shl;
2301 read_value >>= crb_entry->crb_ctrl.shr;
2302 if (crb_entry->value_2)
2303 read_value &= crb_entry->value_2;
2304 read_value |= crb_entry->value_3;
2305 read_value += crb_entry->value_1;
2306 tmplt_hdr->saved_state_array[index] = read_value;
2307 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
2308 }
2309 crb_addr += crb_entry->crb_strd.addr_stride;
2310 }
2311 return rval;
2312 }
2313
2314 static void
2315 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2316 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2317 {
2318 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2319 struct qla8044_minidump_entry_crb *crb_hdr;
2320 uint32_t *data_ptr = *d_ptr;
2321
2322 ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2323 crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
2324 r_addr = crb_hdr->addr;
2325 r_stride = crb_hdr->crb_strd.addr_stride;
2326 loop_cnt = crb_hdr->op_count;
2327
2328 for (i = 0; i < loop_cnt; i++) {
2329 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2330 *data_ptr++ = r_addr;
2331 *data_ptr++ = r_value;
2332 r_addr += r_stride;
2333 }
2334 *d_ptr = data_ptr;
2335 }
2336
2337 static int
2338 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2339 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2340 {
2341 uint32_t r_addr, r_value, r_data;
2342 uint32_t i, j, loop_cnt;
2343 struct qla8044_minidump_entry_rdmem *m_hdr;
2344 unsigned long flags;
2345 uint32_t *data_ptr = *d_ptr;
2346 struct qla_hw_data *ha = vha->hw;
2347
2348 ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2349 m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
2350 r_addr = m_hdr->read_addr;
2351 loop_cnt = m_hdr->read_data_size/16;
2352
2353 ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2354 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2355 __func__, r_addr, m_hdr->read_data_size);
2356
2357 if (r_addr & 0xf) {
2358 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
2359 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2360 __func__, r_addr);
2361 return QLA_FUNCTION_FAILED;
2362 }
2363
2364 if (m_hdr->read_data_size % 16) {
2365 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2366 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2367 __func__, m_hdr->read_data_size);
2368 return QLA_FUNCTION_FAILED;
2369 }
2370
2371 ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2372 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2373 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
2374
2375 write_lock_irqsave(&ha->hw_lock, flags);
2376 for (i = 0; i < loop_cnt; i++) {
2377 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2378 r_value = 0;
2379 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2380 r_value = MIU_TA_CTL_ENABLE;
2381 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2382 r_value = MIU_TA_CTL_START_ENABLE;
2383 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2384
2385 for (j = 0; j < MAX_CTL_CHECK; j++) {
2386 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2387 &r_value);
2388 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2389 break;
2390 }
2391
2392 if (j >= MAX_CTL_CHECK) {
2393 write_unlock_irqrestore(&ha->hw_lock, flags);
2394 return QLA_SUCCESS;
2395 }
2396
2397 for (j = 0; j < 4; j++) {
2398 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2399 &r_data);
2400 *data_ptr++ = r_data;
2401 }
2402
2403 r_addr += 16;
2404 }
2405 write_unlock_irqrestore(&ha->hw_lock, flags);
2406
2407 ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2408 "Leaving fn: %s datacount: 0x%x\n",
2409 __func__, (loop_cnt * 16));
2410
2411 *d_ptr = data_ptr;
2412 return QLA_SUCCESS;
2413 }
2414
2415 /* ISP83xx flash read for _RDROM _BOARD */
2416 static uint32_t
2417 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2418 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2419 {
2420 uint32_t fl_addr, u32_count, rval;
2421 struct qla8044_minidump_entry_rdrom *rom_hdr;
2422 uint32_t *data_ptr = *d_ptr;
2423
2424 rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
2425 fl_addr = rom_hdr->read_addr;
2426 u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
2427
2428 ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2429 __func__, fl_addr, u32_count);
2430
2431 rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2432 (u8 *)(data_ptr), u32_count);
2433
2434 if (rval != QLA_SUCCESS) {
2435 ql_log(ql_log_fatal, vha, 0xb0f6,
2436 "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
2437 return QLA_FUNCTION_FAILED;
2438 } else {
2439 data_ptr += u32_count;
2440 *d_ptr = data_ptr;
2441 return QLA_SUCCESS;
2442 }
2443 }
2444
2445 static void
2446 qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2447 struct qla8044_minidump_entry_hdr *entry_hdr, int index)
2448 {
2449 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2450
2451 ql_log(ql_log_info, vha, 0xb0f7,
2452 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2453 vha->host_no, index, entry_hdr->entry_type,
2454 entry_hdr->d_ctrl.entry_capture_mask);
2455 }
2456
2457 static int
2458 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2459 struct qla8044_minidump_entry_hdr *entry_hdr,
2460 uint32_t **d_ptr)
2461 {
2462 uint32_t addr, r_addr, c_addr, t_r_addr;
2463 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2464 unsigned long p_wait, w_time, p_mask;
2465 uint32_t c_value_w, c_value_r;
2466 struct qla8044_minidump_entry_cache *cache_hdr;
2467 int rval = QLA_FUNCTION_FAILED;
2468 uint32_t *data_ptr = *d_ptr;
2469
2470 ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2471 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2472
2473 loop_count = cache_hdr->op_count;
2474 r_addr = cache_hdr->read_addr;
2475 c_addr = cache_hdr->control_addr;
2476 c_value_w = cache_hdr->cache_ctrl.write_value;
2477
2478 t_r_addr = cache_hdr->tag_reg_addr;
2479 t_value = cache_hdr->addr_ctrl.init_tag_value;
2480 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2481 p_wait = cache_hdr->cache_ctrl.poll_wait;
2482 p_mask = cache_hdr->cache_ctrl.poll_mask;
2483
2484 for (i = 0; i < loop_count; i++) {
2485 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2486 if (c_value_w)
2487 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2488
2489 if (p_mask) {
2490 w_time = jiffies + p_wait;
2491 do {
2492 qla8044_rd_reg_indirect(vha, c_addr,
2493 &c_value_r);
2494 if ((c_value_r & p_mask) == 0) {
2495 break;
2496 } else if (time_after_eq(jiffies, w_time)) {
2497 /* capturing dump failed */
2498 return rval;
2499 }
2500 } while (1);
2501 }
2502
2503 addr = r_addr;
2504 for (k = 0; k < r_cnt; k++) {
2505 qla8044_rd_reg_indirect(vha, addr, &r_value);
2506 *data_ptr++ = r_value;
2507 addr += cache_hdr->read_ctrl.read_addr_stride;
2508 }
2509 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2510 }
2511 *d_ptr = data_ptr;
2512 return QLA_SUCCESS;
2513 }
2514
2515 static void
2516 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2517 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2518 {
2519 uint32_t addr, r_addr, c_addr, t_r_addr;
2520 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2521 uint32_t c_value_w;
2522 struct qla8044_minidump_entry_cache *cache_hdr;
2523 uint32_t *data_ptr = *d_ptr;
2524
2525 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2526 loop_count = cache_hdr->op_count;
2527 r_addr = cache_hdr->read_addr;
2528 c_addr = cache_hdr->control_addr;
2529 c_value_w = cache_hdr->cache_ctrl.write_value;
2530
2531 t_r_addr = cache_hdr->tag_reg_addr;
2532 t_value = cache_hdr->addr_ctrl.init_tag_value;
2533 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2534
2535 for (i = 0; i < loop_count; i++) {
2536 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2537 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2538 addr = r_addr;
2539 for (k = 0; k < r_cnt; k++) {
2540 qla8044_rd_reg_indirect(vha, addr, &r_value);
2541 *data_ptr++ = r_value;
2542 addr += cache_hdr->read_ctrl.read_addr_stride;
2543 }
2544 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2545 }
2546 *d_ptr = data_ptr;
2547 }
2548
2549 static void
2550 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2551 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2552 {
2553 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2554 struct qla8044_minidump_entry_rdocm *ocm_hdr;
2555 uint32_t *data_ptr = *d_ptr;
2556 struct qla_hw_data *ha = vha->hw;
2557
2558 ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2559
2560 ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
2561 r_addr = ocm_hdr->read_addr;
2562 r_stride = ocm_hdr->read_addr_stride;
2563 loop_cnt = ocm_hdr->op_count;
2564
2565 ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2566 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2567 __func__, r_addr, r_stride, loop_cnt);
2568
2569 for (i = 0; i < loop_cnt; i++) {
2570 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2571 *data_ptr++ = r_value;
2572 r_addr += r_stride;
2573 }
2574 ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2575 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
2576
2577 *d_ptr = data_ptr;
2578 }
2579
2580 static void
2581 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2582 struct qla8044_minidump_entry_hdr *entry_hdr,
2583 uint32_t **d_ptr)
2584 {
2585 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2586 struct qla8044_minidump_entry_mux *mux_hdr;
2587 uint32_t *data_ptr = *d_ptr;
2588
2589 ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2590
2591 mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
2592 r_addr = mux_hdr->read_addr;
2593 s_addr = mux_hdr->select_addr;
2594 s_stride = mux_hdr->select_value_stride;
2595 s_value = mux_hdr->select_value;
2596 loop_cnt = mux_hdr->op_count;
2597
2598 for (i = 0; i < loop_cnt; i++) {
2599 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2600 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2601 *data_ptr++ = s_value;
2602 *data_ptr++ = r_value;
2603 s_value += s_stride;
2604 }
2605 *d_ptr = data_ptr;
2606 }
2607
2608 static void
2609 qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2610 struct qla8044_minidump_entry_hdr *entry_hdr,
2611 uint32_t **d_ptr)
2612 {
2613 uint32_t s_addr, r_addr;
2614 uint32_t r_stride, r_value, r_cnt, qid = 0;
2615 uint32_t i, k, loop_cnt;
2616 struct qla8044_minidump_entry_queue *q_hdr;
2617 uint32_t *data_ptr = *d_ptr;
2618
2619 ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2620 q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
2621 s_addr = q_hdr->select_addr;
2622 r_cnt = q_hdr->rd_strd.read_addr_cnt;
2623 r_stride = q_hdr->rd_strd.read_addr_stride;
2624 loop_cnt = q_hdr->op_count;
2625
2626 for (i = 0; i < loop_cnt; i++) {
2627 qla8044_wr_reg_indirect(vha, s_addr, qid);
2628 r_addr = q_hdr->read_addr;
2629 for (k = 0; k < r_cnt; k++) {
2630 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2631 *data_ptr++ = r_value;
2632 r_addr += r_stride;
2633 }
2634 qid += q_hdr->q_strd.queue_id_stride;
2635 }
2636 *d_ptr = data_ptr;
2637 }
2638
2639 /* ISP83xx functions to process new minidump entries... */
2640 static uint32_t
2641 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2642 struct qla8044_minidump_entry_hdr *entry_hdr,
2643 uint32_t **d_ptr)
2644 {
2645 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2646 uint16_t s_stride, i;
2647 struct qla8044_minidump_entry_pollrd *pollrd_hdr;
2648 uint32_t *data_ptr = *d_ptr;
2649
2650 pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
2651 s_addr = pollrd_hdr->select_addr;
2652 r_addr = pollrd_hdr->read_addr;
2653 s_value = pollrd_hdr->select_value;
2654 s_stride = pollrd_hdr->select_value_stride;
2655
2656 poll_wait = pollrd_hdr->poll_wait;
2657 poll_mask = pollrd_hdr->poll_mask;
2658
2659 for (i = 0; i < pollrd_hdr->op_count; i++) {
2660 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2661 poll_wait = pollrd_hdr->poll_wait;
2662 while (1) {
2663 qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2664 if ((r_value & poll_mask) != 0) {
2665 break;
2666 } else {
2667 usleep_range(1000, 1100);
2668 if (--poll_wait == 0) {
2669 ql_log(ql_log_fatal, vha, 0xb0fe,
2670 "%s: TIMEOUT\n", __func__);
2671 goto error;
2672 }
2673 }
2674 }
2675 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2676 *data_ptr++ = s_value;
2677 *data_ptr++ = r_value;
2678
2679 s_value += s_stride;
2680 }
2681 *d_ptr = data_ptr;
2682 return QLA_SUCCESS;
2683
2684 error:
2685 return QLA_FUNCTION_FAILED;
2686 }
2687
2688 static void
2689 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2690 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2691 {
2692 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2693 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2694 struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
2695 uint32_t *data_ptr = *d_ptr;
2696
2697 rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
2698 sel_val1 = rdmux2_hdr->select_value_1;
2699 sel_val2 = rdmux2_hdr->select_value_2;
2700 sel_addr1 = rdmux2_hdr->select_addr_1;
2701 sel_addr2 = rdmux2_hdr->select_addr_2;
2702 sel_val_mask = rdmux2_hdr->select_value_mask;
2703 read_addr = rdmux2_hdr->read_addr;
2704
2705 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2706 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2707 t_sel_val = sel_val1 & sel_val_mask;
2708 *data_ptr++ = t_sel_val;
2709
2710 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2711 qla8044_rd_reg_indirect(vha, read_addr, &data);
2712
2713 *data_ptr++ = data;
2714
2715 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2716 t_sel_val = sel_val2 & sel_val_mask;
2717 *data_ptr++ = t_sel_val;
2718
2719 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2720 qla8044_rd_reg_indirect(vha, read_addr, &data);
2721
2722 *data_ptr++ = data;
2723
2724 sel_val1 += rdmux2_hdr->select_value_stride;
2725 sel_val2 += rdmux2_hdr->select_value_stride;
2726 }
2727
2728 *d_ptr = data_ptr;
2729 }
2730
2731 static uint32_t
2732 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2733 struct qla8044_minidump_entry_hdr *entry_hdr,
2734 uint32_t **d_ptr)
2735 {
2736 uint32_t poll_wait, poll_mask, r_value, data;
2737 uint32_t addr_1, addr_2, value_1, value_2;
2738 struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
2739 uint32_t *data_ptr = *d_ptr;
2740
2741 poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
2742 addr_1 = poll_hdr->addr_1;
2743 addr_2 = poll_hdr->addr_2;
2744 value_1 = poll_hdr->value_1;
2745 value_2 = poll_hdr->value_2;
2746 poll_mask = poll_hdr->poll_mask;
2747
2748 qla8044_wr_reg_indirect(vha, addr_1, value_1);
2749
2750 poll_wait = poll_hdr->poll_wait;
2751 while (1) {
2752 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2753
2754 if ((r_value & poll_mask) != 0) {
2755 break;
2756 } else {
2757 usleep_range(1000, 1100);
2758 if (--poll_wait == 0) {
2759 ql_log(ql_log_fatal, vha, 0xb0ff,
2760 "%s: TIMEOUT\n", __func__);
2761 goto error;
2762 }
2763 }
2764 }
2765
2766 qla8044_rd_reg_indirect(vha, addr_2, &data);
2767 data &= poll_hdr->modify_mask;
2768 qla8044_wr_reg_indirect(vha, addr_2, data);
2769 qla8044_wr_reg_indirect(vha, addr_1, value_2);
2770
2771 poll_wait = poll_hdr->poll_wait;
2772 while (1) {
2773 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2774
2775 if ((r_value & poll_mask) != 0) {
2776 break;
2777 } else {
2778 usleep_range(1000, 1100);
2779 if (--poll_wait == 0) {
2780 ql_log(ql_log_fatal, vha, 0xb100,
2781 "%s: TIMEOUT2\n", __func__);
2782 goto error;
2783 }
2784 }
2785 }
2786
2787 *data_ptr++ = addr_2;
2788 *data_ptr++ = data;
2789
2790 *d_ptr = data_ptr;
2791
2792 return QLA_SUCCESS;
2793
2794 error:
2795 return QLA_FUNCTION_FAILED;
2796 }
2797
2798 #define ISP8044_PEX_DMA_ENGINE_INDEX 8
2799 #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000
2800 #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000
2801 #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0
2802 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04
2803 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08
2804
2805 #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024)
2806 #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
2807
2808 static int
2809 qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2810 {
2811 struct qla_hw_data *ha = vha->hw;
2812 int rval = QLA_SUCCESS;
2813 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2814 uint64_t dma_base_addr = 0;
2815 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2816
2817 tmplt_hdr = ha->md_tmplt_hdr;
2818 dma_eng_num =
2819 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2820 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2821 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2822
2823 /* Read the pex-dma's command-status-and-control register. */
2824 rval = qla8044_rd_reg_indirect(vha,
2825 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2826 &cmd_sts_and_cntrl);
2827 if (rval)
2828 return QLA_FUNCTION_FAILED;
2829
2830 /* Check if requested pex-dma engine is available. */
2831 if (cmd_sts_and_cntrl & BIT_31)
2832 return QLA_SUCCESS;
2833
2834 return QLA_FUNCTION_FAILED;
2835 }
2836
2837 static int
2838 qla8044_start_pex_dma(struct scsi_qla_host *vha,
2839 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
2840 {
2841 struct qla_hw_data *ha = vha->hw;
2842 int rval = QLA_SUCCESS, wait = 0;
2843 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2844 uint64_t dma_base_addr = 0;
2845 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2846
2847 tmplt_hdr = ha->md_tmplt_hdr;
2848 dma_eng_num =
2849 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2850 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2851 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2852
2853 rval = qla8044_wr_reg_indirect(vha,
2854 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
2855 m_hdr->desc_card_addr);
2856 if (rval)
2857 goto error_exit;
2858
2859 rval = qla8044_wr_reg_indirect(vha,
2860 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
2861 if (rval)
2862 goto error_exit;
2863
2864 rval = qla8044_wr_reg_indirect(vha,
2865 dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
2866 m_hdr->start_dma_cmd);
2867 if (rval)
2868 goto error_exit;
2869
2870 /* Wait for dma operation to complete. */
2871 for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
2872 rval = qla8044_rd_reg_indirect(vha,
2873 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2874 &cmd_sts_and_cntrl);
2875 if (rval)
2876 goto error_exit;
2877
2878 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2879 break;
2880
2881 udelay(10);
2882 }
2883
2884 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2885 if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
2886 rval = QLA_FUNCTION_FAILED;
2887 goto error_exit;
2888 }
2889
2890 error_exit:
2891 return rval;
2892 }
2893
2894 static int
2895 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2896 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2897 {
2898 struct qla_hw_data *ha = vha->hw;
2899 int rval = QLA_SUCCESS;
2900 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2901 uint32_t chunk_size, read_size;
2902 uint8_t *data_ptr = (uint8_t *)*d_ptr;
2903 void *rdmem_buffer = NULL;
2904 dma_addr_t rdmem_dma;
2905 struct qla8044_pex_dma_descriptor dma_desc;
2906
2907 rval = qla8044_check_dma_engine_state(vha);
2908 if (rval != QLA_SUCCESS) {
2909 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2910 "DMA engine not available. Fallback to rdmem-read.\n");
2911 return QLA_FUNCTION_FAILED;
2912 }
2913
2914 m_hdr = (void *)entry_hdr;
2915
2916 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2917 ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
2918 if (!rdmem_buffer) {
2919 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2920 "Unable to allocate rdmem dma buffer\n");
2921 return QLA_FUNCTION_FAILED;
2922 }
2923
2924 /* Prepare pex-dma descriptor to be written to MS memory. */
2925 /* dma-desc-cmd layout:
2926 * 0-3: dma-desc-cmd 0-3
2927 * 4-7: pcid function number
2928 * 8-15: dma-desc-cmd 8-15
2929 * dma_bus_addr: dma buffer address
2930 * cmd.read_data_size: amount of data-chunk to be read.
2931 */
2932 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2933 dma_desc.cmd.dma_desc_cmd |=
2934 ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2935
2936 dma_desc.dma_bus_addr = rdmem_dma;
2937 dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
2938 read_size = 0;
2939
2940 /*
2941 * Perform rdmem operation using pex-dma.
2942 * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2943 */
2944 while (read_size < m_hdr->read_data_size) {
2945 if (m_hdr->read_data_size - read_size <
2946 ISP8044_PEX_DMA_READ_SIZE) {
2947 chunk_size = (m_hdr->read_data_size - read_size);
2948 dma_desc.cmd.read_data_size = chunk_size;
2949 }
2950
2951 dma_desc.src_addr = m_hdr->read_addr + read_size;
2952
2953 /* Prepare: Write pex-dma descriptor to MS memory. */
2954 rval = qla8044_ms_mem_write_128b(vha,
2955 m_hdr->desc_card_addr, (void *)&dma_desc,
2956 (sizeof(struct qla8044_pex_dma_descriptor)/16));
2957 if (rval) {
2958 ql_log(ql_log_warn, vha, 0xb14a,
2959 "%s: Error writing rdmem-dma-init to MS !!!\n",
2960 __func__);
2961 goto error_exit;
2962 }
2963 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2964 "%s: Dma-descriptor: Instruct for rdmem dma "
2965 "(chunk_size 0x%x).\n", __func__, chunk_size);
2966
2967 /* Execute: Start pex-dma operation. */
2968 rval = qla8044_start_pex_dma(vha, m_hdr);
2969 if (rval)
2970 goto error_exit;
2971
2972 memcpy(data_ptr, rdmem_buffer, chunk_size);
2973 data_ptr += chunk_size;
2974 read_size += chunk_size;
2975 }
2976
2977 *d_ptr = (void *)data_ptr;
2978
2979 error_exit:
2980 if (rdmem_buffer)
2981 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
2982 rdmem_buffer, rdmem_dma);
2983
2984 return rval;
2985 }
2986
2987 static uint32_t
2988 qla8044_minidump_process_rddfe(struct scsi_qla_host *vha,
2989 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2990 {
2991 int loop_cnt;
2992 uint32_t addr1, addr2, value, data, temp, wrVal;
2993 uint8_t stride, stride2;
2994 uint16_t count;
2995 uint32_t poll, mask, data_size, modify_mask;
2996 uint32_t wait_count = 0;
2997
2998 uint32_t *data_ptr = *d_ptr;
2999
3000 struct qla8044_minidump_entry_rddfe *rddfe;
3001 rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr;
3002
3003 addr1 = rddfe->addr_1;
3004 value = rddfe->value;
3005 stride = rddfe->stride;
3006 stride2 = rddfe->stride2;
3007 count = rddfe->count;
3008
3009 poll = rddfe->poll;
3010 mask = rddfe->mask;
3011 modify_mask = rddfe->modify_mask;
3012 data_size = rddfe->data_size;
3013
3014 addr2 = addr1 + stride;
3015
3016 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
3017 qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value));
3018
3019 wait_count = 0;
3020 while (wait_count < poll) {
3021 qla8044_rd_reg_indirect(vha, addr1, &temp);
3022 if ((temp & mask) != 0)
3023 break;
3024 wait_count++;
3025 }
3026
3027 if (wait_count == poll) {
3028 ql_log(ql_log_warn, vha, 0xb153,
3029 "%s: TIMEOUT\n", __func__);
3030 goto error;
3031 } else {
3032 qla8044_rd_reg_indirect(vha, addr2, &temp);
3033 temp = temp & modify_mask;
3034 temp = (temp | ((loop_cnt << 16) | loop_cnt));
3035 wrVal = ((temp << 16) | temp);
3036
3037 qla8044_wr_reg_indirect(vha, addr2, wrVal);
3038 qla8044_wr_reg_indirect(vha, addr1, value);
3039
3040 wait_count = 0;
3041 while (wait_count < poll) {
3042 qla8044_rd_reg_indirect(vha, addr1, &temp);
3043 if ((temp & mask) != 0)
3044 break;
3045 wait_count++;
3046 }
3047 if (wait_count == poll) {
3048 ql_log(ql_log_warn, vha, 0xb154,
3049 "%s: TIMEOUT\n", __func__);
3050 goto error;
3051 }
3052
3053 qla8044_wr_reg_indirect(vha, addr1,
3054 ((0x40000000 | value) + stride2));
3055 wait_count = 0;
3056 while (wait_count < poll) {
3057 qla8044_rd_reg_indirect(vha, addr1, &temp);
3058 if ((temp & mask) != 0)
3059 break;
3060 wait_count++;
3061 }
3062
3063 if (wait_count == poll) {
3064 ql_log(ql_log_warn, vha, 0xb155,
3065 "%s: TIMEOUT\n", __func__);
3066 goto error;
3067 }
3068
3069 qla8044_rd_reg_indirect(vha, addr2, &data);
3070
3071 *data_ptr++ = wrVal;
3072 *data_ptr++ = data;
3073 }
3074
3075 }
3076
3077 *d_ptr = data_ptr;
3078 return QLA_SUCCESS;
3079
3080 error:
3081 return -1;
3082
3083 }
3084
3085 static uint32_t
3086 qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha,
3087 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3088 {
3089 int ret = 0;
3090 uint32_t addr1, addr2, value1, value2, data, selVal;
3091 uint8_t stride1, stride2;
3092 uint32_t addr3, addr4, addr5, addr6, addr7;
3093 uint16_t count, loop_cnt;
3094 uint32_t poll, mask;
3095 uint32_t *data_ptr = *d_ptr;
3096
3097 struct qla8044_minidump_entry_rdmdio *rdmdio;
3098
3099 rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr;
3100
3101 addr1 = rdmdio->addr_1;
3102 addr2 = rdmdio->addr_2;
3103 value1 = rdmdio->value_1;
3104 stride1 = rdmdio->stride_1;
3105 stride2 = rdmdio->stride_2;
3106 count = rdmdio->count;
3107
3108 poll = rdmdio->poll;
3109 mask = rdmdio->mask;
3110 value2 = rdmdio->value_2;
3111
3112 addr3 = addr1 + stride1;
3113
3114 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
3115 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3116 addr3, mask);
3117 if (ret == -1)
3118 goto error;
3119
3120 addr4 = addr2 - stride1;
3121 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4,
3122 value2);
3123 if (ret == -1)
3124 goto error;
3125
3126 addr5 = addr2 - (2 * stride1);
3127 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5,
3128 value1);
3129 if (ret == -1)
3130 goto error;
3131
3132 addr6 = addr2 - (3 * stride1);
3133 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask,
3134 addr6, 0x2);
3135 if (ret == -1)
3136 goto error;
3137
3138 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3139 addr3, mask);
3140 if (ret == -1)
3141 goto error;
3142
3143 addr7 = addr2 - (4 * stride1);
3144 data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr7);
3145 if (data == -1)
3146 goto error;
3147
3148 selVal = (value2 << 18) | (value1 << 2) | 2;
3149
3150 stride2 = rdmdio->stride_2;
3151 *data_ptr++ = selVal;
3152 *data_ptr++ = data;
3153
3154 value1 = value1 + stride2;
3155 *d_ptr = data_ptr;
3156 }
3157
3158 return 0;
3159
3160 error:
3161 return -1;
3162 }
3163
3164 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha,
3165 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3166 {
3167 uint32_t addr1, addr2, value1, value2, poll, mask, r_value;
3168 uint32_t wait_count = 0;
3169 struct qla8044_minidump_entry_pollwr *pollwr_hdr;
3170
3171 pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
3172 addr1 = pollwr_hdr->addr_1;
3173 addr2 = pollwr_hdr->addr_2;
3174 value1 = pollwr_hdr->value_1;
3175 value2 = pollwr_hdr->value_2;
3176
3177 poll = pollwr_hdr->poll;
3178 mask = pollwr_hdr->mask;
3179
3180 while (wait_count < poll) {
3181 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3182
3183 if ((r_value & poll) != 0)
3184 break;
3185 wait_count++;
3186 }
3187
3188 if (wait_count == poll) {
3189 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__);
3190 goto error;
3191 }
3192
3193 qla8044_wr_reg_indirect(vha, addr2, value2);
3194 qla8044_wr_reg_indirect(vha, addr1, value1);
3195
3196 wait_count = 0;
3197 while (wait_count < poll) {
3198 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3199
3200 if ((r_value & poll) != 0)
3201 break;
3202 wait_count++;
3203 }
3204
3205 return QLA_SUCCESS;
3206
3207 error:
3208 return -1;
3209 }
3210
3211 /*
3212 *
3213 * qla8044_collect_md_data - Retrieve firmware minidump data.
3214 * @ha: pointer to adapter structure
3215 **/
3216 int
3217 qla8044_collect_md_data(struct scsi_qla_host *vha)
3218 {
3219 int num_entry_hdr = 0;
3220 struct qla8044_minidump_entry_hdr *entry_hdr;
3221 struct qla8044_minidump_template_hdr *tmplt_hdr;
3222 uint32_t *data_ptr;
3223 uint32_t data_collected = 0, f_capture_mask;
3224 int i, rval = QLA_FUNCTION_FAILED;
3225 uint64_t now;
3226 uint32_t timestamp, idc_control;
3227 struct qla_hw_data *ha = vha->hw;
3228
3229 if (!ha->md_dump) {
3230 ql_log(ql_log_info, vha, 0xb101,
3231 "%s(%ld) No buffer to dump\n",
3232 __func__, vha->host_no);
3233 return rval;
3234 }
3235
3236 if (ha->fw_dumped) {
3237 ql_log(ql_log_warn, vha, 0xb10d,
3238 "Firmware has been previously dumped (%p) "
3239 "-- ignoring request.\n", ha->fw_dump);
3240 goto md_failed;
3241 }
3242
3243 ha->fw_dumped = 0;
3244
3245 if (!ha->md_tmplt_hdr || !ha->md_dump) {
3246 ql_log(ql_log_warn, vha, 0xb10e,
3247 "Memory not allocated for minidump capture\n");
3248 goto md_failed;
3249 }
3250
3251 qla8044_idc_lock(ha);
3252 idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3253 if (idc_control & GRACEFUL_RESET_BIT1) {
3254 ql_log(ql_log_warn, vha, 0xb112,
3255 "Forced reset from application, "
3256 "ignore minidump capture\n");
3257 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
3258 (idc_control & ~GRACEFUL_RESET_BIT1));
3259 qla8044_idc_unlock(ha);
3260
3261 goto md_failed;
3262 }
3263 qla8044_idc_unlock(ha);
3264
3265 if (qla82xx_validate_template_chksum(vha)) {
3266 ql_log(ql_log_info, vha, 0xb109,
3267 "Template checksum validation error\n");
3268 goto md_failed;
3269 }
3270
3271 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
3272 ha->md_tmplt_hdr;
3273 data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
3274 num_entry_hdr = tmplt_hdr->num_of_entries;
3275
3276 ql_dbg(ql_dbg_p3p, vha, 0xb11a,
3277 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
3278
3279 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
3280
3281 /* Validate whether required debug level is set */
3282 if ((f_capture_mask & 0x3) != 0x3) {
3283 ql_log(ql_log_warn, vha, 0xb10f,
3284 "Minimum required capture mask[0x%x] level not set\n",
3285 f_capture_mask);
3286
3287 }
3288 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
3289 ql_log(ql_log_info, vha, 0xb102,
3290 "[%s]: starting data ptr: %p\n",
3291 __func__, data_ptr);
3292 ql_log(ql_log_info, vha, 0xb10b,
3293 "[%s]: no of entry headers in Template: 0x%x\n",
3294 __func__, num_entry_hdr);
3295 ql_log(ql_log_info, vha, 0xb10c,
3296 "[%s]: Total_data_size 0x%x, %d obtained\n",
3297 __func__, ha->md_dump_size, ha->md_dump_size);
3298
3299 /* Update current timestamp before taking dump */
3300 now = get_jiffies_64();
3301 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
3302 tmplt_hdr->driver_timestamp = timestamp;
3303
3304 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3305 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
3306 tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
3307 tmplt_hdr->ocm_window_reg[ha->portnum];
3308
3309 /* Walk through the entry headers - validate/perform required action */
3310 for (i = 0; i < num_entry_hdr; i++) {
3311 if (data_collected > ha->md_dump_size) {
3312 ql_log(ql_log_info, vha, 0xb103,
3313 "Data collected: [0x%x], "
3314 "Total Dump size: [0x%x]\n",
3315 data_collected, ha->md_dump_size);
3316 return rval;
3317 }
3318
3319 if (!(entry_hdr->d_ctrl.entry_capture_mask &
3320 ql2xmdcapmask)) {
3321 entry_hdr->d_ctrl.driver_flags |=
3322 QLA82XX_DBG_SKIPPED_FLAG;
3323 goto skip_nxt_entry;
3324 }
3325
3326 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3327 "Data collected: [0x%x], Dump size left:[0x%x]\n",
3328 data_collected,
3329 (ha->md_dump_size - data_collected));
3330
3331 /* Decode the entry type and take required action to capture
3332 * debug data
3333 */
3334 switch (entry_hdr->entry_type) {
3335 case QLA82XX_RDEND:
3336 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3337 break;
3338 case QLA82XX_CNTRL:
3339 rval = qla8044_minidump_process_control(vha,
3340 entry_hdr);
3341 if (rval != QLA_SUCCESS) {
3342 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3343 goto md_failed;
3344 }
3345 break;
3346 case QLA82XX_RDCRB:
3347 qla8044_minidump_process_rdcrb(vha,
3348 entry_hdr, &data_ptr);
3349 break;
3350 case QLA82XX_RDMEM:
3351 rval = qla8044_minidump_pex_dma_read(vha,
3352 entry_hdr, &data_ptr);
3353 if (rval != QLA_SUCCESS) {
3354 rval = qla8044_minidump_process_rdmem(vha,
3355 entry_hdr, &data_ptr);
3356 if (rval != QLA_SUCCESS) {
3357 qla8044_mark_entry_skipped(vha,
3358 entry_hdr, i);
3359 goto md_failed;
3360 }
3361 }
3362 break;
3363 case QLA82XX_BOARD:
3364 case QLA82XX_RDROM:
3365 rval = qla8044_minidump_process_rdrom(vha,
3366 entry_hdr, &data_ptr);
3367 if (rval != QLA_SUCCESS) {
3368 qla8044_mark_entry_skipped(vha,
3369 entry_hdr, i);
3370 }
3371 break;
3372 case QLA82XX_L2DTG:
3373 case QLA82XX_L2ITG:
3374 case QLA82XX_L2DAT:
3375 case QLA82XX_L2INS:
3376 rval = qla8044_minidump_process_l2tag(vha,
3377 entry_hdr, &data_ptr);
3378 if (rval != QLA_SUCCESS) {
3379 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3380 goto md_failed;
3381 }
3382 break;
3383 case QLA8044_L1DTG:
3384 case QLA8044_L1ITG:
3385 case QLA82XX_L1DAT:
3386 case QLA82XX_L1INS:
3387 qla8044_minidump_process_l1cache(vha,
3388 entry_hdr, &data_ptr);
3389 break;
3390 case QLA82XX_RDOCM:
3391 qla8044_minidump_process_rdocm(vha,
3392 entry_hdr, &data_ptr);
3393 break;
3394 case QLA82XX_RDMUX:
3395 qla8044_minidump_process_rdmux(vha,
3396 entry_hdr, &data_ptr);
3397 break;
3398 case QLA82XX_QUEUE:
3399 qla8044_minidump_process_queue(vha,
3400 entry_hdr, &data_ptr);
3401 break;
3402 case QLA8044_POLLRD:
3403 rval = qla8044_minidump_process_pollrd(vha,
3404 entry_hdr, &data_ptr);
3405 if (rval != QLA_SUCCESS)
3406 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3407 break;
3408 case QLA8044_RDMUX2:
3409 qla8044_minidump_process_rdmux2(vha,
3410 entry_hdr, &data_ptr);
3411 break;
3412 case QLA8044_POLLRDMWR:
3413 rval = qla8044_minidump_process_pollrdmwr(vha,
3414 entry_hdr, &data_ptr);
3415 if (rval != QLA_SUCCESS)
3416 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3417 break;
3418 case QLA8044_RDDFE:
3419 rval = qla8044_minidump_process_rddfe(vha, entry_hdr,
3420 &data_ptr);
3421 if (rval != QLA_SUCCESS)
3422 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3423 break;
3424 case QLA8044_RDMDIO:
3425 rval = qla8044_minidump_process_rdmdio(vha, entry_hdr,
3426 &data_ptr);
3427 if (rval != QLA_SUCCESS)
3428 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3429 break;
3430 case QLA8044_POLLWR:
3431 rval = qla8044_minidump_process_pollwr(vha, entry_hdr,
3432 &data_ptr);
3433 if (rval != QLA_SUCCESS)
3434 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3435 break;
3436 case QLA82XX_RDNOP:
3437 default:
3438 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3439 break;
3440 }
3441
3442 data_collected = (uint8_t *)data_ptr -
3443 (uint8_t *)((uint8_t *)ha->md_dump);
3444 skip_nxt_entry:
3445 /*
3446 * next entry in the template
3447 */
3448 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3449 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
3450 }
3451
3452 if (data_collected != ha->md_dump_size) {
3453 ql_log(ql_log_info, vha, 0xb105,
3454 "Dump data mismatch: Data collected: "
3455 "[0x%x], total_data_size:[0x%x]\n",
3456 data_collected, ha->md_dump_size);
3457 rval = QLA_FUNCTION_FAILED;
3458 goto md_failed;
3459 }
3460
3461 ql_log(ql_log_info, vha, 0xb110,
3462 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3463 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3464 ha->fw_dumped = 1;
3465 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3466
3467
3468 ql_log(ql_log_info, vha, 0xb106,
3469 "Leaving fn: %s Last entry: 0x%x\n",
3470 __func__, i);
3471 md_failed:
3472 return rval;
3473 }
3474
3475 void
3476 qla8044_get_minidump(struct scsi_qla_host *vha)
3477 {
3478 struct qla_hw_data *ha = vha->hw;
3479
3480 if (!qla8044_collect_md_data(vha)) {
3481 ha->fw_dumped = 1;
3482 ha->prev_minidump_failed = 0;
3483 } else {
3484 ql_log(ql_log_fatal, vha, 0xb0db,
3485 "%s: Unable to collect minidump\n",
3486 __func__);
3487 ha->prev_minidump_failed = 1;
3488 }
3489 }
3490
3491 static int
3492 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3493 {
3494 uint32_t flash_status;
3495 int retries = QLA8044_FLASH_READ_RETRY_COUNT;
3496 int ret_val = QLA_SUCCESS;
3497
3498 while (retries--) {
3499 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3500 &flash_status);
3501 if (ret_val) {
3502 ql_log(ql_log_warn, vha, 0xb13c,
3503 "%s: Failed to read FLASH_STATUS reg.\n",
3504 __func__);
3505 break;
3506 }
3507 if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
3508 QLA8044_FLASH_STATUS_READY)
3509 break;
3510 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
3511 }
3512
3513 if (!retries)
3514 ret_val = QLA_FUNCTION_FAILED;
3515
3516 return ret_val;
3517 }
3518
3519 static int
3520 qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3521 uint32_t data)
3522 {
3523 int ret_val = QLA_SUCCESS;
3524 uint32_t cmd;
3525
3526 cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3527
3528 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3529 QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
3530 if (ret_val) {
3531 ql_log(ql_log_warn, vha, 0xb125,
3532 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3533 goto exit_func;
3534 }
3535
3536 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3537 if (ret_val) {
3538 ql_log(ql_log_warn, vha, 0xb126,
3539 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3540 goto exit_func;
3541 }
3542
3543 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3544 QLA8044_FLASH_SECOND_ERASE_MS_VAL);
3545 if (ret_val) {
3546 ql_log(ql_log_warn, vha, 0xb127,
3547 "%s: Failed to write to FLASH_CONTROL.\n", __func__);
3548 goto exit_func;
3549 }
3550
3551 ret_val = qla8044_poll_flash_status_reg(vha);
3552 if (ret_val)
3553 ql_log(ql_log_warn, vha, 0xb128,
3554 "%s: Error polling flash status reg.\n", __func__);
3555
3556 exit_func:
3557 return ret_val;
3558 }
3559
3560 /*
3561 * This function assumes that the flash lock is held.
3562 */
3563 static int
3564 qla8044_unprotect_flash(scsi_qla_host_t *vha)
3565 {
3566 int ret_val;
3567 struct qla_hw_data *ha = vha->hw;
3568
3569 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3570 if (ret_val)
3571 ql_log(ql_log_warn, vha, 0xb139,
3572 "%s: Write flash status failed.\n", __func__);
3573
3574 return ret_val;
3575 }
3576
3577 /*
3578 * This function assumes that the flash lock is held.
3579 */
3580 static int
3581 qla8044_protect_flash(scsi_qla_host_t *vha)
3582 {
3583 int ret_val;
3584 struct qla_hw_data *ha = vha->hw;
3585
3586 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3587 if (ret_val)
3588 ql_log(ql_log_warn, vha, 0xb13b,
3589 "%s: Write flash status failed.\n", __func__);
3590
3591 return ret_val;
3592 }
3593
3594
3595 static int
3596 qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3597 uint32_t sector_start_addr)
3598 {
3599 uint32_t reversed_addr;
3600 int ret_val = QLA_SUCCESS;
3601
3602 ret_val = qla8044_poll_flash_status_reg(vha);
3603 if (ret_val) {
3604 ql_log(ql_log_warn, vha, 0xb12e,
3605 "%s: Poll flash status after erase failed..\n", __func__);
3606 }
3607
3608 reversed_addr = (((sector_start_addr & 0xFF) << 16) |
3609 (sector_start_addr & 0xFF00) |
3610 ((sector_start_addr & 0xFF0000) >> 16));
3611
3612 ret_val = qla8044_wr_reg_indirect(vha,
3613 QLA8044_FLASH_WRDATA, reversed_addr);
3614 if (ret_val) {
3615 ql_log(ql_log_warn, vha, 0xb12f,
3616 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3617 }
3618 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3619 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3620 if (ret_val) {
3621 ql_log(ql_log_warn, vha, 0xb130,
3622 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3623 }
3624 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3625 QLA8044_FLASH_LAST_ERASE_MS_VAL);
3626 if (ret_val) {
3627 ql_log(ql_log_warn, vha, 0xb131,
3628 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3629 }
3630 ret_val = qla8044_poll_flash_status_reg(vha);
3631 if (ret_val) {
3632 ql_log(ql_log_warn, vha, 0xb132,
3633 "%s: Poll flash status failed.\n", __func__);
3634 }
3635
3636
3637 return ret_val;
3638 }
3639
3640 /*
3641 * qla8044_flash_write_u32 - Write data to flash
3642 *
3643 * @ha : Pointer to adapter structure
3644 * addr : Flash address to write to
3645 * p_data : Data to be written
3646 *
3647 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3648 *
3649 * NOTE: Lock should be held on entry
3650 */
3651 static int
3652 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3653 uint32_t *p_data)
3654 {
3655 int ret_val = QLA_SUCCESS;
3656
3657 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3658 0x00800000 | (addr >> 2));
3659 if (ret_val) {
3660 ql_log(ql_log_warn, vha, 0xb134,
3661 "%s: Failed write to FLASH_ADDR.\n", __func__);
3662 goto exit_func;
3663 }
3664 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3665 if (ret_val) {
3666 ql_log(ql_log_warn, vha, 0xb135,
3667 "%s: Failed write to FLASH_WRDATA.\n", __func__);
3668 goto exit_func;
3669 }
3670 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3671 if (ret_val) {
3672 ql_log(ql_log_warn, vha, 0xb136,
3673 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3674 goto exit_func;
3675 }
3676 ret_val = qla8044_poll_flash_status_reg(vha);
3677 if (ret_val) {
3678 ql_log(ql_log_warn, vha, 0xb137,
3679 "%s: Poll flash status failed.\n", __func__);
3680 }
3681
3682 exit_func:
3683 return ret_val;
3684 }
3685
3686 static int
3687 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3688 uint32_t faddr, uint32_t dwords)
3689 {
3690 int ret = QLA_FUNCTION_FAILED;
3691 uint32_t spi_val;
3692
3693 if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
3694 dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
3695 ql_dbg(ql_dbg_user, vha, 0xb123,
3696 "Got unsupported dwords = 0x%x.\n",
3697 dwords);
3698 return QLA_FUNCTION_FAILED;
3699 }
3700
3701 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3702 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3703 spi_val | QLA8044_FLASH_SPI_CTL);
3704 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3705 QLA8044_FLASH_FIRST_TEMP_VAL);
3706
3707 /* First DWORD write to FLASH_WRDATA */
3708 ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3709 *dwptr++);
3710 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3711 QLA8044_FLASH_FIRST_MS_PATTERN);
3712
3713 ret = qla8044_poll_flash_status_reg(vha);
3714 if (ret) {
3715 ql_log(ql_log_warn, vha, 0xb124,
3716 "%s: Failed.\n", __func__);
3717 goto exit_func;
3718 }
3719
3720 dwords--;
3721
3722 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3723 QLA8044_FLASH_SECOND_TEMP_VAL);
3724
3725
3726 /* Second to N-1 DWORDS writes */
3727 while (dwords != 1) {
3728 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3729 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3730 QLA8044_FLASH_SECOND_MS_PATTERN);
3731 ret = qla8044_poll_flash_status_reg(vha);
3732 if (ret) {
3733 ql_log(ql_log_warn, vha, 0xb129,
3734 "%s: Failed.\n", __func__);
3735 goto exit_func;
3736 }
3737 dwords--;
3738 }
3739
3740 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3741 QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
3742
3743 /* Last DWORD write */
3744 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3745 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3746 QLA8044_FLASH_LAST_MS_PATTERN);
3747 ret = qla8044_poll_flash_status_reg(vha);
3748 if (ret) {
3749 ql_log(ql_log_warn, vha, 0xb12a,
3750 "%s: Failed.\n", __func__);
3751 goto exit_func;
3752 }
3753 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3754
3755 if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
3756 ql_log(ql_log_warn, vha, 0xb12b,
3757 "%s: Failed.\n", __func__);
3758 spi_val = 0;
3759 /* Operation failed, clear error bit. */
3760 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3761 &spi_val);
3762 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3763 spi_val | QLA8044_FLASH_SPI_CTL);
3764 }
3765 exit_func:
3766 return ret;
3767 }
3768
3769 static int
3770 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3771 uint32_t faddr, uint32_t dwords)
3772 {
3773 int ret = QLA_FUNCTION_FAILED;
3774 uint32_t liter;
3775
3776 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3777 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3778 if (ret) {
3779 ql_dbg(ql_dbg_p3p, vha, 0xb141,
3780 "%s: flash address=%x data=%x.\n", __func__,
3781 faddr, *dwptr);
3782 break;
3783 }
3784 }
3785
3786 return ret;
3787 }
3788
3789 int
3790 qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3791 uint32_t offset, uint32_t length)
3792 {
3793 int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
3794 int dword_count, erase_sec_count;
3795 uint32_t erase_offset;
3796 uint8_t *p_cache, *p_src;
3797
3798 erase_offset = offset;
3799
3800 p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
3801 if (!p_cache)
3802 return QLA_FUNCTION_FAILED;
3803
3804 memcpy(p_cache, buf, length);
3805 p_src = p_cache;
3806 dword_count = length / sizeof(uint32_t);
3807 /* Since the offset and legth are sector aligned, it will be always
3808 * multiple of burst_iter_count (64)
3809 */
3810 burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
3811 erase_sec_count = length / QLA8044_SECTOR_SIZE;
3812
3813 /* Suspend HBA. */
3814 scsi_block_requests(vha->host);
3815 /* Lock and enable write for whole operation. */
3816 qla8044_flash_lock(vha);
3817 qla8044_unprotect_flash(vha);
3818
3819 /* Erasing the sectors */
3820 for (i = 0; i < erase_sec_count; i++) {
3821 rval = qla8044_erase_flash_sector(vha, erase_offset);
3822 ql_dbg(ql_dbg_user, vha, 0xb138,
3823 "Done erase of sector=0x%x.\n",
3824 erase_offset);
3825 if (rval) {
3826 ql_log(ql_log_warn, vha, 0xb121,
3827 "Failed to erase the sector having address: "
3828 "0x%x.\n", erase_offset);
3829 goto out;
3830 }
3831 erase_offset += QLA8044_SECTOR_SIZE;
3832 }
3833 ql_dbg(ql_dbg_user, vha, 0xb13f,
3834 "Got write for addr = 0x%x length=0x%x.\n",
3835 offset, length);
3836
3837 for (i = 0; i < burst_iter_count; i++) {
3838
3839 /* Go with write. */
3840 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3841 offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
3842 if (rval) {
3843 /* Buffer Mode failed skip to dword mode */
3844 ql_log(ql_log_warn, vha, 0xb122,
3845 "Failed to write flash in buffer mode, "
3846 "Reverting to slow-write.\n");
3847 rval = qla8044_write_flash_dword_mode(vha,
3848 (uint32_t *)p_src, offset,
3849 QLA8044_MAX_OPTROM_BURST_DWORDS);
3850 }
3851 p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3852 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3853 }
3854 ql_dbg(ql_dbg_user, vha, 0xb133,
3855 "Done writing.\n");
3856
3857 out:
3858 qla8044_protect_flash(vha);
3859 qla8044_flash_unlock(vha);
3860 scsi_unblock_requests(vha->host);
3861 kfree(p_cache);
3862
3863 return rval;
3864 }
3865
3866 #define LEG_INT_PTR_B31 (1 << 31)
3867 #define LEG_INT_PTR_B30 (1 << 30)
3868 #define PF_BITS_MASK (0xF << 16)
3869 /**
3870 * qla8044_intr_handler() - Process interrupts for the ISP8044
3871 * @irq:
3872 * @dev_id: SCSI driver HA context
3873 *
3874 * Called by system whenever the host adapter generates an interrupt.
3875 *
3876 * Returns handled flag.
3877 */
3878 irqreturn_t
3879 qla8044_intr_handler(int irq, void *dev_id)
3880 {
3881 scsi_qla_host_t *vha;
3882 struct qla_hw_data *ha;
3883 struct rsp_que *rsp;
3884 struct device_reg_82xx __iomem *reg;
3885 int status = 0;
3886 unsigned long flags;
3887 unsigned long iter;
3888 uint32_t stat;
3889 uint16_t mb[4];
3890 uint32_t leg_int_ptr = 0, pf_bit;
3891
3892 rsp = (struct rsp_que *) dev_id;
3893 if (!rsp) {
3894 ql_log(ql_log_info, NULL, 0xb143,
3895 "%s(): NULL response queue pointer\n", __func__);
3896 return IRQ_NONE;
3897 }
3898 ha = rsp->hw;
3899 vha = pci_get_drvdata(ha->pdev);
3900
3901 if (unlikely(pci_channel_offline(ha->pdev)))
3902 return IRQ_HANDLED;
3903
3904 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3905
3906 /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3907 if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
3908 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3909 "%s: Legacy Interrupt Bit 31 not set, "
3910 "spurious interrupt!\n", __func__);
3911 return IRQ_NONE;
3912 }
3913
3914 pf_bit = ha->portnum << 16;
3915 /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3916 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
3917 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3918 "%s: Incorrect function ID 0x%x in "
3919 "legacy interrupt register, "
3920 "ha->pf_bit = 0x%x\n", __func__,
3921 (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
3922 return IRQ_NONE;
3923 }
3924
3925 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3926 * Control register and poll till Legacy Interrupt Pointer register
3927 * bit32 is 0.
3928 */
3929 qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
3930 do {
3931 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3932 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
3933 break;
3934 } while (leg_int_ptr & (LEG_INT_PTR_B30));
3935
3936 reg = &ha->iobase->isp82;
3937 spin_lock_irqsave(&ha->hardware_lock, flags);
3938 for (iter = 1; iter--; ) {
3939
3940 if (RD_REG_DWORD(&reg->host_int)) {
3941 stat = RD_REG_DWORD(&reg->host_status);
3942 if ((stat & HSRX_RISC_INT) == 0)
3943 break;
3944
3945 switch (stat & 0xff) {
3946 case 0x1:
3947 case 0x2:
3948 case 0x10:
3949 case 0x11:
3950 qla82xx_mbx_completion(vha, MSW(stat));
3951 status |= MBX_INTERRUPT;
3952 break;
3953 case 0x12:
3954 mb[0] = MSW(stat);
3955 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
3956 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
3957 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
3958 qla2x00_async_event(vha, rsp, mb);
3959 break;
3960 case 0x13:
3961 qla24xx_process_response_queue(vha, rsp);
3962 break;
3963 default:
3964 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3965 "Unrecognized interrupt type "
3966 "(%d).\n", stat & 0xff);
3967 break;
3968 }
3969 }
3970 WRT_REG_DWORD(&reg->host_int, 0);
3971 }
3972
3973 qla2x00_handle_mbx_completion(ha, status);
3974 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3975
3976 return IRQ_HANDLED;
3977 }
3978
3979 static int
3980 qla8044_idc_dontreset(struct qla_hw_data *ha)
3981 {
3982 uint32_t idc_ctrl;
3983
3984 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3985 return idc_ctrl & DONTRESET_BIT0;
3986 }
3987
3988 static void
3989 qla8044_clear_rst_ready(scsi_qla_host_t *vha)
3990 {
3991 uint32_t drv_state;
3992
3993 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
3994
3995 /*
3996 * For ISP8044, drv_active register has 1 bit per function,
3997 * shift 1 by func_num to set a bit for the function.
3998 * For ISP82xx, drv_active has 4 bits per function
3999 */
4000 drv_state &= ~(1 << vha->hw->portnum);
4001
4002 ql_dbg(ql_dbg_p3p, vha, 0xb13d,
4003 "drv_state: 0x%08x\n", drv_state);
4004 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
4005 }
4006
4007 int
4008 qla8044_abort_isp(scsi_qla_host_t *vha)
4009 {
4010 int rval;
4011 uint32_t dev_state;
4012 struct qla_hw_data *ha = vha->hw;
4013
4014 qla8044_idc_lock(ha);
4015 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
4016
4017 if (ql2xdontresethba)
4018 qla8044_set_idc_dontreset(vha);
4019
4020 /* If device_state is NEED_RESET, go ahead with
4021 * Reset,irrespective of ql2xdontresethba. This is to allow a
4022 * non-reset-owner to force a reset. Non-reset-owner sets
4023 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
4024 * and then forces a Reset by setting device_state to
4025 * NEED_RESET. */
4026 if (dev_state == QLA8XXX_DEV_READY) {
4027 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
4028 * recovery */
4029 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
4030 ql_dbg(ql_dbg_p3p, vha, 0xb13e,
4031 "Reset recovery disabled\n");
4032 rval = QLA_FUNCTION_FAILED;
4033 goto exit_isp_reset;
4034 }
4035
4036 ql_dbg(ql_dbg_p3p, vha, 0xb140,
4037 "HW State: NEED RESET\n");
4038 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
4039 QLA8XXX_DEV_NEED_RESET);
4040 }
4041
4042 /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
4043 * and which drivers are present. Unlike ISP82XX, the function setting
4044 * NEED_RESET, may not be the Reset owner. */
4045 qla83xx_reset_ownership(vha);
4046
4047 qla8044_idc_unlock(ha);
4048 rval = qla8044_device_state_handler(vha);
4049 qla8044_idc_lock(ha);
4050 qla8044_clear_rst_ready(vha);
4051
4052 exit_isp_reset:
4053 qla8044_idc_unlock(ha);
4054 if (rval == QLA_SUCCESS) {
4055 ha->flags.isp82xx_fw_hung = 0;
4056 ha->flags.nic_core_reset_hdlr_active = 0;
4057 rval = qla82xx_restart_isp(vha);
4058 }
4059
4060 return rval;
4061 }
4062
4063 void
4064 qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4065 {
4066 struct qla_hw_data *ha = vha->hw;
4067
4068 if (!ha->allow_cna_fw_dump)
4069 return;
4070
4071 scsi_block_requests(vha->host);
4072 ha->flags.isp82xx_no_md_cap = 1;
4073 qla8044_idc_lock(ha);
4074 qla82xx_set_reset_owner(vha);
4075 qla8044_idc_unlock(ha);
4076 qla2x00_wait_for_chip_reset(vha);
4077 scsi_unblock_requests(vha->host);
4078 }
Linux with added FPC-III support