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Merge tag 'fixes-for-v4.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi...
[linux/fpc-iii.git] / drivers / bus / arm-ccn.c
blob97a9185af433f052f315ae99e12f41232a1b1a3d
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2014 ARM Limited
12 */
13
14 #include <linux/ctype.h>
15 #include <linux/hrtimer.h>
16 #include <linux/idr.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define CCN_NUM_XP_PORTS 2
25 #define CCN_NUM_VCS 4
26 #define CCN_NUM_REGIONS 256
27 #define CCN_REGION_SIZE 0x10000
28
29 #define CCN_ALL_OLY_ID 0xff00
30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
31 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
33 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
34
35 #define CCN_MN_ERRINT_STATUS 0x0008
36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
46 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
47 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
48 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
49
50 #define CCN_DT_ACTIVE_DSM 0x0000
51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
53 #define CCN_DT_CTL 0x0028
54 #define CCN_DT_CTL__DT_EN (1 << 0)
55 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
56 #define CCN_DT_PMCCNTR 0x0140
57 #define CCN_DT_PMCCNTRSR 0x0190
58 #define CCN_DT_PMOVSR 0x0198
59 #define CCN_DT_PMOVSR_CLR 0x01a0
60 #define CCN_DT_PMOVSR_CLR__MASK 0x1f
61 #define CCN_DT_PMCR 0x01a8
62 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
63 #define CCN_DT_PMCR__PMU_EN (1 << 0)
64 #define CCN_DT_PMSR 0x01b0
65 #define CCN_DT_PMSR_REQ 0x01b8
66 #define CCN_DT_PMSR_CLR 0x01c0
67
68 #define CCN_HNF_PMU_EVENT_SEL 0x0600
69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
71
72 #define CCN_XP_DT_CONFIG 0x0300
73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
80 #define CCN_XP_DT_INTERFACE_SEL 0x0308
81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
87 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
88 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
89 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
90 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
91 #define CCN_XP_DT_CONTROL 0x0370
92 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
96 #define CCN_XP_PMU_EVENT_SEL 0x0600
97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
99
100 #define CCN_SBAS_PMU_EVENT_SEL 0x0600
101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
103
104 #define CCN_RNI_PMU_EVENT_SEL 0x0600
105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
107
108 #define CCN_TYPE_MN 0x01
109 #define CCN_TYPE_DT 0x02
110 #define CCN_TYPE_HNF 0x04
111 #define CCN_TYPE_HNI 0x05
112 #define CCN_TYPE_XP 0x08
113 #define CCN_TYPE_SBSX 0x0c
114 #define CCN_TYPE_SBAS 0x10
115 #define CCN_TYPE_RNI_1P 0x14
116 #define CCN_TYPE_RNI_2P 0x15
117 #define CCN_TYPE_RNI_3P 0x16
118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
119 #define CCN_TYPE_RND_2P 0x19
120 #define CCN_TYPE_RND_3P 0x1a
121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
122
123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
124
125 #define CCN_NUM_PMU_EVENTS 4
126 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
127 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
128 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
129
130 #define CCN_NUM_PREDEFINED_MASKS 4
131 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
132 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
133 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
134 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
135
136 struct arm_ccn_component {
137 void __iomem *base;
138 u32 type;
139
140 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
141 union {
142 struct {
143 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
144 } xp;
145 };
146 };
147
148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
149 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
150
151 struct arm_ccn_dt {
152 int id;
153 void __iomem *base;
154
155 spinlock_t config_lock;
156
157 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
158 struct {
159 struct arm_ccn_component *source;
160 struct perf_event *event;
161 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
162
163 struct {
164 u64 l, h;
165 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
166
167 struct hrtimer hrtimer;
168
169 cpumask_t cpu;
170 struct list_head entry;
171
172 struct pmu pmu;
173 };
174
175 struct arm_ccn {
176 struct device *dev;
177 void __iomem *base;
178 unsigned int irq;
179
180 unsigned sbas_present:1;
181 unsigned sbsx_present:1;
182
183 int num_nodes;
184 struct arm_ccn_component *node;
185
186 int num_xps;
187 struct arm_ccn_component *xp;
188
189 struct arm_ccn_dt dt;
190 };
191
192 static DEFINE_MUTEX(arm_ccn_mutex);
193 static LIST_HEAD(arm_ccn_list);
194
195 static int arm_ccn_node_to_xp(int node)
196 {
197 return node / CCN_NUM_XP_PORTS;
198 }
199
200 static int arm_ccn_node_to_xp_port(int node)
201 {
202 return node % CCN_NUM_XP_PORTS;
203 }
204
205
206 /*
207 * Bit shifts and masks in these defines must be kept in sync with
208 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
209 */
210 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
211 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
212 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
213 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
214 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
215 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
216 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
217 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
218
219 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
220 {
221 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
222 *config |= (node_xp << 0) | (type << 8) | (port << 24);
223 }
224
225 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
226 struct device_attribute *attr, char *buf)
227 {
228 struct dev_ext_attribute *ea = container_of(attr,
229 struct dev_ext_attribute, attr);
230
231 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
232 }
233
234 #define CCN_FORMAT_ATTR(_name, _config) \
235 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
236 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
237 NULL), _config }
238
239 static CCN_FORMAT_ATTR(node, "config:0-7");
240 static CCN_FORMAT_ATTR(xp, "config:0-7");
241 static CCN_FORMAT_ATTR(type, "config:8-15");
242 static CCN_FORMAT_ATTR(event, "config:16-23");
243 static CCN_FORMAT_ATTR(port, "config:24-25");
244 static CCN_FORMAT_ATTR(vc, "config:26-28");
245 static CCN_FORMAT_ATTR(dir, "config:29-29");
246 static CCN_FORMAT_ATTR(mask, "config:30-33");
247 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
248 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
249
250 static struct attribute *arm_ccn_pmu_format_attrs[] = {
251 &arm_ccn_pmu_format_attr_node.attr.attr,
252 &arm_ccn_pmu_format_attr_xp.attr.attr,
253 &arm_ccn_pmu_format_attr_type.attr.attr,
254 &arm_ccn_pmu_format_attr_event.attr.attr,
255 &arm_ccn_pmu_format_attr_port.attr.attr,
256 &arm_ccn_pmu_format_attr_vc.attr.attr,
257 &arm_ccn_pmu_format_attr_dir.attr.attr,
258 &arm_ccn_pmu_format_attr_mask.attr.attr,
259 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
260 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
261 NULL
262 };
263
264 static struct attribute_group arm_ccn_pmu_format_attr_group = {
265 .name = "format",
266 .attrs = arm_ccn_pmu_format_attrs,
267 };
268
269
270 struct arm_ccn_pmu_event {
271 struct device_attribute attr;
272 u32 type;
273 u32 event;
274 int num_ports;
275 int num_vcs;
276 const char *def;
277 int mask;
278 };
279
280 #define CCN_EVENT_ATTR(_name) \
281 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
282
283 /*
284 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
285 * their ports in XP they are connected to. For the sake of usability they are
286 * explicitly defined here (and translated into a relevant watchpoint in
287 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
288 * knowledge of the flit format.
289 */
290
291 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
292 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
293 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
294 .def = _def, .mask = _mask, }
295
296 #define CCN_EVENT_HNI(_name, _def, _mask) { \
297 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
298 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
299 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
300
301 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
302 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
303 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
304 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
305
306 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
307 .type = CCN_TYPE_HNF, .event = _event, }
308
309 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
310 .type = CCN_TYPE_XP, .event = _event, \
311 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
312
313 /*
314 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
315 * on configuration. One of them is picked to represent the whole group,
316 * as they all share the same event types.
317 */
318 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
319 .type = CCN_TYPE_RNI_3P, .event = _event, }
320
321 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
322 .type = CCN_TYPE_SBAS, .event = _event, }
323
324 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
325 .type = CCN_TYPE_CYCLES }
326
327
328 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
329 struct device_attribute *attr, char *buf)
330 {
331 struct arm_ccn_pmu_event *event = container_of(attr,
332 struct arm_ccn_pmu_event, attr);
333 ssize_t res;
334
335 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
336 if (event->event)
337 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
338 event->event);
339 if (event->def)
340 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
341 event->def);
342 if (event->mask)
343 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
344 event->mask);
345
346 /* Arguments required by an event */
347 switch (event->type) {
348 case CCN_TYPE_CYCLES:
349 break;
350 case CCN_TYPE_XP:
351 res += snprintf(buf + res, PAGE_SIZE - res,
352 ",xp=?,port=?,vc=?,dir=?");
353 if (event->event == CCN_EVENT_WATCHPOINT)
354 res += snprintf(buf + res, PAGE_SIZE - res,
355 ",cmp_l=?,cmp_h=?,mask=?");
356 break;
357 default:
358 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
359 break;
360 }
361
362 res += snprintf(buf + res, PAGE_SIZE - res, "\n");
363
364 return res;
365 }
366
367 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
368 struct attribute *attr, int index)
369 {
370 struct device *dev = kobj_to_dev(kobj);
371 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
372 struct device_attribute *dev_attr = container_of(attr,
373 struct device_attribute, attr);
374 struct arm_ccn_pmu_event *event = container_of(dev_attr,
375 struct arm_ccn_pmu_event, attr);
376
377 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
378 return 0;
379 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
380 return 0;
381
382 return attr->mode;
383 }
384
385 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
386 CCN_EVENT_MN(eobarrier, "dir=0,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
387 CCN_EVENT_MN(ecbarrier, "dir=0,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
388 CCN_EVENT_MN(dvmop, "dir=0,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
389 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
390 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
391 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
392 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
393 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
394 CCN_IDX_MASK_ORDER),
395 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
396 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
397 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
398 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
399 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
400 CCN_IDX_MASK_ORDER),
401 CCN_EVENT_HNF(cache_miss, 0x1),
402 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
403 CCN_EVENT_HNF(cache_fill, 0x3),
404 CCN_EVENT_HNF(pocq_retry, 0x4),
405 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
406 CCN_EVENT_HNF(sf_hit, 0x6),
407 CCN_EVENT_HNF(sf_evictions, 0x7),
408 CCN_EVENT_HNF(snoops_sent, 0x8),
409 CCN_EVENT_HNF(snoops_broadcast, 0x9),
410 CCN_EVENT_HNF(l3_eviction, 0xa),
411 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
412 CCN_EVENT_HNF(mc_retries, 0xc),
413 CCN_EVENT_HNF(mc_reqs, 0xd),
414 CCN_EVENT_HNF(qos_hh_retry, 0xe),
415 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
416 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
417 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
418 CCN_EVENT_RNI(rxdat_flits, 0x4),
419 CCN_EVENT_RNI(txdat_flits, 0x5),
420 CCN_EVENT_RNI(txreq_flits, 0x6),
421 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
422 CCN_EVENT_RNI(rrt_full, 0x8),
423 CCN_EVENT_RNI(wrt_full, 0x9),
424 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
425 CCN_EVENT_XP(upload_starvation, 0x1),
426 CCN_EVENT_XP(download_starvation, 0x2),
427 CCN_EVENT_XP(respin, 0x3),
428 CCN_EVENT_XP(valid_flit, 0x4),
429 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
430 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
431 CCN_EVENT_SBAS(rxdat_flits, 0x4),
432 CCN_EVENT_SBAS(txdat_flits, 0x5),
433 CCN_EVENT_SBAS(txreq_flits, 0x6),
434 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
435 CCN_EVENT_SBAS(rrt_full, 0x8),
436 CCN_EVENT_SBAS(wrt_full, 0x9),
437 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
438 CCN_EVENT_CYCLES(cycles),
439 };
440
441 /* Populated in arm_ccn_init() */
442 static struct attribute
443 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
444
445 static struct attribute_group arm_ccn_pmu_events_attr_group = {
446 .name = "events",
447 .is_visible = arm_ccn_pmu_events_is_visible,
448 .attrs = arm_ccn_pmu_events_attrs,
449 };
450
451
452 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
453 {
454 unsigned long i;
455
456 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
457 return NULL;
458 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
459
460 switch (name[1]) {
461 case 'l':
462 return &ccn->dt.cmp_mask[i].l;
463 case 'h':
464 return &ccn->dt.cmp_mask[i].h;
465 default:
466 return NULL;
467 }
468 }
469
470 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
471 struct device_attribute *attr, char *buf)
472 {
473 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
474 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
475
476 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
477 }
478
479 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
480 struct device_attribute *attr, const char *buf, size_t count)
481 {
482 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
483 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
484 int err = -EINVAL;
485
486 if (mask)
487 err = kstrtoull(buf, 0, mask);
488
489 return err ? err : count;
490 }
491
492 #define CCN_CMP_MASK_ATTR(_name) \
493 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
494 __ATTR(_name, S_IRUGO | S_IWUSR, \
495 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
496
497 #define CCN_CMP_MASK_ATTR_RO(_name) \
498 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
499 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
500
501 static CCN_CMP_MASK_ATTR(0l);
502 static CCN_CMP_MASK_ATTR(0h);
503 static CCN_CMP_MASK_ATTR(1l);
504 static CCN_CMP_MASK_ATTR(1h);
505 static CCN_CMP_MASK_ATTR(2l);
506 static CCN_CMP_MASK_ATTR(2h);
507 static CCN_CMP_MASK_ATTR(3l);
508 static CCN_CMP_MASK_ATTR(3h);
509 static CCN_CMP_MASK_ATTR(4l);
510 static CCN_CMP_MASK_ATTR(4h);
511 static CCN_CMP_MASK_ATTR(5l);
512 static CCN_CMP_MASK_ATTR(5h);
513 static CCN_CMP_MASK_ATTR(6l);
514 static CCN_CMP_MASK_ATTR(6h);
515 static CCN_CMP_MASK_ATTR(7l);
516 static CCN_CMP_MASK_ATTR(7h);
517 static CCN_CMP_MASK_ATTR_RO(8l);
518 static CCN_CMP_MASK_ATTR_RO(8h);
519 static CCN_CMP_MASK_ATTR_RO(9l);
520 static CCN_CMP_MASK_ATTR_RO(9h);
521 static CCN_CMP_MASK_ATTR_RO(al);
522 static CCN_CMP_MASK_ATTR_RO(ah);
523 static CCN_CMP_MASK_ATTR_RO(bl);
524 static CCN_CMP_MASK_ATTR_RO(bh);
525
526 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
527 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
528 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
529 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
530 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
531 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
532 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
533 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
534 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
535 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
536 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
537 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
538 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
539 NULL
540 };
541
542 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
543 .name = "cmp_mask",
544 .attrs = arm_ccn_pmu_cmp_mask_attrs,
545 };
546
547 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
548 struct device_attribute *attr, char *buf)
549 {
550 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
551
552 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);
553 }
554
555 static struct device_attribute arm_ccn_pmu_cpumask_attr =
556 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
557
558 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
559 &arm_ccn_pmu_cpumask_attr.attr,
560 NULL,
561 };
562
563 static struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
564 .attrs = arm_ccn_pmu_cpumask_attrs,
565 };
566
567 /*
568 * Default poll period is 10ms, which is way over the top anyway,
569 * as in the worst case scenario (an event every cycle), with 1GHz
570 * clocked bus, the smallest, 32 bit counter will overflow in
571 * more than 4s.
572 */
573 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
574 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
575 S_IRUGO | S_IWUSR);
576
577 static ktime_t arm_ccn_pmu_timer_period(void)
578 {
579 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
580 }
581
582
583 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
584 &arm_ccn_pmu_events_attr_group,
585 &arm_ccn_pmu_format_attr_group,
586 &arm_ccn_pmu_cmp_mask_attr_group,
587 &arm_ccn_pmu_cpumask_attr_group,
588 NULL
589 };
590
591
592 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
593 {
594 int bit;
595
596 do {
597 bit = find_first_zero_bit(bitmap, size);
598 if (bit >= size)
599 return -EAGAIN;
600 } while (test_and_set_bit(bit, bitmap));
601
602 return bit;
603 }
604
605 /* All RN-I and RN-D nodes have identical PMUs */
606 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
607 {
608 if (a == b)
609 return 1;
610
611 switch (a) {
612 case CCN_TYPE_RNI_1P:
613 case CCN_TYPE_RNI_2P:
614 case CCN_TYPE_RNI_3P:
615 case CCN_TYPE_RND_1P:
616 case CCN_TYPE_RND_2P:
617 case CCN_TYPE_RND_3P:
618 switch (b) {
619 case CCN_TYPE_RNI_1P:
620 case CCN_TYPE_RNI_2P:
621 case CCN_TYPE_RNI_3P:
622 case CCN_TYPE_RND_1P:
623 case CCN_TYPE_RND_2P:
624 case CCN_TYPE_RND_3P:
625 return 1;
626 }
627 break;
628 }
629
630 return 0;
631 }
632
633 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
634 {
635 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
636 struct hw_perf_event *hw = &event->hw;
637 u32 node_xp, type, event_id;
638 struct arm_ccn_component *source;
639 int bit;
640
641 node_xp = CCN_CONFIG_NODE(event->attr.config);
642 type = CCN_CONFIG_TYPE(event->attr.config);
643 event_id = CCN_CONFIG_EVENT(event->attr.config);
644
645 /* Allocate the cycle counter */
646 if (type == CCN_TYPE_CYCLES) {
647 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
648 ccn->dt.pmu_counters_mask))
649 return -EAGAIN;
650
651 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
652 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
653
654 return 0;
655 }
656
657 /* Allocate an event counter */
658 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
659 CCN_NUM_PMU_EVENT_COUNTERS);
660 if (hw->idx < 0) {
661 dev_dbg(ccn->dev, "No more counters available!\n");
662 return -EAGAIN;
663 }
664
665 if (type == CCN_TYPE_XP)
666 source = &ccn->xp[node_xp];
667 else
668 source = &ccn->node[node_xp];
669 ccn->dt.pmu_counters[hw->idx].source = source;
670
671 /* Allocate an event source or a watchpoint */
672 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
673 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
674 CCN_NUM_XP_WATCHPOINTS);
675 else
676 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
677 CCN_NUM_PMU_EVENTS);
678 if (bit < 0) {
679 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
680 node_xp);
681 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
682 return -EAGAIN;
683 }
684 hw->config_base = bit;
685
686 ccn->dt.pmu_counters[hw->idx].event = event;
687
688 return 0;
689 }
690
691 static void arm_ccn_pmu_event_release(struct perf_event *event)
692 {
693 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
694 struct hw_perf_event *hw = &event->hw;
695
696 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
697 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
698 } else {
699 struct arm_ccn_component *source =
700 ccn->dt.pmu_counters[hw->idx].source;
701
702 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
703 CCN_CONFIG_EVENT(event->attr.config) ==
704 CCN_EVENT_WATCHPOINT)
705 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
706 else
707 clear_bit(hw->config_base, source->pmu_events_mask);
708 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
709 }
710
711 ccn->dt.pmu_counters[hw->idx].source = NULL;
712 ccn->dt.pmu_counters[hw->idx].event = NULL;
713 }
714
715 static int arm_ccn_pmu_event_init(struct perf_event *event)
716 {
717 struct arm_ccn *ccn;
718 struct hw_perf_event *hw = &event->hw;
719 u32 node_xp, type, event_id;
720 int valid;
721 int i;
722 struct perf_event *sibling;
723
724 if (event->attr.type != event->pmu->type)
725 return -ENOENT;
726
727 ccn = pmu_to_arm_ccn(event->pmu);
728
729 if (hw->sample_period) {
730 dev_warn(ccn->dev, "Sampling not supported!\n");
731 return -EOPNOTSUPP;
732 }
733
734 if (has_branch_stack(event) || event->attr.exclude_user ||
735 event->attr.exclude_kernel || event->attr.exclude_hv ||
736 event->attr.exclude_idle) {
737 dev_warn(ccn->dev, "Can't exclude execution levels!\n");
738 return -EOPNOTSUPP;
739 }
740
741 if (event->cpu < 0) {
742 dev_warn(ccn->dev, "Can't provide per-task data!\n");
743 return -EOPNOTSUPP;
744 }
745 /*
746 * Many perf core operations (eg. events rotation) operate on a
747 * single CPU context. This is obvious for CPU PMUs, where one
748 * expects the same sets of events being observed on all CPUs,
749 * but can lead to issues for off-core PMUs, like CCN, where each
750 * event could be theoretically assigned to a different CPU. To
751 * mitigate this, we enforce CPU assignment to one, selected
752 * processor (the one described in the "cpumask" attribute).
753 */
754 event->cpu = cpumask_first(&ccn->dt.cpu);
755
756 node_xp = CCN_CONFIG_NODE(event->attr.config);
757 type = CCN_CONFIG_TYPE(event->attr.config);
758 event_id = CCN_CONFIG_EVENT(event->attr.config);
759
760 /* Validate node/xp vs topology */
761 switch (type) {
762 case CCN_TYPE_XP:
763 if (node_xp >= ccn->num_xps) {
764 dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
765 return -EINVAL;
766 }
767 break;
768 case CCN_TYPE_CYCLES:
769 break;
770 default:
771 if (node_xp >= ccn->num_nodes) {
772 dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
773 return -EINVAL;
774 }
775 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
776 dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
777 type, node_xp);
778 return -EINVAL;
779 }
780 break;
781 }
782
783 /* Validate event ID vs available for the type */
784 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
785 i++) {
786 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
787 u32 port = CCN_CONFIG_PORT(event->attr.config);
788 u32 vc = CCN_CONFIG_VC(event->attr.config);
789
790 if (!arm_ccn_pmu_type_eq(type, e->type))
791 continue;
792 if (event_id != e->event)
793 continue;
794 if (e->num_ports && port >= e->num_ports) {
795 dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
796 port, node_xp);
797 return -EINVAL;
798 }
799 if (e->num_vcs && vc >= e->num_vcs) {
800 dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
801 vc, node_xp);
802 return -EINVAL;
803 }
804 valid = 1;
805 }
806 if (!valid) {
807 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
808 event_id, node_xp);
809 return -EINVAL;
810 }
811
812 /* Watchpoint-based event for a node is actually set on XP */
813 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
814 u32 port;
815
816 type = CCN_TYPE_XP;
817 port = arm_ccn_node_to_xp_port(node_xp);
818 node_xp = arm_ccn_node_to_xp(node_xp);
819
820 arm_ccn_pmu_config_set(&event->attr.config,
821 node_xp, type, port);
822 }
823
824 /*
825 * We must NOT create groups containing mixed PMUs, although software
826 * events are acceptable (for example to create a CCN group
827 * periodically read when a hrtimer aka cpu-clock leader triggers).
828 */
829 if (event->group_leader->pmu != event->pmu &&
830 !is_software_event(event->group_leader))
831 return -EINVAL;
832
833 list_for_each_entry(sibling, &event->group_leader->sibling_list,
834 group_entry)
835 if (sibling->pmu != event->pmu &&
836 !is_software_event(sibling))
837 return -EINVAL;
838
839 return 0;
840 }
841
842 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
843 {
844 u64 res;
845
846 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
847 #ifdef readq
848 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
849 #else
850 /* 40 bit counter, can do snapshot and read in two parts */
851 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
852 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
853 ;
854 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
855 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
856 res <<= 32;
857 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
858 #endif
859 } else {
860 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
861 }
862
863 return res;
864 }
865
866 static void arm_ccn_pmu_event_update(struct perf_event *event)
867 {
868 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
869 struct hw_perf_event *hw = &event->hw;
870 u64 prev_count, new_count, mask;
871
872 do {
873 prev_count = local64_read(&hw->prev_count);
874 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
875 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
876
877 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
878
879 local64_add((new_count - prev_count) & mask, &event->count);
880 }
881
882 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
883 {
884 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
885 struct hw_perf_event *hw = &event->hw;
886 struct arm_ccn_component *xp;
887 u32 val, dt_cfg;
888
889 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
890 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
891 else
892 xp = &ccn->xp[arm_ccn_node_to_xp(
893 CCN_CONFIG_NODE(event->attr.config))];
894
895 if (enable)
896 dt_cfg = hw->event_base;
897 else
898 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
899
900 spin_lock(&ccn->dt.config_lock);
901
902 val = readl(xp->base + CCN_XP_DT_CONFIG);
903 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
904 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
905 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
906 writel(val, xp->base + CCN_XP_DT_CONFIG);
907
908 spin_unlock(&ccn->dt.config_lock);
909 }
910
911 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
912 {
913 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
914 struct hw_perf_event *hw = &event->hw;
915
916 local64_set(&event->hw.prev_count,
917 arm_ccn_pmu_read_counter(ccn, hw->idx));
918 hw->state = 0;
919
920 /*
921 * Pin the timer, so that the overflows are handled by the chosen
922 * event->cpu (this is the same one as presented in "cpumask"
923 * attribute).
924 */
925 if (!ccn->irq)
926 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
927 HRTIMER_MODE_REL_PINNED);
928
929 /* Set the DT bus input, engaging the counter */
930 arm_ccn_pmu_xp_dt_config(event, 1);
931 }
932
933 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
934 {
935 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
936 struct hw_perf_event *hw = &event->hw;
937 u64 timeout;
938
939 /* Disable counting, setting the DT bus to pass-through mode */
940 arm_ccn_pmu_xp_dt_config(event, 0);
941
942 if (!ccn->irq)
943 hrtimer_cancel(&ccn->dt.hrtimer);
944
945 /* Let the DT bus drain */
946 timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
947 ccn->num_xps;
948 while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
949 timeout)
950 cpu_relax();
951
952 if (flags & PERF_EF_UPDATE)
953 arm_ccn_pmu_event_update(event);
954
955 hw->state |= PERF_HES_STOPPED;
956 }
957
958 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
959 {
960 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
961 struct hw_perf_event *hw = &event->hw;
962 struct arm_ccn_component *source =
963 ccn->dt.pmu_counters[hw->idx].source;
964 unsigned long wp = hw->config_base;
965 u32 val;
966 u64 cmp_l = event->attr.config1;
967 u64 cmp_h = event->attr.config2;
968 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
969 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
970
971 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
972
973 /* Direction (RX/TX), device (port) & virtual channel */
974 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
975 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
976 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
977 val |= CCN_CONFIG_DIR(event->attr.config) <<
978 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
979 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
980 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
981 val |= CCN_CONFIG_PORT(event->attr.config) <<
982 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
983 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
984 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
985 val |= CCN_CONFIG_VC(event->attr.config) <<
986 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
987 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
988
989 /* Comparison values */
990 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
991 writel((cmp_l >> 32) & 0xefffffff,
992 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
993 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
994 writel((cmp_h >> 32) & 0x0fffffff,
995 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
996
997 /* Mask */
998 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
999 writel((mask_l >> 32) & 0xefffffff,
1000 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
1001 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
1002 writel((mask_h >> 32) & 0x0fffffff,
1003 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1004 }
1005
1006 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
1007 {
1008 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1009 struct hw_perf_event *hw = &event->hw;
1010 struct arm_ccn_component *source =
1011 ccn->dt.pmu_counters[hw->idx].source;
1012 u32 val, id;
1013
1014 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1015
1016 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1017 (CCN_CONFIG_PORT(event->attr.config) << 3) |
1018 (CCN_CONFIG_EVENT(event->attr.config) << 0);
1019
1020 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1021 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1022 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1023 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1024 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1025 }
1026
1027 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1028 {
1029 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1030 struct hw_perf_event *hw = &event->hw;
1031 struct arm_ccn_component *source =
1032 ccn->dt.pmu_counters[hw->idx].source;
1033 u32 type = CCN_CONFIG_TYPE(event->attr.config);
1034 u32 val, port;
1035
1036 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1037 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1038 hw->config_base);
1039
1040 /* These *_event_sel regs should be identical, but let's make sure... */
1041 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1042 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1043 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1044 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1045 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1046 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1047 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1048 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1049 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1050 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1051 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1052 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1053 return;
1054
1055 /* Set the event id for the pre-allocated counter */
1056 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1057 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1058 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1059 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1060 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1061 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1062 }
1063
1064 static void arm_ccn_pmu_event_config(struct perf_event *event)
1065 {
1066 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1067 struct hw_perf_event *hw = &event->hw;
1068 u32 xp, offset, val;
1069
1070 /* Cycle counter requires no setup */
1071 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1072 return;
1073
1074 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1075 xp = CCN_CONFIG_XP(event->attr.config);
1076 else
1077 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1078
1079 spin_lock(&ccn->dt.config_lock);
1080
1081 /* Set the DT bus "distance" register */
1082 offset = (hw->idx / 4) * 4;
1083 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1084 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1085 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1086 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1087 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1088
1089 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1090 if (CCN_CONFIG_EVENT(event->attr.config) ==
1091 CCN_EVENT_WATCHPOINT)
1092 arm_ccn_pmu_xp_watchpoint_config(event);
1093 else
1094 arm_ccn_pmu_xp_event_config(event);
1095 } else {
1096 arm_ccn_pmu_node_event_config(event);
1097 }
1098
1099 spin_unlock(&ccn->dt.config_lock);
1100 }
1101
1102 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1103 {
1104 int err;
1105 struct hw_perf_event *hw = &event->hw;
1106
1107 err = arm_ccn_pmu_event_alloc(event);
1108 if (err)
1109 return err;
1110
1111 arm_ccn_pmu_event_config(event);
1112
1113 hw->state = PERF_HES_STOPPED;
1114
1115 if (flags & PERF_EF_START)
1116 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1117
1118 return 0;
1119 }
1120
1121 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1122 {
1123 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1124
1125 arm_ccn_pmu_event_release(event);
1126 }
1127
1128 static void arm_ccn_pmu_event_read(struct perf_event *event)
1129 {
1130 arm_ccn_pmu_event_update(event);
1131 }
1132
1133 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1134 {
1135 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1136 int idx;
1137
1138 if (!pmovsr)
1139 return IRQ_NONE;
1140
1141 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1142
1143 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1144
1145 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1146 struct perf_event *event = dt->pmu_counters[idx].event;
1147 int overflowed = pmovsr & BIT(idx);
1148
1149 WARN_ON_ONCE(overflowed && !event &&
1150 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1151
1152 if (!event || !overflowed)
1153 continue;
1154
1155 arm_ccn_pmu_event_update(event);
1156 }
1157
1158 return IRQ_HANDLED;
1159 }
1160
1161 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1162 {
1163 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1164 hrtimer);
1165 unsigned long flags;
1166
1167 local_irq_save(flags);
1168 arm_ccn_pmu_overflow_handler(dt);
1169 local_irq_restore(flags);
1170
1171 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1172 return HRTIMER_RESTART;
1173 }
1174
1175
1176 static int arm_ccn_pmu_offline_cpu(unsigned int cpu)
1177 {
1178 struct arm_ccn_dt *dt;
1179 unsigned int target;
1180
1181 mutex_lock(&arm_ccn_mutex);
1182 list_for_each_entry(dt, &arm_ccn_list, entry) {
1183 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1184
1185 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))
1186 continue;
1187 target = cpumask_any_but(cpu_online_mask, cpu);
1188 if (target >= nr_cpu_ids)
1189 continue;
1190 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1191 cpumask_set_cpu(target, &dt->cpu);
1192 if (ccn->irq)
1193 WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0);
1194 }
1195 mutex_unlock(&arm_ccn_mutex);
1196 return 0;
1197 }
1198
1199
1200 static DEFINE_IDA(arm_ccn_pmu_ida);
1201
1202 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1203 {
1204 int i;
1205 char *name;
1206 int err;
1207
1208 /* Initialize DT subsystem */
1209 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1210 spin_lock_init(&ccn->dt.config_lock);
1211 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1212 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1213 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1214 ccn->dt.base + CCN_DT_PMCR);
1215 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1216 for (i = 0; i < ccn->num_xps; i++) {
1217 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1218 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1219 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1220 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1221 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1222 CCN_XP_DT_CONTROL__DT_ENABLE,
1223 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1224 }
1225 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1226 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1227 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1228 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1229 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1230 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1231 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1232 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1233
1234 /* Get a convenient /sys/event_source/devices/ name */
1235 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1236 if (ccn->dt.id == 0) {
1237 name = "ccn";
1238 } else {
1239 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);
1240
1241 name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL);
1242 snprintf(name, len + 1, "ccn_%d", ccn->dt.id);
1243 }
1244
1245 /* Perf driver registration */
1246 ccn->dt.pmu = (struct pmu) {
1247 .attr_groups = arm_ccn_pmu_attr_groups,
1248 .task_ctx_nr = perf_invalid_context,
1249 .event_init = arm_ccn_pmu_event_init,
1250 .add = arm_ccn_pmu_event_add,
1251 .del = arm_ccn_pmu_event_del,
1252 .start = arm_ccn_pmu_event_start,
1253 .stop = arm_ccn_pmu_event_stop,
1254 .read = arm_ccn_pmu_event_read,
1255 };
1256
1257 /* No overflow interrupt? Have to use a timer instead. */
1258 if (!ccn->irq) {
1259 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1260 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1261 HRTIMER_MODE_REL);
1262 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1263 }
1264
1265 /* Pick one CPU which we will use to collect data from CCN... */
1266 cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu);
1267
1268 /* Also make sure that the overflow interrupt is handled by this CPU */
1269 if (ccn->irq) {
1270 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu);
1271 if (err) {
1272 dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1273 goto error_set_affinity;
1274 }
1275 }
1276
1277 err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1278 if (err)
1279 goto error_pmu_register;
1280
1281 mutex_lock(&arm_ccn_mutex);
1282 list_add(&ccn->dt.entry, &arm_ccn_list);
1283 mutex_unlock(&arm_ccn_mutex);
1284 return 0;
1285
1286 error_pmu_register:
1287 error_set_affinity:
1288 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1289 for (i = 0; i < ccn->num_xps; i++)
1290 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1291 writel(0, ccn->dt.base + CCN_DT_PMCR);
1292 return err;
1293 }
1294
1295 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1296 {
1297 int i;
1298
1299 mutex_lock(&arm_ccn_mutex);
1300 list_del(&ccn->dt.entry);
1301 mutex_unlock(&arm_ccn_mutex);
1302
1303 if (ccn->irq)
1304 irq_set_affinity_hint(ccn->irq, NULL);
1305 for (i = 0; i < ccn->num_xps; i++)
1306 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1307 writel(0, ccn->dt.base + CCN_DT_PMCR);
1308 perf_pmu_unregister(&ccn->dt.pmu);
1309 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1310 }
1311
1312 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1313 int (*callback)(struct arm_ccn *ccn, int region,
1314 void __iomem *base, u32 type, u32 id))
1315 {
1316 int region;
1317
1318 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1319 u32 val, type, id;
1320 void __iomem *base;
1321 int err;
1322
1323 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1324 4 * (region / 32));
1325 if (!(val & (1 << (region % 32))))
1326 continue;
1327
1328 base = ccn->base + region * CCN_REGION_SIZE;
1329 val = readl(base + CCN_ALL_OLY_ID);
1330 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1331 CCN_ALL_OLY_ID__OLY_ID__MASK;
1332 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1333 CCN_ALL_OLY_ID__NODE_ID__MASK;
1334
1335 err = callback(ccn, region, base, type, id);
1336 if (err)
1337 return err;
1338 }
1339
1340 return 0;
1341 }
1342
1343 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1344 void __iomem *base, u32 type, u32 id)
1345 {
1346
1347 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1348 ccn->num_xps = id + 1;
1349 else if (id >= ccn->num_nodes)
1350 ccn->num_nodes = id + 1;
1351
1352 return 0;
1353 }
1354
1355 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1356 void __iomem *base, u32 type, u32 id)
1357 {
1358 struct arm_ccn_component *component;
1359
1360 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1361
1362 switch (type) {
1363 case CCN_TYPE_MN:
1364 case CCN_TYPE_DT:
1365 return 0;
1366 case CCN_TYPE_XP:
1367 component = &ccn->xp[id];
1368 break;
1369 case CCN_TYPE_SBSX:
1370 ccn->sbsx_present = 1;
1371 component = &ccn->node[id];
1372 break;
1373 case CCN_TYPE_SBAS:
1374 ccn->sbas_present = 1;
1375 /* Fall-through */
1376 default:
1377 component = &ccn->node[id];
1378 break;
1379 }
1380
1381 component->base = base;
1382 component->type = type;
1383
1384 return 0;
1385 }
1386
1387
1388 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1389 const u32 *err_sig_val)
1390 {
1391 /* This should be really handled by firmware... */
1392 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1393 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1394 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1395 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1396 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1397 ccn->base + CCN_MN_ERRINT_STATUS);
1398
1399 return IRQ_HANDLED;
1400 }
1401
1402
1403 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1404 {
1405 irqreturn_t res = IRQ_NONE;
1406 struct arm_ccn *ccn = dev_id;
1407 u32 err_sig_val[6];
1408 u32 err_or;
1409 int i;
1410
1411 /* PMU overflow is a special case */
1412 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1413 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1414 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1415 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1416 }
1417
1418 /* Have to read all err_sig_vals to clear them */
1419 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1420 err_sig_val[i] = readl(ccn->base +
1421 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1422 err_or |= err_sig_val[i];
1423 }
1424 if (err_or)
1425 res |= arm_ccn_error_handler(ccn, err_sig_val);
1426
1427 if (res != IRQ_NONE)
1428 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1429 ccn->base + CCN_MN_ERRINT_STATUS);
1430
1431 return res;
1432 }
1433
1434
1435 static int arm_ccn_probe(struct platform_device *pdev)
1436 {
1437 struct arm_ccn *ccn;
1438 struct resource *res;
1439 unsigned int irq;
1440 int err;
1441
1442 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1443 if (!ccn)
1444 return -ENOMEM;
1445 ccn->dev = &pdev->dev;
1446 platform_set_drvdata(pdev, ccn);
1447
1448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1449 if (!res)
1450 return -EINVAL;
1451
1452 if (!devm_request_mem_region(ccn->dev, res->start,
1453 resource_size(res), pdev->name))
1454 return -EBUSY;
1455
1456 ccn->base = devm_ioremap(ccn->dev, res->start,
1457 resource_size(res));
1458 if (!ccn->base)
1459 return -EFAULT;
1460
1461 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1462 if (!res)
1463 return -EINVAL;
1464 irq = res->start;
1465
1466 /* Check if we can use the interrupt */
1467 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1468 ccn->base + CCN_MN_ERRINT_STATUS);
1469 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1470 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1471 /* Can set 'disable' bits, so can acknowledge interrupts */
1472 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1473 ccn->base + CCN_MN_ERRINT_STATUS);
1474 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
1475 dev_name(ccn->dev), ccn);
1476 if (err)
1477 return err;
1478
1479 ccn->irq = irq;
1480 }
1481
1482
1483 /* Build topology */
1484
1485 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1486 if (err)
1487 return err;
1488
1489 ccn->node = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_nodes,
1490 GFP_KERNEL);
1491 ccn->xp = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_xps,
1492 GFP_KERNEL);
1493 if (!ccn->node || !ccn->xp)
1494 return -ENOMEM;
1495
1496 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1497 if (err)
1498 return err;
1499
1500 return arm_ccn_pmu_init(ccn);
1501 }
1502
1503 static int arm_ccn_remove(struct platform_device *pdev)
1504 {
1505 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1506
1507 arm_ccn_pmu_cleanup(ccn);
1508
1509 return 0;
1510 }
1511
1512 static const struct of_device_id arm_ccn_match[] = {
1513 { .compatible = "arm,ccn-504", },
1514 {},
1515 };
1516
1517 static struct platform_driver arm_ccn_driver = {
1518 .driver = {
1519 .name = "arm-ccn",
1520 .of_match_table = arm_ccn_match,
1521 },
1522 .probe = arm_ccn_probe,
1523 .remove = arm_ccn_remove,
1524 };
1525
1526 static int __init arm_ccn_init(void)
1527 {
1528 int i, ret;
1529
1530 ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1531 "AP_PERF_ARM_CCN_ONLINE", NULL,
1532 arm_ccn_pmu_offline_cpu);
1533 if (ret)
1534 return ret;
1535
1536 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1537 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1538
1539 return platform_driver_register(&arm_ccn_driver);
1540 }
1541
1542 static void __exit arm_ccn_exit(void)
1543 {
1544 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1545 platform_driver_unregister(&arm_ccn_driver);
1546 }
1547
1548 module_init(arm_ccn_init);
1549 module_exit(arm_ccn_exit);
1550
1551 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1552 MODULE_LICENSE("GPL");
Linux with added FPC-III support