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pvrusb2: reduce stack usage pvr2_eeprom_analyze()
[linux/fpc-iii.git] / drivers / net / ethernet / renesas / ravb_main.c
blob510ff62584d6433cb9a4e8ed6d85abd9d3842e58
1 /* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34
35 #include <asm/div64.h>
36
37 #include "ravb.h"
38
39 #define RAVB_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
45 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
46 "ch0", /* RAVB_BE */
47 "ch1", /* RAVB_NC */
48 };
49
50 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
51 "ch18", /* RAVB_BE */
52 "ch19", /* RAVB_NC */
53 };
54
55 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
56 u32 set)
57 {
58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
59 }
60
61 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
62 {
63 int i;
64
65 for (i = 0; i < 10000; i++) {
66 if ((ravb_read(ndev, reg) & mask) == value)
67 return 0;
68 udelay(10);
69 }
70 return -ETIMEDOUT;
71 }
72
73 static int ravb_config(struct net_device *ndev)
74 {
75 int error;
76
77 /* Set config mode */
78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
79 /* Check if the operating mode is changed to the config mode */
80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
81 if (error)
82 netdev_err(ndev, "failed to switch device to config mode\n");
83
84 return error;
85 }
86
87 static void ravb_set_duplex(struct net_device *ndev)
88 {
89 struct ravb_private *priv = netdev_priv(ndev);
90
91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
92 }
93
94 static void ravb_set_rate(struct net_device *ndev)
95 {
96 struct ravb_private *priv = netdev_priv(ndev);
97
98 switch (priv->speed) {
99 case 100: /* 100BASE */
100 ravb_write(ndev, GECMR_SPEED_100, GECMR);
101 break;
102 case 1000: /* 1000BASE */
103 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
104 break;
105 }
106 }
107
108 static void ravb_set_buffer_align(struct sk_buff *skb)
109 {
110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
111
112 if (reserve)
113 skb_reserve(skb, RAVB_ALIGN - reserve);
114 }
115
116 /* Get MAC address from the MAC address registers
117 *
118 * Ethernet AVB device doesn't have ROM for MAC address.
119 * This function gets the MAC address that was used by a bootloader.
120 */
121 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
122 {
123 if (mac) {
124 ether_addr_copy(ndev->dev_addr, mac);
125 } else {
126 u32 mahr = ravb_read(ndev, MAHR);
127 u32 malr = ravb_read(ndev, MALR);
128
129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
133 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
134 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
135 }
136 }
137
138 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
139 {
140 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
141 mdiobb);
142
143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
144 }
145
146 /* MDC pin control */
147 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
148 {
149 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
150 }
151
152 /* Data I/O pin control */
153 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
154 {
155 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
156 }
157
158 /* Set data bit */
159 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
160 {
161 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
162 }
163
164 /* Get data bit */
165 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
166 {
167 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
168 mdiobb);
169
170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
171 }
172
173 /* MDIO bus control struct */
174 static struct mdiobb_ops bb_ops = {
175 .owner = THIS_MODULE,
176 .set_mdc = ravb_set_mdc,
177 .set_mdio_dir = ravb_set_mdio_dir,
178 .set_mdio_data = ravb_set_mdio_data,
179 .get_mdio_data = ravb_get_mdio_data,
180 };
181
182 /* Free TX skb function for AVB-IP */
183 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
184 {
185 struct ravb_private *priv = netdev_priv(ndev);
186 struct net_device_stats *stats = &priv->stats[q];
187 struct ravb_tx_desc *desc;
188 int free_num = 0;
189 int entry;
190 u32 size;
191
192 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
193 bool txed;
194
195 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
196 NUM_TX_DESC);
197 desc = &priv->tx_ring[q][entry];
198 txed = desc->die_dt == DT_FEMPTY;
199 if (free_txed_only && !txed)
200 break;
201 /* Descriptor type must be checked before all other reads */
202 dma_rmb();
203 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
204 /* Free the original skb. */
205 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
206 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
207 size, DMA_TO_DEVICE);
208 /* Last packet descriptor? */
209 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
210 entry /= NUM_TX_DESC;
211 dev_kfree_skb_any(priv->tx_skb[q][entry]);
212 priv->tx_skb[q][entry] = NULL;
213 if (txed)
214 stats->tx_packets++;
215 }
216 free_num++;
217 }
218 if (txed)
219 stats->tx_bytes += size;
220 desc->die_dt = DT_EEMPTY;
221 }
222 return free_num;
223 }
224
225 /* Free skb's and DMA buffers for Ethernet AVB */
226 static void ravb_ring_free(struct net_device *ndev, int q)
227 {
228 struct ravb_private *priv = netdev_priv(ndev);
229 int ring_size;
230 int i;
231
232 /* Free RX skb ringbuffer */
233 if (priv->rx_skb[q]) {
234 for (i = 0; i < priv->num_rx_ring[q]; i++)
235 dev_kfree_skb(priv->rx_skb[q][i]);
236 }
237 kfree(priv->rx_skb[q]);
238 priv->rx_skb[q] = NULL;
239
240 /* Free aligned TX buffers */
241 kfree(priv->tx_align[q]);
242 priv->tx_align[q] = NULL;
243
244 if (priv->rx_ring[q]) {
245 for (i = 0; i < priv->num_rx_ring[q]; i++) {
246 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
247
248 if (!dma_mapping_error(ndev->dev.parent,
249 le32_to_cpu(desc->dptr)))
250 dma_unmap_single(ndev->dev.parent,
251 le32_to_cpu(desc->dptr),
252 PKT_BUF_SZ,
253 DMA_FROM_DEVICE);
254 }
255 ring_size = sizeof(struct ravb_ex_rx_desc) *
256 (priv->num_rx_ring[q] + 1);
257 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
258 priv->rx_desc_dma[q]);
259 priv->rx_ring[q] = NULL;
260 }
261
262 if (priv->tx_ring[q]) {
263 ravb_tx_free(ndev, q, false);
264
265 ring_size = sizeof(struct ravb_tx_desc) *
266 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
268 priv->tx_desc_dma[q]);
269 priv->tx_ring[q] = NULL;
270 }
271
272 /* Free TX skb ringbuffer.
273 * SKBs are freed by ravb_tx_free() call above.
274 */
275 kfree(priv->tx_skb[q]);
276 priv->tx_skb[q] = NULL;
277 }
278
279 /* Format skb and descriptor buffer for Ethernet AVB */
280 static void ravb_ring_format(struct net_device *ndev, int q)
281 {
282 struct ravb_private *priv = netdev_priv(ndev);
283 struct ravb_ex_rx_desc *rx_desc;
284 struct ravb_tx_desc *tx_desc;
285 struct ravb_desc *desc;
286 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
287 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
288 NUM_TX_DESC;
289 dma_addr_t dma_addr;
290 int i;
291
292 priv->cur_rx[q] = 0;
293 priv->cur_tx[q] = 0;
294 priv->dirty_rx[q] = 0;
295 priv->dirty_tx[q] = 0;
296
297 memset(priv->rx_ring[q], 0, rx_ring_size);
298 /* Build RX ring buffer */
299 for (i = 0; i < priv->num_rx_ring[q]; i++) {
300 /* RX descriptor */
301 rx_desc = &priv->rx_ring[q][i];
302 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
303 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
304 PKT_BUF_SZ,
305 DMA_FROM_DEVICE);
306 /* We just set the data size to 0 for a failed mapping which
307 * should prevent DMA from happening...
308 */
309 if (dma_mapping_error(ndev->dev.parent, dma_addr))
310 rx_desc->ds_cc = cpu_to_le16(0);
311 rx_desc->dptr = cpu_to_le32(dma_addr);
312 rx_desc->die_dt = DT_FEMPTY;
313 }
314 rx_desc = &priv->rx_ring[q][i];
315 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
316 rx_desc->die_dt = DT_LINKFIX; /* type */
317
318 memset(priv->tx_ring[q], 0, tx_ring_size);
319 /* Build TX ring buffer */
320 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
321 i++, tx_desc++) {
322 tx_desc->die_dt = DT_EEMPTY;
323 tx_desc++;
324 tx_desc->die_dt = DT_EEMPTY;
325 }
326 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
327 tx_desc->die_dt = DT_LINKFIX; /* type */
328
329 /* RX descriptor base address for best effort */
330 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
331 desc->die_dt = DT_LINKFIX; /* type */
332 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
333
334 /* TX descriptor base address for best effort */
335 desc = &priv->desc_bat[q];
336 desc->die_dt = DT_LINKFIX; /* type */
337 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
338 }
339
340 /* Init skb and descriptor buffer for Ethernet AVB */
341 static int ravb_ring_init(struct net_device *ndev, int q)
342 {
343 struct ravb_private *priv = netdev_priv(ndev);
344 struct sk_buff *skb;
345 int ring_size;
346 int i;
347
348 /* Allocate RX and TX skb rings */
349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
350 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
352 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
353 if (!priv->rx_skb[q] || !priv->tx_skb[q])
354 goto error;
355
356 for (i = 0; i < priv->num_rx_ring[q]; i++) {
357 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
358 if (!skb)
359 goto error;
360 ravb_set_buffer_align(skb);
361 priv->rx_skb[q][i] = skb;
362 }
363
364 /* Allocate rings for the aligned buffers */
365 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
366 DPTR_ALIGN - 1, GFP_KERNEL);
367 if (!priv->tx_align[q])
368 goto error;
369
370 /* Allocate all RX descriptors. */
371 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
372 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
373 &priv->rx_desc_dma[q],
374 GFP_KERNEL);
375 if (!priv->rx_ring[q])
376 goto error;
377
378 priv->dirty_rx[q] = 0;
379
380 /* Allocate all TX descriptors. */
381 ring_size = sizeof(struct ravb_tx_desc) *
382 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
383 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
384 &priv->tx_desc_dma[q],
385 GFP_KERNEL);
386 if (!priv->tx_ring[q])
387 goto error;
388
389 return 0;
390
391 error:
392 ravb_ring_free(ndev, q);
393
394 return -ENOMEM;
395 }
396
397 /* E-MAC init function */
398 static void ravb_emac_init(struct net_device *ndev)
399 {
400 struct ravb_private *priv = netdev_priv(ndev);
401
402 /* Receive frame limit set register */
403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
404
405 /* PAUSE prohibition */
406 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
407 ECMR_TE | ECMR_RE, ECMR);
408
409 ravb_set_rate(ndev);
410
411 /* Set MAC address */
412 ravb_write(ndev,
413 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
414 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
415 ravb_write(ndev,
416 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
417
418 /* E-MAC status register clear */
419 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
420
421 /* E-MAC interrupt enable register */
422 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
423 }
424
425 /* Device init function for Ethernet AVB */
426 static int ravb_dmac_init(struct net_device *ndev)
427 {
428 struct ravb_private *priv = netdev_priv(ndev);
429 int error;
430
431 /* Set CONFIG mode */
432 error = ravb_config(ndev);
433 if (error)
434 return error;
435
436 error = ravb_ring_init(ndev, RAVB_BE);
437 if (error)
438 return error;
439 error = ravb_ring_init(ndev, RAVB_NC);
440 if (error) {
441 ravb_ring_free(ndev, RAVB_BE);
442 return error;
443 }
444
445 /* Descriptor format */
446 ravb_ring_format(ndev, RAVB_BE);
447 ravb_ring_format(ndev, RAVB_NC);
448
449 #if defined(__LITTLE_ENDIAN)
450 ravb_modify(ndev, CCC, CCC_BOC, 0);
451 #else
452 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
453 #endif
454
455 /* Set AVB RX */
456 ravb_write(ndev,
457 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
458
459 /* Set FIFO size */
460 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
461
462 /* Timestamp enable */
463 ravb_write(ndev, TCCR_TFEN, TCCR);
464
465 /* Interrupt init: */
466 if (priv->chip_id == RCAR_GEN3) {
467 /* Clear DIL.DPLx */
468 ravb_write(ndev, 0, DIL);
469 /* Set queue specific interrupt */
470 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
471 }
472 /* Frame receive */
473 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
474 /* Disable FIFO full warning */
475 ravb_write(ndev, 0, RIC1);
476 /* Receive FIFO full error, descriptor empty */
477 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
478 /* Frame transmitted, timestamp FIFO updated */
479 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
480
481 /* Setting the control will start the AVB-DMAC process. */
482 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
483
484 return 0;
485 }
486
487 static void ravb_get_tx_tstamp(struct net_device *ndev)
488 {
489 struct ravb_private *priv = netdev_priv(ndev);
490 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
491 struct skb_shared_hwtstamps shhwtstamps;
492 struct sk_buff *skb;
493 struct timespec64 ts;
494 u16 tag, tfa_tag;
495 int count;
496 u32 tfa2;
497
498 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
499 while (count--) {
500 tfa2 = ravb_read(ndev, TFA2);
501 tfa_tag = (tfa2 & TFA2_TST) >> 16;
502 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
503 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
504 ravb_read(ndev, TFA1);
505 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
506 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
507 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
508 list) {
509 skb = ts_skb->skb;
510 tag = ts_skb->tag;
511 list_del(&ts_skb->list);
512 kfree(ts_skb);
513 if (tag == tfa_tag) {
514 skb_tstamp_tx(skb, &shhwtstamps);
515 break;
516 }
517 }
518 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
519 }
520 }
521
522 /* Packet receive function for Ethernet AVB */
523 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
524 {
525 struct ravb_private *priv = netdev_priv(ndev);
526 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
527 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
528 priv->cur_rx[q];
529 struct net_device_stats *stats = &priv->stats[q];
530 struct ravb_ex_rx_desc *desc;
531 struct sk_buff *skb;
532 dma_addr_t dma_addr;
533 struct timespec64 ts;
534 u8 desc_status;
535 u16 pkt_len;
536 int limit;
537
538 boguscnt = min(boguscnt, *quota);
539 limit = boguscnt;
540 desc = &priv->rx_ring[q][entry];
541 while (desc->die_dt != DT_FEMPTY) {
542 /* Descriptor type must be checked before all other reads */
543 dma_rmb();
544 desc_status = desc->msc;
545 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
546
547 if (--boguscnt < 0)
548 break;
549
550 /* We use 0-byte descriptors to mark the DMA mapping errors */
551 if (!pkt_len)
552 continue;
553
554 if (desc_status & MSC_MC)
555 stats->multicast++;
556
557 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
558 MSC_CEEF)) {
559 stats->rx_errors++;
560 if (desc_status & MSC_CRC)
561 stats->rx_crc_errors++;
562 if (desc_status & MSC_RFE)
563 stats->rx_frame_errors++;
564 if (desc_status & (MSC_RTLF | MSC_RTSF))
565 stats->rx_length_errors++;
566 if (desc_status & MSC_CEEF)
567 stats->rx_missed_errors++;
568 } else {
569 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
570
571 skb = priv->rx_skb[q][entry];
572 priv->rx_skb[q][entry] = NULL;
573 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
574 PKT_BUF_SZ,
575 DMA_FROM_DEVICE);
576 get_ts &= (q == RAVB_NC) ?
577 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
578 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
579 if (get_ts) {
580 struct skb_shared_hwtstamps *shhwtstamps;
581
582 shhwtstamps = skb_hwtstamps(skb);
583 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
584 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
585 32) | le32_to_cpu(desc->ts_sl);
586 ts.tv_nsec = le32_to_cpu(desc->ts_n);
587 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
588 }
589 skb_put(skb, pkt_len);
590 skb->protocol = eth_type_trans(skb, ndev);
591 napi_gro_receive(&priv->napi[q], skb);
592 stats->rx_packets++;
593 stats->rx_bytes += pkt_len;
594 }
595
596 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
597 desc = &priv->rx_ring[q][entry];
598 }
599
600 /* Refill the RX ring buffers. */
601 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
602 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
603 desc = &priv->rx_ring[q][entry];
604 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
605
606 if (!priv->rx_skb[q][entry]) {
607 skb = netdev_alloc_skb(ndev,
608 PKT_BUF_SZ + RAVB_ALIGN - 1);
609 if (!skb)
610 break; /* Better luck next round. */
611 ravb_set_buffer_align(skb);
612 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
613 le16_to_cpu(desc->ds_cc),
614 DMA_FROM_DEVICE);
615 skb_checksum_none_assert(skb);
616 /* We just set the data size to 0 for a failed mapping
617 * which should prevent DMA from happening...
618 */
619 if (dma_mapping_error(ndev->dev.parent, dma_addr))
620 desc->ds_cc = cpu_to_le16(0);
621 desc->dptr = cpu_to_le32(dma_addr);
622 priv->rx_skb[q][entry] = skb;
623 }
624 /* Descriptor type must be set after all the above writes */
625 dma_wmb();
626 desc->die_dt = DT_FEMPTY;
627 }
628
629 *quota -= limit - (++boguscnt);
630
631 return boguscnt <= 0;
632 }
633
634 static void ravb_rcv_snd_disable(struct net_device *ndev)
635 {
636 /* Disable TX and RX */
637 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
638 }
639
640 static void ravb_rcv_snd_enable(struct net_device *ndev)
641 {
642 /* Enable TX and RX */
643 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
644 }
645
646 /* function for waiting dma process finished */
647 static int ravb_stop_dma(struct net_device *ndev)
648 {
649 int error;
650
651 /* Wait for stopping the hardware TX process */
652 error = ravb_wait(ndev, TCCR,
653 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
654 if (error)
655 return error;
656
657 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
658 0);
659 if (error)
660 return error;
661
662 /* Stop the E-MAC's RX/TX processes. */
663 ravb_rcv_snd_disable(ndev);
664
665 /* Wait for stopping the RX DMA process */
666 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
667 if (error)
668 return error;
669
670 /* Stop AVB-DMAC process */
671 return ravb_config(ndev);
672 }
673
674 /* E-MAC interrupt handler */
675 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
676 {
677 struct ravb_private *priv = netdev_priv(ndev);
678 u32 ecsr, psr;
679
680 ecsr = ravb_read(ndev, ECSR);
681 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
682 if (ecsr & ECSR_ICD)
683 ndev->stats.tx_carrier_errors++;
684 if (ecsr & ECSR_LCHNG) {
685 /* Link changed */
686 if (priv->no_avb_link)
687 return;
688 psr = ravb_read(ndev, PSR);
689 if (priv->avb_link_active_low)
690 psr ^= PSR_LMON;
691 if (!(psr & PSR_LMON)) {
692 /* DIsable RX and TX */
693 ravb_rcv_snd_disable(ndev);
694 } else {
695 /* Enable RX and TX */
696 ravb_rcv_snd_enable(ndev);
697 }
698 }
699 }
700
701 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
702 {
703 struct net_device *ndev = dev_id;
704 struct ravb_private *priv = netdev_priv(ndev);
705
706 spin_lock(&priv->lock);
707 ravb_emac_interrupt_unlocked(ndev);
708 mmiowb();
709 spin_unlock(&priv->lock);
710 return IRQ_HANDLED;
711 }
712
713 /* Error interrupt handler */
714 static void ravb_error_interrupt(struct net_device *ndev)
715 {
716 struct ravb_private *priv = netdev_priv(ndev);
717 u32 eis, ris2;
718
719 eis = ravb_read(ndev, EIS);
720 ravb_write(ndev, ~EIS_QFS, EIS);
721 if (eis & EIS_QFS) {
722 ris2 = ravb_read(ndev, RIS2);
723 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
724
725 /* Receive Descriptor Empty int */
726 if (ris2 & RIS2_QFF0)
727 priv->stats[RAVB_BE].rx_over_errors++;
728
729 /* Receive Descriptor Empty int */
730 if (ris2 & RIS2_QFF1)
731 priv->stats[RAVB_NC].rx_over_errors++;
732
733 /* Receive FIFO Overflow int */
734 if (ris2 & RIS2_RFFF)
735 priv->rx_fifo_errors++;
736 }
737 }
738
739 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
740 {
741 struct ravb_private *priv = netdev_priv(ndev);
742 u32 ris0 = ravb_read(ndev, RIS0);
743 u32 ric0 = ravb_read(ndev, RIC0);
744 u32 tis = ravb_read(ndev, TIS);
745 u32 tic = ravb_read(ndev, TIC);
746
747 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
748 if (napi_schedule_prep(&priv->napi[q])) {
749 /* Mask RX and TX interrupts */
750 if (priv->chip_id == RCAR_GEN2) {
751 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
752 ravb_write(ndev, tic & ~BIT(q), TIC);
753 } else {
754 ravb_write(ndev, BIT(q), RID0);
755 ravb_write(ndev, BIT(q), TID);
756 }
757 __napi_schedule(&priv->napi[q]);
758 } else {
759 netdev_warn(ndev,
760 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
761 ris0, ric0);
762 netdev_warn(ndev,
763 " tx status 0x%08x, tx mask 0x%08x.\n",
764 tis, tic);
765 }
766 return true;
767 }
768 return false;
769 }
770
771 static bool ravb_timestamp_interrupt(struct net_device *ndev)
772 {
773 u32 tis = ravb_read(ndev, TIS);
774
775 if (tis & TIS_TFUF) {
776 ravb_write(ndev, ~TIS_TFUF, TIS);
777 ravb_get_tx_tstamp(ndev);
778 return true;
779 }
780 return false;
781 }
782
783 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
784 {
785 struct net_device *ndev = dev_id;
786 struct ravb_private *priv = netdev_priv(ndev);
787 irqreturn_t result = IRQ_NONE;
788 u32 iss;
789
790 spin_lock(&priv->lock);
791 /* Get interrupt status */
792 iss = ravb_read(ndev, ISS);
793
794 /* Received and transmitted interrupts */
795 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
796 int q;
797
798 /* Timestamp updated */
799 if (ravb_timestamp_interrupt(ndev))
800 result = IRQ_HANDLED;
801
802 /* Network control and best effort queue RX/TX */
803 for (q = RAVB_NC; q >= RAVB_BE; q--) {
804 if (ravb_queue_interrupt(ndev, q))
805 result = IRQ_HANDLED;
806 }
807 }
808
809 /* E-MAC status summary */
810 if (iss & ISS_MS) {
811 ravb_emac_interrupt_unlocked(ndev);
812 result = IRQ_HANDLED;
813 }
814
815 /* Error status summary */
816 if (iss & ISS_ES) {
817 ravb_error_interrupt(ndev);
818 result = IRQ_HANDLED;
819 }
820
821 /* gPTP interrupt status summary */
822 if (iss & ISS_CGIS) {
823 ravb_ptp_interrupt(ndev);
824 result = IRQ_HANDLED;
825 }
826
827 mmiowb();
828 spin_unlock(&priv->lock);
829 return result;
830 }
831
832 /* Timestamp/Error/gPTP interrupt handler */
833 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
834 {
835 struct net_device *ndev = dev_id;
836 struct ravb_private *priv = netdev_priv(ndev);
837 irqreturn_t result = IRQ_NONE;
838 u32 iss;
839
840 spin_lock(&priv->lock);
841 /* Get interrupt status */
842 iss = ravb_read(ndev, ISS);
843
844 /* Timestamp updated */
845 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
846 result = IRQ_HANDLED;
847
848 /* Error status summary */
849 if (iss & ISS_ES) {
850 ravb_error_interrupt(ndev);
851 result = IRQ_HANDLED;
852 }
853
854 /* gPTP interrupt status summary */
855 if (iss & ISS_CGIS) {
856 ravb_ptp_interrupt(ndev);
857 result = IRQ_HANDLED;
858 }
859
860 mmiowb();
861 spin_unlock(&priv->lock);
862 return result;
863 }
864
865 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
866 {
867 struct net_device *ndev = dev_id;
868 struct ravb_private *priv = netdev_priv(ndev);
869 irqreturn_t result = IRQ_NONE;
870
871 spin_lock(&priv->lock);
872
873 /* Network control/Best effort queue RX/TX */
874 if (ravb_queue_interrupt(ndev, q))
875 result = IRQ_HANDLED;
876
877 mmiowb();
878 spin_unlock(&priv->lock);
879 return result;
880 }
881
882 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
883 {
884 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
885 }
886
887 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
888 {
889 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
890 }
891
892 static int ravb_poll(struct napi_struct *napi, int budget)
893 {
894 struct net_device *ndev = napi->dev;
895 struct ravb_private *priv = netdev_priv(ndev);
896 unsigned long flags;
897 int q = napi - priv->napi;
898 int mask = BIT(q);
899 int quota = budget;
900 u32 ris0, tis;
901
902 for (;;) {
903 tis = ravb_read(ndev, TIS);
904 ris0 = ravb_read(ndev, RIS0);
905 if (!((ris0 & mask) || (tis & mask)))
906 break;
907
908 /* Processing RX Descriptor Ring */
909 if (ris0 & mask) {
910 /* Clear RX interrupt */
911 ravb_write(ndev, ~mask, RIS0);
912 if (ravb_rx(ndev, &quota, q))
913 goto out;
914 }
915 /* Processing TX Descriptor Ring */
916 if (tis & mask) {
917 spin_lock_irqsave(&priv->lock, flags);
918 /* Clear TX interrupt */
919 ravb_write(ndev, ~mask, TIS);
920 ravb_tx_free(ndev, q, true);
921 netif_wake_subqueue(ndev, q);
922 mmiowb();
923 spin_unlock_irqrestore(&priv->lock, flags);
924 }
925 }
926
927 napi_complete(napi);
928
929 /* Re-enable RX/TX interrupts */
930 spin_lock_irqsave(&priv->lock, flags);
931 if (priv->chip_id == RCAR_GEN2) {
932 ravb_modify(ndev, RIC0, mask, mask);
933 ravb_modify(ndev, TIC, mask, mask);
934 } else {
935 ravb_write(ndev, mask, RIE0);
936 ravb_write(ndev, mask, TIE);
937 }
938 mmiowb();
939 spin_unlock_irqrestore(&priv->lock, flags);
940
941 /* Receive error message handling */
942 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
943 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
944 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
945 ndev->stats.rx_over_errors = priv->rx_over_errors;
946 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
947 }
948 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
949 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
950 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
951 }
952 out:
953 return budget - quota;
954 }
955
956 /* PHY state control function */
957 static void ravb_adjust_link(struct net_device *ndev)
958 {
959 struct ravb_private *priv = netdev_priv(ndev);
960 struct phy_device *phydev = ndev->phydev;
961 bool new_state = false;
962
963 if (phydev->link) {
964 if (phydev->duplex != priv->duplex) {
965 new_state = true;
966 priv->duplex = phydev->duplex;
967 ravb_set_duplex(ndev);
968 }
969
970 if (phydev->speed != priv->speed) {
971 new_state = true;
972 priv->speed = phydev->speed;
973 ravb_set_rate(ndev);
974 }
975 if (!priv->link) {
976 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
977 new_state = true;
978 priv->link = phydev->link;
979 if (priv->no_avb_link)
980 ravb_rcv_snd_enable(ndev);
981 }
982 } else if (priv->link) {
983 new_state = true;
984 priv->link = 0;
985 priv->speed = 0;
986 priv->duplex = -1;
987 if (priv->no_avb_link)
988 ravb_rcv_snd_disable(ndev);
989 }
990
991 if (new_state && netif_msg_link(priv))
992 phy_print_status(phydev);
993 }
994
995 /* PHY init function */
996 static int ravb_phy_init(struct net_device *ndev)
997 {
998 struct device_node *np = ndev->dev.parent->of_node;
999 struct ravb_private *priv = netdev_priv(ndev);
1000 struct phy_device *phydev;
1001 struct device_node *pn;
1002 int err;
1003
1004 priv->link = 0;
1005 priv->speed = 0;
1006 priv->duplex = -1;
1007
1008 /* Try connecting to PHY */
1009 pn = of_parse_phandle(np, "phy-handle", 0);
1010 if (!pn) {
1011 /* In the case of a fixed PHY, the DT node associated
1012 * to the PHY is the Ethernet MAC DT node.
1013 */
1014 if (of_phy_is_fixed_link(np)) {
1015 err = of_phy_register_fixed_link(np);
1016 if (err)
1017 return err;
1018 }
1019 pn = of_node_get(np);
1020 }
1021 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1022 priv->phy_interface);
1023 of_node_put(pn);
1024 if (!phydev) {
1025 netdev_err(ndev, "failed to connect PHY\n");
1026 err = -ENOENT;
1027 goto err_deregister_fixed_link;
1028 }
1029
1030 /* This driver only support 10/100Mbit speeds on Gen3
1031 * at this time.
1032 */
1033 if (priv->chip_id == RCAR_GEN3) {
1034 err = phy_set_max_speed(phydev, SPEED_100);
1035 if (err) {
1036 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1037 goto err_phy_disconnect;
1038 }
1039
1040 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1041 }
1042
1043 /* 10BASE is not supported */
1044 phydev->supported &= ~PHY_10BT_FEATURES;
1045
1046 phy_attached_info(phydev);
1047
1048 return 0;
1049
1050 err_phy_disconnect:
1051 phy_disconnect(phydev);
1052 err_deregister_fixed_link:
1053 if (of_phy_is_fixed_link(np))
1054 of_phy_deregister_fixed_link(np);
1055
1056 return err;
1057 }
1058
1059 /* PHY control start function */
1060 static int ravb_phy_start(struct net_device *ndev)
1061 {
1062 int error;
1063
1064 error = ravb_phy_init(ndev);
1065 if (error)
1066 return error;
1067
1068 phy_start(ndev->phydev);
1069
1070 return 0;
1071 }
1072
1073 static int ravb_get_link_ksettings(struct net_device *ndev,
1074 struct ethtool_link_ksettings *cmd)
1075 {
1076 struct ravb_private *priv = netdev_priv(ndev);
1077 int error = -ENODEV;
1078 unsigned long flags;
1079
1080 if (ndev->phydev) {
1081 spin_lock_irqsave(&priv->lock, flags);
1082 error = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1083 spin_unlock_irqrestore(&priv->lock, flags);
1084 }
1085
1086 return error;
1087 }
1088
1089 static int ravb_set_link_ksettings(struct net_device *ndev,
1090 const struct ethtool_link_ksettings *cmd)
1091 {
1092 struct ravb_private *priv = netdev_priv(ndev);
1093 unsigned long flags;
1094 int error;
1095
1096 if (!ndev->phydev)
1097 return -ENODEV;
1098
1099 spin_lock_irqsave(&priv->lock, flags);
1100
1101 /* Disable TX and RX */
1102 ravb_rcv_snd_disable(ndev);
1103
1104 error = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1105 if (error)
1106 goto error_exit;
1107
1108 if (cmd->base.duplex == DUPLEX_FULL)
1109 priv->duplex = 1;
1110 else
1111 priv->duplex = 0;
1112
1113 ravb_set_duplex(ndev);
1114
1115 error_exit:
1116 mdelay(1);
1117
1118 /* Enable TX and RX */
1119 ravb_rcv_snd_enable(ndev);
1120
1121 mmiowb();
1122 spin_unlock_irqrestore(&priv->lock, flags);
1123
1124 return error;
1125 }
1126
1127 static int ravb_nway_reset(struct net_device *ndev)
1128 {
1129 struct ravb_private *priv = netdev_priv(ndev);
1130 int error = -ENODEV;
1131 unsigned long flags;
1132
1133 if (ndev->phydev) {
1134 spin_lock_irqsave(&priv->lock, flags);
1135 error = phy_start_aneg(ndev->phydev);
1136 spin_unlock_irqrestore(&priv->lock, flags);
1137 }
1138
1139 return error;
1140 }
1141
1142 static u32 ravb_get_msglevel(struct net_device *ndev)
1143 {
1144 struct ravb_private *priv = netdev_priv(ndev);
1145
1146 return priv->msg_enable;
1147 }
1148
1149 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1150 {
1151 struct ravb_private *priv = netdev_priv(ndev);
1152
1153 priv->msg_enable = value;
1154 }
1155
1156 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1157 "rx_queue_0_current",
1158 "tx_queue_0_current",
1159 "rx_queue_0_dirty",
1160 "tx_queue_0_dirty",
1161 "rx_queue_0_packets",
1162 "tx_queue_0_packets",
1163 "rx_queue_0_bytes",
1164 "tx_queue_0_bytes",
1165 "rx_queue_0_mcast_packets",
1166 "rx_queue_0_errors",
1167 "rx_queue_0_crc_errors",
1168 "rx_queue_0_frame_errors",
1169 "rx_queue_0_length_errors",
1170 "rx_queue_0_missed_errors",
1171 "rx_queue_0_over_errors",
1172
1173 "rx_queue_1_current",
1174 "tx_queue_1_current",
1175 "rx_queue_1_dirty",
1176 "tx_queue_1_dirty",
1177 "rx_queue_1_packets",
1178 "tx_queue_1_packets",
1179 "rx_queue_1_bytes",
1180 "tx_queue_1_bytes",
1181 "rx_queue_1_mcast_packets",
1182 "rx_queue_1_errors",
1183 "rx_queue_1_crc_errors",
1184 "rx_queue_1_frame_errors",
1185 "rx_queue_1_length_errors",
1186 "rx_queue_1_missed_errors",
1187 "rx_queue_1_over_errors",
1188 };
1189
1190 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1191
1192 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1193 {
1194 switch (sset) {
1195 case ETH_SS_STATS:
1196 return RAVB_STATS_LEN;
1197 default:
1198 return -EOPNOTSUPP;
1199 }
1200 }
1201
1202 static void ravb_get_ethtool_stats(struct net_device *ndev,
1203 struct ethtool_stats *stats, u64 *data)
1204 {
1205 struct ravb_private *priv = netdev_priv(ndev);
1206 int i = 0;
1207 int q;
1208
1209 /* Device-specific stats */
1210 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1211 struct net_device_stats *stats = &priv->stats[q];
1212
1213 data[i++] = priv->cur_rx[q];
1214 data[i++] = priv->cur_tx[q];
1215 data[i++] = priv->dirty_rx[q];
1216 data[i++] = priv->dirty_tx[q];
1217 data[i++] = stats->rx_packets;
1218 data[i++] = stats->tx_packets;
1219 data[i++] = stats->rx_bytes;
1220 data[i++] = stats->tx_bytes;
1221 data[i++] = stats->multicast;
1222 data[i++] = stats->rx_errors;
1223 data[i++] = stats->rx_crc_errors;
1224 data[i++] = stats->rx_frame_errors;
1225 data[i++] = stats->rx_length_errors;
1226 data[i++] = stats->rx_missed_errors;
1227 data[i++] = stats->rx_over_errors;
1228 }
1229 }
1230
1231 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1232 {
1233 switch (stringset) {
1234 case ETH_SS_STATS:
1235 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1236 break;
1237 }
1238 }
1239
1240 static void ravb_get_ringparam(struct net_device *ndev,
1241 struct ethtool_ringparam *ring)
1242 {
1243 struct ravb_private *priv = netdev_priv(ndev);
1244
1245 ring->rx_max_pending = BE_RX_RING_MAX;
1246 ring->tx_max_pending = BE_TX_RING_MAX;
1247 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1248 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1249 }
1250
1251 static int ravb_set_ringparam(struct net_device *ndev,
1252 struct ethtool_ringparam *ring)
1253 {
1254 struct ravb_private *priv = netdev_priv(ndev);
1255 int error;
1256
1257 if (ring->tx_pending > BE_TX_RING_MAX ||
1258 ring->rx_pending > BE_RX_RING_MAX ||
1259 ring->tx_pending < BE_TX_RING_MIN ||
1260 ring->rx_pending < BE_RX_RING_MIN)
1261 return -EINVAL;
1262 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1263 return -EINVAL;
1264
1265 if (netif_running(ndev)) {
1266 netif_device_detach(ndev);
1267 /* Stop PTP Clock driver */
1268 if (priv->chip_id == RCAR_GEN2)
1269 ravb_ptp_stop(ndev);
1270 /* Wait for DMA stopping */
1271 error = ravb_stop_dma(ndev);
1272 if (error) {
1273 netdev_err(ndev,
1274 "cannot set ringparam! Any AVB processes are still running?\n");
1275 return error;
1276 }
1277 synchronize_irq(ndev->irq);
1278
1279 /* Free all the skb's in the RX queue and the DMA buffers. */
1280 ravb_ring_free(ndev, RAVB_BE);
1281 ravb_ring_free(ndev, RAVB_NC);
1282 }
1283
1284 /* Set new parameters */
1285 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1286 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1287
1288 if (netif_running(ndev)) {
1289 error = ravb_dmac_init(ndev);
1290 if (error) {
1291 netdev_err(ndev,
1292 "%s: ravb_dmac_init() failed, error %d\n",
1293 __func__, error);
1294 return error;
1295 }
1296
1297 ravb_emac_init(ndev);
1298
1299 /* Initialise PTP Clock driver */
1300 if (priv->chip_id == RCAR_GEN2)
1301 ravb_ptp_init(ndev, priv->pdev);
1302
1303 netif_device_attach(ndev);
1304 }
1305
1306 return 0;
1307 }
1308
1309 static int ravb_get_ts_info(struct net_device *ndev,
1310 struct ethtool_ts_info *info)
1311 {
1312 struct ravb_private *priv = netdev_priv(ndev);
1313
1314 info->so_timestamping =
1315 SOF_TIMESTAMPING_TX_SOFTWARE |
1316 SOF_TIMESTAMPING_RX_SOFTWARE |
1317 SOF_TIMESTAMPING_SOFTWARE |
1318 SOF_TIMESTAMPING_TX_HARDWARE |
1319 SOF_TIMESTAMPING_RX_HARDWARE |
1320 SOF_TIMESTAMPING_RAW_HARDWARE;
1321 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1322 info->rx_filters =
1323 (1 << HWTSTAMP_FILTER_NONE) |
1324 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1325 (1 << HWTSTAMP_FILTER_ALL);
1326 info->phc_index = ptp_clock_index(priv->ptp.clock);
1327
1328 return 0;
1329 }
1330
1331 static const struct ethtool_ops ravb_ethtool_ops = {
1332 .nway_reset = ravb_nway_reset,
1333 .get_msglevel = ravb_get_msglevel,
1334 .set_msglevel = ravb_set_msglevel,
1335 .get_link = ethtool_op_get_link,
1336 .get_strings = ravb_get_strings,
1337 .get_ethtool_stats = ravb_get_ethtool_stats,
1338 .get_sset_count = ravb_get_sset_count,
1339 .get_ringparam = ravb_get_ringparam,
1340 .set_ringparam = ravb_set_ringparam,
1341 .get_ts_info = ravb_get_ts_info,
1342 .get_link_ksettings = ravb_get_link_ksettings,
1343 .set_link_ksettings = ravb_set_link_ksettings,
1344 };
1345
1346 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1347 struct net_device *ndev, struct device *dev,
1348 const char *ch)
1349 {
1350 char *name;
1351 int error;
1352
1353 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1354 if (!name)
1355 return -ENOMEM;
1356 error = request_irq(irq, handler, 0, name, ndev);
1357 if (error)
1358 netdev_err(ndev, "cannot request IRQ %s\n", name);
1359
1360 return error;
1361 }
1362
1363 /* Network device open function for Ethernet AVB */
1364 static int ravb_open(struct net_device *ndev)
1365 {
1366 struct ravb_private *priv = netdev_priv(ndev);
1367 struct platform_device *pdev = priv->pdev;
1368 struct device *dev = &pdev->dev;
1369 int error;
1370
1371 napi_enable(&priv->napi[RAVB_BE]);
1372 napi_enable(&priv->napi[RAVB_NC]);
1373
1374 if (priv->chip_id == RCAR_GEN2) {
1375 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1376 ndev->name, ndev);
1377 if (error) {
1378 netdev_err(ndev, "cannot request IRQ\n");
1379 goto out_napi_off;
1380 }
1381 } else {
1382 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1383 dev, "ch22:multi");
1384 if (error)
1385 goto out_napi_off;
1386 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1387 dev, "ch24:emac");
1388 if (error)
1389 goto out_free_irq;
1390 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1391 ndev, dev, "ch0:rx_be");
1392 if (error)
1393 goto out_free_irq_emac;
1394 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1395 ndev, dev, "ch18:tx_be");
1396 if (error)
1397 goto out_free_irq_be_rx;
1398 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1399 ndev, dev, "ch1:rx_nc");
1400 if (error)
1401 goto out_free_irq_be_tx;
1402 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1403 ndev, dev, "ch19:tx_nc");
1404 if (error)
1405 goto out_free_irq_nc_rx;
1406 }
1407
1408 /* Device init */
1409 error = ravb_dmac_init(ndev);
1410 if (error)
1411 goto out_free_irq_nc_tx;
1412 ravb_emac_init(ndev);
1413
1414 /* Initialise PTP Clock driver */
1415 if (priv->chip_id == RCAR_GEN2)
1416 ravb_ptp_init(ndev, priv->pdev);
1417
1418 netif_tx_start_all_queues(ndev);
1419
1420 /* PHY control start */
1421 error = ravb_phy_start(ndev);
1422 if (error)
1423 goto out_ptp_stop;
1424
1425 return 0;
1426
1427 out_ptp_stop:
1428 /* Stop PTP Clock driver */
1429 if (priv->chip_id == RCAR_GEN2)
1430 ravb_ptp_stop(ndev);
1431 out_free_irq_nc_tx:
1432 if (priv->chip_id == RCAR_GEN2)
1433 goto out_free_irq;
1434 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1435 out_free_irq_nc_rx:
1436 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1437 out_free_irq_be_tx:
1438 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1439 out_free_irq_be_rx:
1440 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1441 out_free_irq_emac:
1442 free_irq(priv->emac_irq, ndev);
1443 out_free_irq:
1444 free_irq(ndev->irq, ndev);
1445 out_napi_off:
1446 napi_disable(&priv->napi[RAVB_NC]);
1447 napi_disable(&priv->napi[RAVB_BE]);
1448 return error;
1449 }
1450
1451 /* Timeout function for Ethernet AVB */
1452 static void ravb_tx_timeout(struct net_device *ndev)
1453 {
1454 struct ravb_private *priv = netdev_priv(ndev);
1455
1456 netif_err(priv, tx_err, ndev,
1457 "transmit timed out, status %08x, resetting...\n",
1458 ravb_read(ndev, ISS));
1459
1460 /* tx_errors count up */
1461 ndev->stats.tx_errors++;
1462
1463 schedule_work(&priv->work);
1464 }
1465
1466 static void ravb_tx_timeout_work(struct work_struct *work)
1467 {
1468 struct ravb_private *priv = container_of(work, struct ravb_private,
1469 work);
1470 struct net_device *ndev = priv->ndev;
1471
1472 netif_tx_stop_all_queues(ndev);
1473
1474 /* Stop PTP Clock driver */
1475 if (priv->chip_id == RCAR_GEN2)
1476 ravb_ptp_stop(ndev);
1477
1478 /* Wait for DMA stopping */
1479 ravb_stop_dma(ndev);
1480
1481 ravb_ring_free(ndev, RAVB_BE);
1482 ravb_ring_free(ndev, RAVB_NC);
1483
1484 /* Device init */
1485 ravb_dmac_init(ndev);
1486 ravb_emac_init(ndev);
1487
1488 /* Initialise PTP Clock driver */
1489 if (priv->chip_id == RCAR_GEN2)
1490 ravb_ptp_init(ndev, priv->pdev);
1491
1492 netif_tx_start_all_queues(ndev);
1493 }
1494
1495 /* Packet transmit function for Ethernet AVB */
1496 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1497 {
1498 struct ravb_private *priv = netdev_priv(ndev);
1499 u16 q = skb_get_queue_mapping(skb);
1500 struct ravb_tstamp_skb *ts_skb;
1501 struct ravb_tx_desc *desc;
1502 unsigned long flags;
1503 u32 dma_addr;
1504 void *buffer;
1505 u32 entry;
1506 u32 len;
1507
1508 spin_lock_irqsave(&priv->lock, flags);
1509 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1510 NUM_TX_DESC) {
1511 netif_err(priv, tx_queued, ndev,
1512 "still transmitting with the full ring!\n");
1513 netif_stop_subqueue(ndev, q);
1514 spin_unlock_irqrestore(&priv->lock, flags);
1515 return NETDEV_TX_BUSY;
1516 }
1517 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1518 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1519
1520 if (skb_put_padto(skb, ETH_ZLEN))
1521 goto drop;
1522
1523 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1524 entry / NUM_TX_DESC * DPTR_ALIGN;
1525 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1526 /* Zero length DMA descriptors are problematic as they seem to
1527 * terminate DMA transfers. Avoid them by simply using a length of
1528 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1529 *
1530 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1531 * data by the call to skb_put_padto() above this is safe with
1532 * respect to both the length of the first DMA descriptor (len)
1533 * overflowing the available data and the length of the second DMA
1534 * descriptor (skb->len - len) being negative.
1535 */
1536 if (len == 0)
1537 len = DPTR_ALIGN;
1538
1539 memcpy(buffer, skb->data, len);
1540 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1541 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1542 goto drop;
1543
1544 desc = &priv->tx_ring[q][entry];
1545 desc->ds_tagl = cpu_to_le16(len);
1546 desc->dptr = cpu_to_le32(dma_addr);
1547
1548 buffer = skb->data + len;
1549 len = skb->len - len;
1550 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1551 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1552 goto unmap;
1553
1554 desc++;
1555 desc->ds_tagl = cpu_to_le16(len);
1556 desc->dptr = cpu_to_le32(dma_addr);
1557
1558 /* TX timestamp required */
1559 if (q == RAVB_NC) {
1560 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1561 if (!ts_skb) {
1562 desc--;
1563 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1564 DMA_TO_DEVICE);
1565 goto unmap;
1566 }
1567 ts_skb->skb = skb;
1568 ts_skb->tag = priv->ts_skb_tag++;
1569 priv->ts_skb_tag &= 0x3ff;
1570 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1571
1572 /* TAG and timestamp required flag */
1573 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1574 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1575 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1576 }
1577
1578 skb_tx_timestamp(skb);
1579 /* Descriptor type must be set after all the above writes */
1580 dma_wmb();
1581 desc->die_dt = DT_FEND;
1582 desc--;
1583 desc->die_dt = DT_FSTART;
1584
1585 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1586
1587 priv->cur_tx[q] += NUM_TX_DESC;
1588 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1589 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1590 !ravb_tx_free(ndev, q, true))
1591 netif_stop_subqueue(ndev, q);
1592
1593 exit:
1594 mmiowb();
1595 spin_unlock_irqrestore(&priv->lock, flags);
1596 return NETDEV_TX_OK;
1597
1598 unmap:
1599 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1600 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1601 drop:
1602 dev_kfree_skb_any(skb);
1603 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1604 goto exit;
1605 }
1606
1607 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1608 void *accel_priv, select_queue_fallback_t fallback)
1609 {
1610 /* If skb needs TX timestamp, it is handled in network control queue */
1611 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1612 RAVB_BE;
1613
1614 }
1615
1616 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1617 {
1618 struct ravb_private *priv = netdev_priv(ndev);
1619 struct net_device_stats *nstats, *stats0, *stats1;
1620
1621 nstats = &ndev->stats;
1622 stats0 = &priv->stats[RAVB_BE];
1623 stats1 = &priv->stats[RAVB_NC];
1624
1625 nstats->tx_dropped += ravb_read(ndev, TROCR);
1626 ravb_write(ndev, 0, TROCR); /* (write clear) */
1627 nstats->collisions += ravb_read(ndev, CDCR);
1628 ravb_write(ndev, 0, CDCR); /* (write clear) */
1629 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1630 ravb_write(ndev, 0, LCCR); /* (write clear) */
1631
1632 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1633 ravb_write(ndev, 0, CERCR); /* (write clear) */
1634 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1635 ravb_write(ndev, 0, CEECR); /* (write clear) */
1636
1637 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1638 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1639 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1640 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1641 nstats->multicast = stats0->multicast + stats1->multicast;
1642 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1643 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1644 nstats->rx_frame_errors =
1645 stats0->rx_frame_errors + stats1->rx_frame_errors;
1646 nstats->rx_length_errors =
1647 stats0->rx_length_errors + stats1->rx_length_errors;
1648 nstats->rx_missed_errors =
1649 stats0->rx_missed_errors + stats1->rx_missed_errors;
1650 nstats->rx_over_errors =
1651 stats0->rx_over_errors + stats1->rx_over_errors;
1652
1653 return nstats;
1654 }
1655
1656 /* Update promiscuous bit */
1657 static void ravb_set_rx_mode(struct net_device *ndev)
1658 {
1659 struct ravb_private *priv = netdev_priv(ndev);
1660 unsigned long flags;
1661
1662 spin_lock_irqsave(&priv->lock, flags);
1663 ravb_modify(ndev, ECMR, ECMR_PRM,
1664 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1665 mmiowb();
1666 spin_unlock_irqrestore(&priv->lock, flags);
1667 }
1668
1669 /* Device close function for Ethernet AVB */
1670 static int ravb_close(struct net_device *ndev)
1671 {
1672 struct device_node *np = ndev->dev.parent->of_node;
1673 struct ravb_private *priv = netdev_priv(ndev);
1674 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1675
1676 netif_tx_stop_all_queues(ndev);
1677
1678 /* Disable interrupts by clearing the interrupt masks. */
1679 ravb_write(ndev, 0, RIC0);
1680 ravb_write(ndev, 0, RIC2);
1681 ravb_write(ndev, 0, TIC);
1682
1683 /* Stop PTP Clock driver */
1684 if (priv->chip_id == RCAR_GEN2)
1685 ravb_ptp_stop(ndev);
1686
1687 /* Set the config mode to stop the AVB-DMAC's processes */
1688 if (ravb_stop_dma(ndev) < 0)
1689 netdev_err(ndev,
1690 "device will be stopped after h/w processes are done.\n");
1691
1692 /* Clear the timestamp list */
1693 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1694 list_del(&ts_skb->list);
1695 kfree(ts_skb);
1696 }
1697
1698 /* PHY disconnect */
1699 if (ndev->phydev) {
1700 phy_stop(ndev->phydev);
1701 phy_disconnect(ndev->phydev);
1702 if (of_phy_is_fixed_link(np))
1703 of_phy_deregister_fixed_link(np);
1704 }
1705
1706 if (priv->chip_id != RCAR_GEN2) {
1707 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1708 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1709 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1710 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1711 free_irq(priv->emac_irq, ndev);
1712 }
1713 free_irq(ndev->irq, ndev);
1714
1715 napi_disable(&priv->napi[RAVB_NC]);
1716 napi_disable(&priv->napi[RAVB_BE]);
1717
1718 /* Free all the skb's in the RX queue and the DMA buffers. */
1719 ravb_ring_free(ndev, RAVB_BE);
1720 ravb_ring_free(ndev, RAVB_NC);
1721
1722 return 0;
1723 }
1724
1725 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1726 {
1727 struct ravb_private *priv = netdev_priv(ndev);
1728 struct hwtstamp_config config;
1729
1730 config.flags = 0;
1731 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1732 HWTSTAMP_TX_OFF;
1733 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1734 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1735 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1736 config.rx_filter = HWTSTAMP_FILTER_ALL;
1737 else
1738 config.rx_filter = HWTSTAMP_FILTER_NONE;
1739
1740 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1741 -EFAULT : 0;
1742 }
1743
1744 /* Control hardware time stamping */
1745 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1746 {
1747 struct ravb_private *priv = netdev_priv(ndev);
1748 struct hwtstamp_config config;
1749 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1750 u32 tstamp_tx_ctrl;
1751
1752 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1753 return -EFAULT;
1754
1755 /* Reserved for future extensions */
1756 if (config.flags)
1757 return -EINVAL;
1758
1759 switch (config.tx_type) {
1760 case HWTSTAMP_TX_OFF:
1761 tstamp_tx_ctrl = 0;
1762 break;
1763 case HWTSTAMP_TX_ON:
1764 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1765 break;
1766 default:
1767 return -ERANGE;
1768 }
1769
1770 switch (config.rx_filter) {
1771 case HWTSTAMP_FILTER_NONE:
1772 tstamp_rx_ctrl = 0;
1773 break;
1774 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1775 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1776 break;
1777 default:
1778 config.rx_filter = HWTSTAMP_FILTER_ALL;
1779 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1780 }
1781
1782 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1783 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1784
1785 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1786 -EFAULT : 0;
1787 }
1788
1789 /* ioctl to device function */
1790 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1791 {
1792 struct phy_device *phydev = ndev->phydev;
1793
1794 if (!netif_running(ndev))
1795 return -EINVAL;
1796
1797 if (!phydev)
1798 return -ENODEV;
1799
1800 switch (cmd) {
1801 case SIOCGHWTSTAMP:
1802 return ravb_hwtstamp_get(ndev, req);
1803 case SIOCSHWTSTAMP:
1804 return ravb_hwtstamp_set(ndev, req);
1805 }
1806
1807 return phy_mii_ioctl(phydev, req, cmd);
1808 }
1809
1810 static const struct net_device_ops ravb_netdev_ops = {
1811 .ndo_open = ravb_open,
1812 .ndo_stop = ravb_close,
1813 .ndo_start_xmit = ravb_start_xmit,
1814 .ndo_select_queue = ravb_select_queue,
1815 .ndo_get_stats = ravb_get_stats,
1816 .ndo_set_rx_mode = ravb_set_rx_mode,
1817 .ndo_tx_timeout = ravb_tx_timeout,
1818 .ndo_do_ioctl = ravb_do_ioctl,
1819 .ndo_validate_addr = eth_validate_addr,
1820 .ndo_set_mac_address = eth_mac_addr,
1821 .ndo_change_mtu = eth_change_mtu,
1822 };
1823
1824 /* MDIO bus init function */
1825 static int ravb_mdio_init(struct ravb_private *priv)
1826 {
1827 struct platform_device *pdev = priv->pdev;
1828 struct device *dev = &pdev->dev;
1829 int error;
1830
1831 /* Bitbang init */
1832 priv->mdiobb.ops = &bb_ops;
1833
1834 /* MII controller setting */
1835 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1836 if (!priv->mii_bus)
1837 return -ENOMEM;
1838
1839 /* Hook up MII support for ethtool */
1840 priv->mii_bus->name = "ravb_mii";
1841 priv->mii_bus->parent = dev;
1842 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1843 pdev->name, pdev->id);
1844
1845 /* Register MDIO bus */
1846 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1847 if (error)
1848 goto out_free_bus;
1849
1850 return 0;
1851
1852 out_free_bus:
1853 free_mdio_bitbang(priv->mii_bus);
1854 return error;
1855 }
1856
1857 /* MDIO bus release function */
1858 static int ravb_mdio_release(struct ravb_private *priv)
1859 {
1860 /* Unregister mdio bus */
1861 mdiobus_unregister(priv->mii_bus);
1862
1863 /* Free bitbang info */
1864 free_mdio_bitbang(priv->mii_bus);
1865
1866 return 0;
1867 }
1868
1869 static const struct of_device_id ravb_match_table[] = {
1870 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1871 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1872 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1873 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1874 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1875 { }
1876 };
1877 MODULE_DEVICE_TABLE(of, ravb_match_table);
1878
1879 static int ravb_set_gti(struct net_device *ndev)
1880 {
1881
1882 struct device *dev = ndev->dev.parent;
1883 struct device_node *np = dev->of_node;
1884 unsigned long rate;
1885 struct clk *clk;
1886 uint64_t inc;
1887
1888 clk = of_clk_get(np, 0);
1889 if (IS_ERR(clk)) {
1890 dev_err(dev, "could not get clock\n");
1891 return PTR_ERR(clk);
1892 }
1893
1894 rate = clk_get_rate(clk);
1895 clk_put(clk);
1896
1897 if (!rate)
1898 return -EINVAL;
1899
1900 inc = 1000000000ULL << 20;
1901 do_div(inc, rate);
1902
1903 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1904 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1905 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1906 return -EINVAL;
1907 }
1908
1909 ravb_write(ndev, inc, GTI);
1910
1911 return 0;
1912 }
1913
1914 static void ravb_set_config_mode(struct net_device *ndev)
1915 {
1916 struct ravb_private *priv = netdev_priv(ndev);
1917
1918 if (priv->chip_id == RCAR_GEN2) {
1919 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1920 /* Set CSEL value */
1921 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1922 } else {
1923 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1924 CCC_GAC | CCC_CSEL_HPB);
1925 }
1926 }
1927
1928 static int ravb_probe(struct platform_device *pdev)
1929 {
1930 struct device_node *np = pdev->dev.of_node;
1931 struct ravb_private *priv;
1932 enum ravb_chip_id chip_id;
1933 struct net_device *ndev;
1934 int error, irq, q;
1935 struct resource *res;
1936 int i;
1937
1938 if (!np) {
1939 dev_err(&pdev->dev,
1940 "this driver is required to be instantiated from device tree\n");
1941 return -EINVAL;
1942 }
1943
1944 /* Get base address */
1945 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1946 if (!res) {
1947 dev_err(&pdev->dev, "invalid resource\n");
1948 return -EINVAL;
1949 }
1950
1951 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1952 NUM_TX_QUEUE, NUM_RX_QUEUE);
1953 if (!ndev)
1954 return -ENOMEM;
1955
1956 pm_runtime_enable(&pdev->dev);
1957 pm_runtime_get_sync(&pdev->dev);
1958
1959 /* The Ether-specific entries in the device structure. */
1960 ndev->base_addr = res->start;
1961
1962 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
1963
1964 if (chip_id == RCAR_GEN3)
1965 irq = platform_get_irq_byname(pdev, "ch22");
1966 else
1967 irq = platform_get_irq(pdev, 0);
1968 if (irq < 0) {
1969 error = irq;
1970 goto out_release;
1971 }
1972 ndev->irq = irq;
1973
1974 SET_NETDEV_DEV(ndev, &pdev->dev);
1975
1976 priv = netdev_priv(ndev);
1977 priv->ndev = ndev;
1978 priv->pdev = pdev;
1979 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1980 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1981 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1982 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1983 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1984 if (IS_ERR(priv->addr)) {
1985 error = PTR_ERR(priv->addr);
1986 goto out_release;
1987 }
1988
1989 spin_lock_init(&priv->lock);
1990 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1991
1992 priv->phy_interface = of_get_phy_mode(np);
1993
1994 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1995 priv->avb_link_active_low =
1996 of_property_read_bool(np, "renesas,ether-link-active-low");
1997
1998 if (chip_id == RCAR_GEN3) {
1999 irq = platform_get_irq_byname(pdev, "ch24");
2000 if (irq < 0) {
2001 error = irq;
2002 goto out_release;
2003 }
2004 priv->emac_irq = irq;
2005 for (i = 0; i < NUM_RX_QUEUE; i++) {
2006 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2007 if (irq < 0) {
2008 error = irq;
2009 goto out_release;
2010 }
2011 priv->rx_irqs[i] = irq;
2012 }
2013 for (i = 0; i < NUM_TX_QUEUE; i++) {
2014 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2015 if (irq < 0) {
2016 error = irq;
2017 goto out_release;
2018 }
2019 priv->tx_irqs[i] = irq;
2020 }
2021 }
2022
2023 priv->chip_id = chip_id;
2024
2025 /* Set function */
2026 ndev->netdev_ops = &ravb_netdev_ops;
2027 ndev->ethtool_ops = &ravb_ethtool_ops;
2028
2029 /* Set AVB config mode */
2030 ravb_set_config_mode(ndev);
2031
2032 /* Set GTI value */
2033 error = ravb_set_gti(ndev);
2034 if (error)
2035 goto out_release;
2036
2037 /* Request GTI loading */
2038 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2039
2040 /* Allocate descriptor base address table */
2041 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2042 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2043 &priv->desc_bat_dma, GFP_KERNEL);
2044 if (!priv->desc_bat) {
2045 dev_err(&pdev->dev,
2046 "Cannot allocate desc base address table (size %d bytes)\n",
2047 priv->desc_bat_size);
2048 error = -ENOMEM;
2049 goto out_release;
2050 }
2051 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2052 priv->desc_bat[q].die_dt = DT_EOS;
2053 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2054
2055 /* Initialise HW timestamp list */
2056 INIT_LIST_HEAD(&priv->ts_skb_list);
2057
2058 /* Initialise PTP Clock driver */
2059 if (chip_id != RCAR_GEN2)
2060 ravb_ptp_init(ndev, pdev);
2061
2062 /* Debug message level */
2063 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2064
2065 /* Read and set MAC address */
2066 ravb_read_mac_address(ndev, of_get_mac_address(np));
2067 if (!is_valid_ether_addr(ndev->dev_addr)) {
2068 dev_warn(&pdev->dev,
2069 "no valid MAC address supplied, using a random one\n");
2070 eth_hw_addr_random(ndev);
2071 }
2072
2073 /* MDIO bus init */
2074 error = ravb_mdio_init(priv);
2075 if (error) {
2076 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2077 goto out_dma_free;
2078 }
2079
2080 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2081 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2082
2083 /* Network device register */
2084 error = register_netdev(ndev);
2085 if (error)
2086 goto out_napi_del;
2087
2088 /* Print device information */
2089 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2090 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2091
2092 platform_set_drvdata(pdev, ndev);
2093
2094 return 0;
2095
2096 out_napi_del:
2097 netif_napi_del(&priv->napi[RAVB_NC]);
2098 netif_napi_del(&priv->napi[RAVB_BE]);
2099 ravb_mdio_release(priv);
2100 out_dma_free:
2101 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2102 priv->desc_bat_dma);
2103
2104 /* Stop PTP Clock driver */
2105 if (chip_id != RCAR_GEN2)
2106 ravb_ptp_stop(ndev);
2107 out_release:
2108 if (ndev)
2109 free_netdev(ndev);
2110
2111 pm_runtime_put(&pdev->dev);
2112 pm_runtime_disable(&pdev->dev);
2113 return error;
2114 }
2115
2116 static int ravb_remove(struct platform_device *pdev)
2117 {
2118 struct net_device *ndev = platform_get_drvdata(pdev);
2119 struct ravb_private *priv = netdev_priv(ndev);
2120
2121 /* Stop PTP Clock driver */
2122 if (priv->chip_id != RCAR_GEN2)
2123 ravb_ptp_stop(ndev);
2124
2125 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2126 priv->desc_bat_dma);
2127 /* Set reset mode */
2128 ravb_write(ndev, CCC_OPC_RESET, CCC);
2129 pm_runtime_put_sync(&pdev->dev);
2130 unregister_netdev(ndev);
2131 netif_napi_del(&priv->napi[RAVB_NC]);
2132 netif_napi_del(&priv->napi[RAVB_BE]);
2133 ravb_mdio_release(priv);
2134 pm_runtime_disable(&pdev->dev);
2135 free_netdev(ndev);
2136 platform_set_drvdata(pdev, NULL);
2137
2138 return 0;
2139 }
2140
2141 static int __maybe_unused ravb_suspend(struct device *dev)
2142 {
2143 struct net_device *ndev = dev_get_drvdata(dev);
2144 int ret = 0;
2145
2146 if (netif_running(ndev)) {
2147 netif_device_detach(ndev);
2148 ret = ravb_close(ndev);
2149 }
2150
2151 return ret;
2152 }
2153
2154 static int __maybe_unused ravb_resume(struct device *dev)
2155 {
2156 struct net_device *ndev = dev_get_drvdata(dev);
2157 struct ravb_private *priv = netdev_priv(ndev);
2158 int ret = 0;
2159
2160 /* All register have been reset to default values.
2161 * Restore all registers which where setup at probe time and
2162 * reopen device if it was running before system suspended.
2163 */
2164
2165 /* Set AVB config mode */
2166 ravb_set_config_mode(ndev);
2167
2168 /* Set GTI value */
2169 ret = ravb_set_gti(ndev);
2170 if (ret)
2171 return ret;
2172
2173 /* Request GTI loading */
2174 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2175
2176 /* Restore descriptor base address table */
2177 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2178
2179 if (netif_running(ndev)) {
2180 ret = ravb_open(ndev);
2181 if (ret < 0)
2182 return ret;
2183 netif_device_attach(ndev);
2184 }
2185
2186 return ret;
2187 }
2188
2189 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2190 {
2191 /* Runtime PM callback shared between ->runtime_suspend()
2192 * and ->runtime_resume(). Simply returns success.
2193 *
2194 * This driver re-initializes all registers after
2195 * pm_runtime_get_sync() anyway so there is no need
2196 * to save and restore registers here.
2197 */
2198 return 0;
2199 }
2200
2201 static const struct dev_pm_ops ravb_dev_pm_ops = {
2202 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2203 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2204 };
2205
2206 static struct platform_driver ravb_driver = {
2207 .probe = ravb_probe,
2208 .remove = ravb_remove,
2209 .driver = {
2210 .name = "ravb",
2211 .pm = &ravb_dev_pm_ops,
2212 .of_match_table = ravb_match_table,
2213 },
2214 };
2215
2216 module_platform_driver(ravb_driver);
2217
2218 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2219 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2220 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support