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Linux 4.19.133
[linux/fpc-iii.git] / drivers / spi / spi-fsl-dspi.c
blob2844c9a72a980be1c1f002416218a99823ac712b
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2013 Freescale Semiconductor, Inc.
4 // Copyright 2020 NXP
5 //
6 // Freescale DSPI driver
7 // This file contains a driver for the Freescale DSPI
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/math64.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regmap.h>
26 #include <linux/sched.h>
27 #include <linux/spi/spi.h>
28 #include <linux/spi/spi-fsl-dspi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/time.h>
31
32 #define DRIVER_NAME "fsl-dspi"
33
34 #ifdef CONFIG_M5441x
35 #define DSPI_FIFO_SIZE 16
36 #else
37 #define DSPI_FIFO_SIZE 4
38 #endif
39 #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
40
41 #define SPI_MCR 0x00
42 #define SPI_MCR_MASTER (1 << 31)
43 #define SPI_MCR_PCSIS (0x3F << 16)
44 #define SPI_MCR_CLR_TXF (1 << 11)
45 #define SPI_MCR_CLR_RXF (1 << 10)
46 #define SPI_MCR_XSPI (1 << 3)
47 #define SPI_MCR_DIS_TXF (1 << 13)
48 #define SPI_MCR_DIS_RXF (1 << 12)
49 #define SPI_MCR_HALT (1 << 0)
50
51 #define SPI_TCR 0x08
52 #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
53
54 #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
55 #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
56 #define SPI_CTAR_CPOL(x) ((x) << 26)
57 #define SPI_CTAR_CPHA(x) ((x) << 25)
58 #define SPI_CTAR_LSBFE(x) ((x) << 24)
59 #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
60 #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
61 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
62 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
63 #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
64 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
65 #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
66 #define SPI_CTAR_BR(x) ((x) & 0x0000000f)
67 #define SPI_CTAR_SCALE_BITS 0xf
68
69 #define SPI_CTAR0_SLAVE 0x0c
70
71 #define SPI_SR 0x2c
72 #define SPI_SR_EOQF 0x10000000
73 #define SPI_SR_TCFQF 0x80000000
74 #define SPI_SR_CLEAR 0xdaad0000
75
76 #define SPI_RSER_TFFFE BIT(25)
77 #define SPI_RSER_TFFFD BIT(24)
78 #define SPI_RSER_RFDFE BIT(17)
79 #define SPI_RSER_RFDFD BIT(16)
80
81 #define SPI_RSER 0x30
82 #define SPI_RSER_EOQFE 0x10000000
83 #define SPI_RSER_TCFQE 0x80000000
84
85 #define SPI_PUSHR 0x34
86 #define SPI_PUSHR_CMD_CONT (1 << 15)
87 #define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16)
88 #define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12)
89 #define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16)
90 #define SPI_PUSHR_CMD_EOQ (1 << 11)
91 #define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16)
92 #define SPI_PUSHR_CMD_CTCNT (1 << 10)
93 #define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16)
94 #define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f)
95 #define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16)
96 #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
97
98 #define SPI_PUSHR_SLAVE 0x34
99
100 #define SPI_POPR 0x38
101 #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
102
103 #define SPI_TXFR0 0x3c
104 #define SPI_TXFR1 0x40
105 #define SPI_TXFR2 0x44
106 #define SPI_TXFR3 0x48
107 #define SPI_RXFR0 0x7c
108 #define SPI_RXFR1 0x80
109 #define SPI_RXFR2 0x84
110 #define SPI_RXFR3 0x88
111
112 #define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4))
113 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
114 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
115
116 #define SPI_SREX 0x13c
117
118 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
119 #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
120 #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
121 #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
122
123 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
124 #define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1)
125
126 /* Register offsets for regmap_pushr */
127 #define PUSHR_CMD 0x0
128 #define PUSHR_TX 0x2
129
130 #define SPI_CS_INIT 0x01
131 #define SPI_CS_ASSERT 0x02
132 #define SPI_CS_DROP 0x04
133
134 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
135
136 struct chip_data {
137 u32 ctar_val;
138 u16 void_write_data;
139 };
140
141 enum dspi_trans_mode {
142 DSPI_EOQ_MODE = 0,
143 DSPI_TCFQ_MODE,
144 DSPI_DMA_MODE,
145 };
146
147 struct fsl_dspi_devtype_data {
148 enum dspi_trans_mode trans_mode;
149 u8 max_clock_factor;
150 bool xspi_mode;
151 };
152
153 static const struct fsl_dspi_devtype_data vf610_data = {
154 .trans_mode = DSPI_DMA_MODE,
155 .max_clock_factor = 2,
156 };
157
158 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
159 .trans_mode = DSPI_TCFQ_MODE,
160 .max_clock_factor = 8,
161 .xspi_mode = true,
162 };
163
164 static const struct fsl_dspi_devtype_data ls2085a_data = {
165 .trans_mode = DSPI_TCFQ_MODE,
166 .max_clock_factor = 8,
167 };
168
169 static const struct fsl_dspi_devtype_data coldfire_data = {
170 .trans_mode = DSPI_EOQ_MODE,
171 .max_clock_factor = 8,
172 };
173
174 struct fsl_dspi_dma {
175 /* Length of transfer in words of DSPI_FIFO_SIZE */
176 u32 curr_xfer_len;
177
178 u32 *tx_dma_buf;
179 struct dma_chan *chan_tx;
180 dma_addr_t tx_dma_phys;
181 struct completion cmd_tx_complete;
182 struct dma_async_tx_descriptor *tx_desc;
183
184 u32 *rx_dma_buf;
185 struct dma_chan *chan_rx;
186 dma_addr_t rx_dma_phys;
187 struct completion cmd_rx_complete;
188 struct dma_async_tx_descriptor *rx_desc;
189 };
190
191 struct fsl_dspi {
192 struct spi_master *master;
193 struct platform_device *pdev;
194
195 struct regmap *regmap;
196 struct regmap *regmap_pushr;
197 int irq;
198 struct clk *clk;
199
200 struct spi_transfer *cur_transfer;
201 struct spi_message *cur_msg;
202 struct chip_data *cur_chip;
203 size_t len;
204 const void *tx;
205 void *rx;
206 void *rx_end;
207 u16 void_write_data;
208 u16 tx_cmd;
209 u8 bits_per_word;
210 u8 bytes_per_word;
211 const struct fsl_dspi_devtype_data *devtype_data;
212
213 wait_queue_head_t waitq;
214 u32 waitflags;
215
216 struct fsl_dspi_dma *dma;
217 };
218
219 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
220 {
221 u32 txdata = 0;
222
223 if (dspi->tx) {
224 if (dspi->bytes_per_word == 1)
225 txdata = *(u8 *)dspi->tx;
226 else if (dspi->bytes_per_word == 2)
227 txdata = *(u16 *)dspi->tx;
228 else /* dspi->bytes_per_word == 4 */
229 txdata = *(u32 *)dspi->tx;
230 dspi->tx += dspi->bytes_per_word;
231 }
232 dspi->len -= dspi->bytes_per_word;
233 return txdata;
234 }
235
236 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
237 {
238 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
239
240 if (dspi->len > 0)
241 cmd |= SPI_PUSHR_CMD_CONT;
242 return cmd << 16 | data;
243 }
244
245 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
246 {
247 if (!dspi->rx)
248 return;
249
250 /* Mask of undefined bits */
251 rxdata &= (1 << dspi->bits_per_word) - 1;
252
253 if (dspi->bytes_per_word == 1)
254 *(u8 *)dspi->rx = rxdata;
255 else if (dspi->bytes_per_word == 2)
256 *(u16 *)dspi->rx = rxdata;
257 else /* dspi->bytes_per_word == 4 */
258 *(u32 *)dspi->rx = rxdata;
259 dspi->rx += dspi->bytes_per_word;
260 }
261
262 static void dspi_tx_dma_callback(void *arg)
263 {
264 struct fsl_dspi *dspi = arg;
265 struct fsl_dspi_dma *dma = dspi->dma;
266
267 complete(&dma->cmd_tx_complete);
268 }
269
270 static void dspi_rx_dma_callback(void *arg)
271 {
272 struct fsl_dspi *dspi = arg;
273 struct fsl_dspi_dma *dma = dspi->dma;
274 int i;
275
276 if (dspi->rx) {
277 for (i = 0; i < dma->curr_xfer_len; i++)
278 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
279 }
280
281 complete(&dma->cmd_rx_complete);
282 }
283
284 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
285 {
286 struct fsl_dspi_dma *dma = dspi->dma;
287 struct device *dev = &dspi->pdev->dev;
288 int time_left;
289 int i;
290
291 for (i = 0; i < dma->curr_xfer_len; i++)
292 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
293
294 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
295 dma->tx_dma_phys,
296 dma->curr_xfer_len *
297 DMA_SLAVE_BUSWIDTH_4_BYTES,
298 DMA_MEM_TO_DEV,
299 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
300 if (!dma->tx_desc) {
301 dev_err(dev, "Not able to get desc for DMA xfer\n");
302 return -EIO;
303 }
304
305 dma->tx_desc->callback = dspi_tx_dma_callback;
306 dma->tx_desc->callback_param = dspi;
307 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
308 dev_err(dev, "DMA submit failed\n");
309 return -EINVAL;
310 }
311
312 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
313 dma->rx_dma_phys,
314 dma->curr_xfer_len *
315 DMA_SLAVE_BUSWIDTH_4_BYTES,
316 DMA_DEV_TO_MEM,
317 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
318 if (!dma->rx_desc) {
319 dev_err(dev, "Not able to get desc for DMA xfer\n");
320 return -EIO;
321 }
322
323 dma->rx_desc->callback = dspi_rx_dma_callback;
324 dma->rx_desc->callback_param = dspi;
325 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
326 dev_err(dev, "DMA submit failed\n");
327 return -EINVAL;
328 }
329
330 reinit_completion(&dspi->dma->cmd_rx_complete);
331 reinit_completion(&dspi->dma->cmd_tx_complete);
332
333 dma_async_issue_pending(dma->chan_rx);
334 dma_async_issue_pending(dma->chan_tx);
335
336 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
337 DMA_COMPLETION_TIMEOUT);
338 if (time_left == 0) {
339 dev_err(dev, "DMA tx timeout\n");
340 dmaengine_terminate_all(dma->chan_tx);
341 dmaengine_terminate_all(dma->chan_rx);
342 return -ETIMEDOUT;
343 }
344
345 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
346 DMA_COMPLETION_TIMEOUT);
347 if (time_left == 0) {
348 dev_err(dev, "DMA rx timeout\n");
349 dmaengine_terminate_all(dma->chan_tx);
350 dmaengine_terminate_all(dma->chan_rx);
351 return -ETIMEDOUT;
352 }
353
354 return 0;
355 }
356
357 static int dspi_dma_xfer(struct fsl_dspi *dspi)
358 {
359 struct fsl_dspi_dma *dma = dspi->dma;
360 struct device *dev = &dspi->pdev->dev;
361 struct spi_message *message = dspi->cur_msg;
362 int curr_remaining_bytes;
363 int bytes_per_buffer;
364 int ret = 0;
365
366 curr_remaining_bytes = dspi->len;
367 bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
368 while (curr_remaining_bytes) {
369 /* Check if current transfer fits the DMA buffer */
370 dma->curr_xfer_len = curr_remaining_bytes
371 / dspi->bytes_per_word;
372 if (dma->curr_xfer_len > bytes_per_buffer)
373 dma->curr_xfer_len = bytes_per_buffer;
374
375 ret = dspi_next_xfer_dma_submit(dspi);
376 if (ret) {
377 dev_err(dev, "DMA transfer failed\n");
378 goto exit;
379
380 } else {
381 const int len =
382 dma->curr_xfer_len * dspi->bytes_per_word;
383 curr_remaining_bytes -= len;
384 message->actual_length += len;
385 if (curr_remaining_bytes < 0)
386 curr_remaining_bytes = 0;
387 }
388 }
389
390 exit:
391 return ret;
392 }
393
394 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
395 {
396 struct fsl_dspi_dma *dma;
397 struct dma_slave_config cfg;
398 struct device *dev = &dspi->pdev->dev;
399 int ret;
400
401 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
402 if (!dma)
403 return -ENOMEM;
404
405 dma->chan_rx = dma_request_slave_channel(dev, "rx");
406 if (!dma->chan_rx) {
407 dev_err(dev, "rx dma channel not available\n");
408 ret = -ENODEV;
409 return ret;
410 }
411
412 dma->chan_tx = dma_request_slave_channel(dev, "tx");
413 if (!dma->chan_tx) {
414 dev_err(dev, "tx dma channel not available\n");
415 ret = -ENODEV;
416 goto err_tx_channel;
417 }
418
419 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
420 &dma->tx_dma_phys, GFP_KERNEL);
421 if (!dma->tx_dma_buf) {
422 ret = -ENOMEM;
423 goto err_tx_dma_buf;
424 }
425
426 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
427 &dma->rx_dma_phys, GFP_KERNEL);
428 if (!dma->rx_dma_buf) {
429 ret = -ENOMEM;
430 goto err_rx_dma_buf;
431 }
432
433 cfg.src_addr = phy_addr + SPI_POPR;
434 cfg.dst_addr = phy_addr + SPI_PUSHR;
435 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
436 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
437 cfg.src_maxburst = 1;
438 cfg.dst_maxburst = 1;
439
440 cfg.direction = DMA_DEV_TO_MEM;
441 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
442 if (ret) {
443 dev_err(dev, "can't configure rx dma channel\n");
444 ret = -EINVAL;
445 goto err_slave_config;
446 }
447
448 cfg.direction = DMA_MEM_TO_DEV;
449 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
450 if (ret) {
451 dev_err(dev, "can't configure tx dma channel\n");
452 ret = -EINVAL;
453 goto err_slave_config;
454 }
455
456 dspi->dma = dma;
457 init_completion(&dma->cmd_tx_complete);
458 init_completion(&dma->cmd_rx_complete);
459
460 return 0;
461
462 err_slave_config:
463 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
464 dma->rx_dma_buf, dma->rx_dma_phys);
465 err_rx_dma_buf:
466 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
467 dma->tx_dma_buf, dma->tx_dma_phys);
468 err_tx_dma_buf:
469 dma_release_channel(dma->chan_tx);
470 err_tx_channel:
471 dma_release_channel(dma->chan_rx);
472
473 devm_kfree(dev, dma);
474 dspi->dma = NULL;
475
476 return ret;
477 }
478
479 static void dspi_release_dma(struct fsl_dspi *dspi)
480 {
481 struct fsl_dspi_dma *dma = dspi->dma;
482 struct device *dev = &dspi->pdev->dev;
483
484 if (dma) {
485 if (dma->chan_tx) {
486 dma_unmap_single(dev, dma->tx_dma_phys,
487 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
488 dma_release_channel(dma->chan_tx);
489 }
490
491 if (dma->chan_rx) {
492 dma_unmap_single(dev, dma->rx_dma_phys,
493 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
494 dma_release_channel(dma->chan_rx);
495 }
496 }
497 }
498
499 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
500 unsigned long clkrate)
501 {
502 /* Valid baud rate pre-scaler values */
503 int pbr_tbl[4] = {2, 3, 5, 7};
504 int brs[16] = { 2, 4, 6, 8,
505 16, 32, 64, 128,
506 256, 512, 1024, 2048,
507 4096, 8192, 16384, 32768 };
508 int scale_needed, scale, minscale = INT_MAX;
509 int i, j;
510
511 scale_needed = clkrate / speed_hz;
512 if (clkrate % speed_hz)
513 scale_needed++;
514
515 for (i = 0; i < ARRAY_SIZE(brs); i++)
516 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
517 scale = brs[i] * pbr_tbl[j];
518 if (scale >= scale_needed) {
519 if (scale < minscale) {
520 minscale = scale;
521 *br = i;
522 *pbr = j;
523 }
524 break;
525 }
526 }
527
528 if (minscale == INT_MAX) {
529 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
530 speed_hz, clkrate);
531 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
532 *br = ARRAY_SIZE(brs) - 1;
533 }
534 }
535
536 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
537 unsigned long clkrate)
538 {
539 int pscale_tbl[4] = {1, 3, 5, 7};
540 int scale_needed, scale, minscale = INT_MAX;
541 int i, j;
542 u32 remainder;
543
544 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
545 &remainder);
546 if (remainder)
547 scale_needed++;
548
549 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
550 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
551 scale = pscale_tbl[i] * (2 << j);
552 if (scale >= scale_needed) {
553 if (scale < minscale) {
554 minscale = scale;
555 *psc = i;
556 *sc = j;
557 }
558 break;
559 }
560 }
561
562 if (minscale == INT_MAX) {
563 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
564 delay_ns, clkrate);
565 *psc = ARRAY_SIZE(pscale_tbl) - 1;
566 *sc = SPI_CTAR_SCALE_BITS;
567 }
568 }
569
570 static void fifo_write(struct fsl_dspi *dspi)
571 {
572 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
573 }
574
575 static void cmd_fifo_write(struct fsl_dspi *dspi)
576 {
577 u16 cmd = dspi->tx_cmd;
578
579 if (dspi->len > 0)
580 cmd |= SPI_PUSHR_CMD_CONT;
581 regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
582 }
583
584 static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata)
585 {
586 regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
587 }
588
589 static void dspi_tcfq_write(struct fsl_dspi *dspi)
590 {
591 /* Clear transfer count */
592 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
593
594 if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
595 /* Write two TX FIFO entries first, and then the corresponding
596 * CMD FIFO entry.
597 */
598 u32 data = dspi_pop_tx(dspi);
599
600 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) {
601 /* LSB */
602 tx_fifo_write(dspi, data & 0xFFFF);
603 tx_fifo_write(dspi, data >> 16);
604 } else {
605 /* MSB */
606 tx_fifo_write(dspi, data >> 16);
607 tx_fifo_write(dspi, data & 0xFFFF);
608 }
609 cmd_fifo_write(dspi);
610 } else {
611 /* Write one entry to both TX FIFO and CMD FIFO
612 * simultaneously.
613 */
614 fifo_write(dspi);
615 }
616 }
617
618 static u32 fifo_read(struct fsl_dspi *dspi)
619 {
620 u32 rxdata = 0;
621
622 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
623 return rxdata;
624 }
625
626 static void dspi_tcfq_read(struct fsl_dspi *dspi)
627 {
628 dspi_push_rx(dspi, fifo_read(dspi));
629 }
630
631 static void dspi_eoq_write(struct fsl_dspi *dspi)
632 {
633 int fifo_size = DSPI_FIFO_SIZE;
634 u16 xfer_cmd = dspi->tx_cmd;
635
636 /* Fill TX FIFO with as many transfers as possible */
637 while (dspi->len && fifo_size--) {
638 dspi->tx_cmd = xfer_cmd;
639 /* Request EOQF for last transfer in FIFO */
640 if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
641 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
642 /* Clear transfer count for first transfer in FIFO */
643 if (fifo_size == (DSPI_FIFO_SIZE - 1))
644 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
645 /* Write combined TX FIFO and CMD FIFO entry */
646 fifo_write(dspi);
647 }
648 }
649
650 static void dspi_eoq_read(struct fsl_dspi *dspi)
651 {
652 int fifo_size = DSPI_FIFO_SIZE;
653
654 /* Read one FIFO entry at and push to rx buffer */
655 while ((dspi->rx < dspi->rx_end) && fifo_size--)
656 dspi_push_rx(dspi, fifo_read(dspi));
657 }
658
659 static int dspi_transfer_one_message(struct spi_master *master,
660 struct spi_message *message)
661 {
662 struct fsl_dspi *dspi = spi_master_get_devdata(master);
663 struct spi_device *spi = message->spi;
664 struct spi_transfer *transfer;
665 int status = 0;
666 enum dspi_trans_mode trans_mode;
667
668 message->actual_length = 0;
669
670 list_for_each_entry(transfer, &message->transfers, transfer_list) {
671 dspi->cur_transfer = transfer;
672 dspi->cur_msg = message;
673 dspi->cur_chip = spi_get_ctldata(spi);
674 /* Prepare command word for CMD FIFO */
675 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
676 SPI_PUSHR_CMD_PCS(spi->chip_select);
677 if (list_is_last(&dspi->cur_transfer->transfer_list,
678 &dspi->cur_msg->transfers)) {
679 /* Leave PCS activated after last transfer when
680 * cs_change is set.
681 */
682 if (transfer->cs_change)
683 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
684 } else {
685 /* Keep PCS active between transfers in same message
686 * when cs_change is not set, and de-activate PCS
687 * between transfers in the same message when
688 * cs_change is set.
689 */
690 if (!transfer->cs_change)
691 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
692 }
693
694 dspi->void_write_data = dspi->cur_chip->void_write_data;
695
696 dspi->tx = transfer->tx_buf;
697 dspi->rx = transfer->rx_buf;
698 dspi->rx_end = dspi->rx + transfer->len;
699 dspi->len = transfer->len;
700 /* Validated transfer specific frame size (defaults applied) */
701 dspi->bits_per_word = transfer->bits_per_word;
702 if (transfer->bits_per_word <= 8)
703 dspi->bytes_per_word = 1;
704 else if (transfer->bits_per_word <= 16)
705 dspi->bytes_per_word = 2;
706 else
707 dspi->bytes_per_word = 4;
708
709 regmap_update_bits(dspi->regmap, SPI_MCR,
710 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
711 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
712 regmap_write(dspi->regmap, SPI_CTAR(0),
713 dspi->cur_chip->ctar_val |
714 SPI_FRAME_BITS(transfer->bits_per_word));
715 if (dspi->devtype_data->xspi_mode)
716 regmap_write(dspi->regmap, SPI_CTARE(0),
717 SPI_FRAME_EBITS(transfer->bits_per_word)
718 | SPI_CTARE_DTCP(1));
719
720 trans_mode = dspi->devtype_data->trans_mode;
721 switch (trans_mode) {
722 case DSPI_EOQ_MODE:
723 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
724 dspi_eoq_write(dspi);
725 break;
726 case DSPI_TCFQ_MODE:
727 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
728 dspi_tcfq_write(dspi);
729 break;
730 case DSPI_DMA_MODE:
731 regmap_write(dspi->regmap, SPI_RSER,
732 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
733 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
734 status = dspi_dma_xfer(dspi);
735 break;
736 default:
737 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
738 trans_mode);
739 status = -EINVAL;
740 goto out;
741 }
742
743 if (trans_mode != DSPI_DMA_MODE) {
744 if (wait_event_interruptible(dspi->waitq,
745 dspi->waitflags))
746 dev_err(&dspi->pdev->dev,
747 "wait transfer complete fail!\n");
748 dspi->waitflags = 0;
749 }
750
751 if (transfer->delay_usecs)
752 udelay(transfer->delay_usecs);
753 }
754
755 out:
756 message->status = status;
757 spi_finalize_current_message(master);
758
759 return status;
760 }
761
762 static int dspi_setup(struct spi_device *spi)
763 {
764 struct chip_data *chip;
765 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
766 struct fsl_dspi_platform_data *pdata;
767 u32 cs_sck_delay = 0, sck_cs_delay = 0;
768 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
769 unsigned char pasc = 0, asc = 0;
770 unsigned long clkrate;
771
772 /* Only alloc on first setup */
773 chip = spi_get_ctldata(spi);
774 if (chip == NULL) {
775 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
776 if (!chip)
777 return -ENOMEM;
778 }
779
780 pdata = dev_get_platdata(&dspi->pdev->dev);
781
782 if (!pdata) {
783 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
784 &cs_sck_delay);
785
786 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
787 &sck_cs_delay);
788 } else {
789 cs_sck_delay = pdata->cs_sck_delay;
790 sck_cs_delay = pdata->sck_cs_delay;
791 }
792
793 chip->void_write_data = 0;
794
795 clkrate = clk_get_rate(dspi->clk);
796 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
797
798 /* Set PCS to SCK delay scale values */
799 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
800
801 /* Set After SCK delay scale values */
802 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
803
804 chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
805 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
806 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
807 | SPI_CTAR_PCSSCK(pcssck)
808 | SPI_CTAR_CSSCK(cssck)
809 | SPI_CTAR_PASC(pasc)
810 | SPI_CTAR_ASC(asc)
811 | SPI_CTAR_PBR(pbr)
812 | SPI_CTAR_BR(br);
813
814 spi_set_ctldata(spi, chip);
815
816 return 0;
817 }
818
819 static void dspi_cleanup(struct spi_device *spi)
820 {
821 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
822
823 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
824 spi->master->bus_num, spi->chip_select);
825
826 kfree(chip);
827 }
828
829 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
830 {
831 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
832 struct spi_message *msg = dspi->cur_msg;
833 enum dspi_trans_mode trans_mode;
834 u32 spi_sr, spi_tcr;
835 u16 spi_tcnt;
836
837 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
838 regmap_write(dspi->regmap, SPI_SR, spi_sr);
839
840
841 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
842 /* Get transfer counter (in number of SPI transfers). It was
843 * reset to 0 when transfer(s) were started.
844 */
845 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
846 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
847 /* Update total number of bytes that were transferred */
848 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
849
850 trans_mode = dspi->devtype_data->trans_mode;
851 switch (trans_mode) {
852 case DSPI_EOQ_MODE:
853 dspi_eoq_read(dspi);
854 break;
855 case DSPI_TCFQ_MODE:
856 dspi_tcfq_read(dspi);
857 break;
858 default:
859 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
860 trans_mode);
861 return IRQ_HANDLED;
862 }
863
864 if (!dspi->len) {
865 dspi->waitflags = 1;
866 wake_up_interruptible(&dspi->waitq);
867 } else {
868 switch (trans_mode) {
869 case DSPI_EOQ_MODE:
870 dspi_eoq_write(dspi);
871 break;
872 case DSPI_TCFQ_MODE:
873 dspi_tcfq_write(dspi);
874 break;
875 default:
876 dev_err(&dspi->pdev->dev,
877 "unsupported trans_mode %u\n",
878 trans_mode);
879 }
880 }
881 }
882
883 return IRQ_HANDLED;
884 }
885
886 static const struct of_device_id fsl_dspi_dt_ids[] = {
887 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
888 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
889 { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
890 { /* sentinel */ }
891 };
892 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
893
894 #ifdef CONFIG_PM_SLEEP
895 static int dspi_suspend(struct device *dev)
896 {
897 struct spi_master *master = dev_get_drvdata(dev);
898 struct fsl_dspi *dspi = spi_master_get_devdata(master);
899
900 if (dspi->irq)
901 disable_irq(dspi->irq);
902 spi_master_suspend(master);
903 clk_disable_unprepare(dspi->clk);
904
905 pinctrl_pm_select_sleep_state(dev);
906
907 return 0;
908 }
909
910 static int dspi_resume(struct device *dev)
911 {
912 struct spi_master *master = dev_get_drvdata(dev);
913 struct fsl_dspi *dspi = spi_master_get_devdata(master);
914 int ret;
915
916 pinctrl_pm_select_default_state(dev);
917
918 ret = clk_prepare_enable(dspi->clk);
919 if (ret)
920 return ret;
921 spi_master_resume(master);
922 if (dspi->irq)
923 enable_irq(dspi->irq);
924
925 return 0;
926 }
927 #endif /* CONFIG_PM_SLEEP */
928
929 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
930
931 static const struct regmap_range dspi_volatile_ranges[] = {
932 regmap_reg_range(SPI_MCR, SPI_TCR),
933 regmap_reg_range(SPI_SR, SPI_SR),
934 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
935 };
936
937 static const struct regmap_access_table dspi_volatile_table = {
938 .yes_ranges = dspi_volatile_ranges,
939 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
940 };
941
942 static const struct regmap_config dspi_regmap_config = {
943 .reg_bits = 32,
944 .val_bits = 32,
945 .reg_stride = 4,
946 .max_register = 0x88,
947 .volatile_table = &dspi_volatile_table,
948 };
949
950 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
951 regmap_reg_range(SPI_MCR, SPI_TCR),
952 regmap_reg_range(SPI_SR, SPI_SR),
953 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
954 regmap_reg_range(SPI_SREX, SPI_SREX),
955 };
956
957 static const struct regmap_access_table dspi_xspi_volatile_table = {
958 .yes_ranges = dspi_xspi_volatile_ranges,
959 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
960 };
961
962 static const struct regmap_config dspi_xspi_regmap_config[] = {
963 {
964 .reg_bits = 32,
965 .val_bits = 32,
966 .reg_stride = 4,
967 .max_register = 0x13c,
968 .volatile_table = &dspi_xspi_volatile_table,
969 },
970 {
971 .name = "pushr",
972 .reg_bits = 16,
973 .val_bits = 16,
974 .reg_stride = 2,
975 .max_register = 0x2,
976 },
977 };
978
979 static void dspi_init(struct fsl_dspi *dspi)
980 {
981 regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS |
982 (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0));
983 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
984 if (dspi->devtype_data->xspi_mode)
985 regmap_write(dspi->regmap, SPI_CTARE(0),
986 SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
987 }
988
989 static int dspi_probe(struct platform_device *pdev)
990 {
991 struct device_node *np = pdev->dev.of_node;
992 struct spi_master *master;
993 struct fsl_dspi *dspi;
994 struct resource *res;
995 const struct regmap_config *regmap_config;
996 void __iomem *base;
997 struct fsl_dspi_platform_data *pdata;
998 int ret = 0, cs_num, bus_num;
999
1000 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
1001 if (!master)
1002 return -ENOMEM;
1003
1004 dspi = spi_master_get_devdata(master);
1005 dspi->pdev = pdev;
1006 dspi->master = master;
1007
1008 master->transfer = NULL;
1009 master->setup = dspi_setup;
1010 master->transfer_one_message = dspi_transfer_one_message;
1011 master->dev.of_node = pdev->dev.of_node;
1012
1013 master->cleanup = dspi_cleanup;
1014 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1015
1016 pdata = dev_get_platdata(&pdev->dev);
1017 if (pdata) {
1018 master->num_chipselect = pdata->cs_num;
1019 master->bus_num = pdata->bus_num;
1020
1021 dspi->devtype_data = &coldfire_data;
1022 } else {
1023
1024 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1025 if (ret < 0) {
1026 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1027 goto out_master_put;
1028 }
1029 master->num_chipselect = cs_num;
1030
1031 ret = of_property_read_u32(np, "bus-num", &bus_num);
1032 if (ret < 0) {
1033 dev_err(&pdev->dev, "can't get bus-num\n");
1034 goto out_master_put;
1035 }
1036 master->bus_num = bus_num;
1037
1038 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1039 if (!dspi->devtype_data) {
1040 dev_err(&pdev->dev, "can't get devtype_data\n");
1041 ret = -EFAULT;
1042 goto out_master_put;
1043 }
1044 }
1045
1046 if (dspi->devtype_data->xspi_mode)
1047 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1048 else
1049 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1050
1051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052 base = devm_ioremap_resource(&pdev->dev, res);
1053 if (IS_ERR(base)) {
1054 ret = PTR_ERR(base);
1055 goto out_master_put;
1056 }
1057
1058 if (dspi->devtype_data->xspi_mode)
1059 regmap_config = &dspi_xspi_regmap_config[0];
1060 else
1061 regmap_config = &dspi_regmap_config;
1062 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1063 if (IS_ERR(dspi->regmap)) {
1064 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1065 PTR_ERR(dspi->regmap));
1066 ret = PTR_ERR(dspi->regmap);
1067 goto out_master_put;
1068 }
1069
1070 if (dspi->devtype_data->xspi_mode) {
1071 dspi->regmap_pushr = devm_regmap_init_mmio(
1072 &pdev->dev, base + SPI_PUSHR,
1073 &dspi_xspi_regmap_config[1]);
1074 if (IS_ERR(dspi->regmap_pushr)) {
1075 dev_err(&pdev->dev,
1076 "failed to init pushr regmap: %ld\n",
1077 PTR_ERR(dspi->regmap_pushr));
1078 ret = PTR_ERR(dspi->regmap_pushr);
1079 goto out_master_put;
1080 }
1081 }
1082
1083 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1084 if (IS_ERR(dspi->clk)) {
1085 ret = PTR_ERR(dspi->clk);
1086 dev_err(&pdev->dev, "unable to get clock\n");
1087 goto out_master_put;
1088 }
1089 ret = clk_prepare_enable(dspi->clk);
1090 if (ret)
1091 goto out_master_put;
1092
1093 dspi_init(dspi);
1094 dspi->irq = platform_get_irq(pdev, 0);
1095 if (dspi->irq < 0) {
1096 dev_err(&pdev->dev, "can't get platform irq\n");
1097 ret = dspi->irq;
1098 goto out_clk_put;
1099 }
1100
1101 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1102 IRQF_SHARED, pdev->name, dspi);
1103 if (ret < 0) {
1104 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1105 goto out_clk_put;
1106 }
1107
1108 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1109 ret = dspi_request_dma(dspi, res->start);
1110 if (ret < 0) {
1111 dev_err(&pdev->dev, "can't get dma channels\n");
1112 goto out_free_irq;
1113 }
1114 }
1115
1116 master->max_speed_hz =
1117 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1118
1119 init_waitqueue_head(&dspi->waitq);
1120 platform_set_drvdata(pdev, master);
1121
1122 ret = spi_register_master(master);
1123 if (ret != 0) {
1124 dev_err(&pdev->dev, "Problem registering DSPI master\n");
1125 goto out_free_irq;
1126 }
1127
1128 return ret;
1129
1130 out_free_irq:
1131 if (dspi->irq)
1132 free_irq(dspi->irq, dspi);
1133 out_clk_put:
1134 clk_disable_unprepare(dspi->clk);
1135 out_master_put:
1136 spi_master_put(master);
1137
1138 return ret;
1139 }
1140
1141 static int dspi_remove(struct platform_device *pdev)
1142 {
1143 struct spi_master *master = platform_get_drvdata(pdev);
1144 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1145
1146 /* Disconnect from the SPI framework */
1147 spi_unregister_controller(dspi->master);
1148
1149 /* Disable RX and TX */
1150 regmap_update_bits(dspi->regmap, SPI_MCR,
1151 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1152 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1153
1154 /* Stop Running */
1155 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1156
1157 dspi_release_dma(dspi);
1158 if (dspi->irq)
1159 free_irq(dspi->irq, dspi);
1160 clk_disable_unprepare(dspi->clk);
1161
1162 return 0;
1163 }
1164
1165 static void dspi_shutdown(struct platform_device *pdev)
1166 {
1167 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1168 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1169
1170 /* Disable RX and TX */
1171 regmap_update_bits(dspi->regmap, SPI_MCR,
1172 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1173 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1174
1175 /* Stop Running */
1176 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1177
1178 dspi_release_dma(dspi);
1179 clk_disable_unprepare(dspi->clk);
1180 spi_unregister_controller(dspi->master);
1181 }
1182
1183 static struct platform_driver fsl_dspi_driver = {
1184 .driver.name = DRIVER_NAME,
1185 .driver.of_match_table = fsl_dspi_dt_ids,
1186 .driver.owner = THIS_MODULE,
1187 .driver.pm = &dspi_pm,
1188 .probe = dspi_probe,
1189 .remove = dspi_remove,
1190 .shutdown = dspi_shutdown,
1191 };
1192 module_platform_driver(fsl_dspi_driver);
1193
1194 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1195 MODULE_LICENSE("GPL");
1196 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support