drivers/staging/sxg/sxghw.h

   1 /*************************************************************
   2  * Copyright © 1997-2007 Alacritech, Inc. All rights reserved
   3  *
   4  * $Id: sxghw.h,v 1.2 2008/07/24 17:24:23 chris Exp $
   5  *
   6  * sxghw.h:
   7  *
   8  * This file contains structures and definitions for the
   9  * Alacritech Sahara hardware
  10  *
  11  **********************************************************/
  12
  13
  14 /* PCI Configuration space */
  15 /*  PCI Vendor ID */
  16 #define SXG_VENDOR_ID                   0x139A  /* Alacritech's Vendor ID */
  17
  18 /*  PCI Device ID */
  19 #define SXG_DEVICE_ID                   0x0009  /* Sahara Device ID */
  20
  21
  22 /* Type of ASIC in use */
  23 enum asic_type {
  24         SAHARA_REV_A,
  25         SAHARA_REV_B
  26 };
  27
  28 /* Type of Xcvr in fiber card */
  29 enum xcvr_type {
  30         XCVR_UNKNOWN,
  31         XCVR_NONE,
  32         XCVR_SR,
  33         XCVR_LR,
  34         XCVR_LRM,
  35         XCVR_CR
  36 };
  37 /*
  38  * Subsystem IDs.
  39  *
  40  * The subsystem ID value is broken into bit fields as follows:
  41  *              Bits [15:12] - Function
  42  *              Bits [11:8]  - OEM and/or operating system.
  43  *              Bits [7:0]   - Base SID.
  44  */
  45
  46 /* SSID field (bit) masks */
  47 #define SSID_BASE_MASK          0x00FF  /* Base subsystem ID mask */
  48 #define SSID_OEM_MASK           0x0F00  /* Subsystem OEM mask */
  49 #define SSID_FUNC_MASK          0xF000  /* Subsystem function mask */
  50
  51 /* Base SSID's */
  52 /* 100022 Sahara prototype (XenPak) board */
  53 #define SSID_SAHARA_PROTO       0x0018
  54 #define SSID_SAHARA_FIBER       0x0019  /* 100023 Sahara 1-port fiber board */
  55 #define SSID_SAHARA_COPPER      0x001A  /* 100024 Sahara 1-port copper board */
  56
  57 /* Useful SSID macros */
  58 /* isolate base SSID bits */
  59 #define SSID_BASE(ssid)         ((ssid) & SSID_BASE_MASK)
  60 /* isolate SSID OEM bits */
  61 #define SSID_OEM(ssid)          ((ssid) & SSID_OEM_MASK)
  62 /* isolate SSID function bits */
  63 #define SSID_FUNC(ssid)         ((ssid) & SSID_FUNC_MASK)
  64
  65
  66 /* HW Register Space */
  67 #define SXG_HWREG_MEMSIZE       0x4000          /* 16k */
  68
  69 #pragma pack(push, 1)
  70 struct sxg_hw_regs {
  71         u32     Reset;          /* Write 0xdead to invoke soft reset */
  72         u32     Pad1;           /* No register defined at offset 4 */
  73         u32     InterruptMask0; /* Deassert legacy interrupt on function 0 */
  74         u32     InterruptMask1; /* Deassert legacy interrupt on function 1 */
  75         u32     UcodeDataLow;   /* Store microcode instruction bits 31-0 */
  76         u32     UcodeDataMiddle;        /* Store microcode instruction bits 63-32 */
  77         u32     UcodeDataHigh;  /* Store microcode instruction bits 95-64 */
  78         u32     UcodeAddr;      /* Store microcode address - See flags below */
  79         u32     PadTo0x80[24];  /* Pad to Xcv configuration registers */
  80         u32     MacConfig0;     /* 0x80 - AXGMAC Configuration Register 0 */
  81         u32     MacConfig1;     /* 0x84 - AXGMAC Configuration Register 1 */
  82         u32     MacConfig2;     /* 0x88 - AXGMAC Configuration Register 2 */
  83         u32     MacConfig3;     /* 0x8C - AXGMAC Configuration Register 3 */
  84         u32     MacAddressLow;  /* 0x90 - AXGMAC MAC Station Address - octets 1-4 */
  85         u32     MacAddressHigh; /* 0x94 - AXGMAC MAC Station Address - octets 5-6 */
  86         u32     MacReserved1[2];        /* 0x98 - AXGMAC Reserved */
  87         u32     MacMaxFrameLen; /* 0xA0 - AXGMAC Maximum Frame Length */
  88         u32     MacReserved2[2];        /* 0xA4 - AXGMAC Reserved */
  89         u32     MacRevision;    /* 0xAC - AXGMAC Revision Level Register */
  90         u32     MacReserved3[4];        /* 0xB0 - AXGMAC Reserved */
  91         u32     MacAmiimCmd;    /* 0xC0 - AXGMAC AMIIM Command Register */
  92         u32     MacAmiimField;  /* 0xC4 - AXGMAC AMIIM Field Register */
  93         u32     MacAmiimConfig; /* 0xC8 - AXGMAC AMIIM Configuration Register */
  94         u32     MacAmiimLink;   /* 0xCC - AXGMAC AMIIM Link Fail Vector Register */
  95         u32     MacAmiimIndicator;      /* 0xD0 - AXGMAC AMIIM Indicator Registor */
  96         u32     PadTo0x100[11];         /* 0xD4 - 0x100 - Pad */
  97         u32     XmtConfig;      /* 0x100 - Transmit Configuration Register */
  98         u32     RcvConfig;      /* 0x104 - Receive Configuration Register 1 */
  99         u32     LinkAddress0Low;        /* 0x108 - Link address 0 */
 100         u32     LinkAddress0High;       /* 0x10C - Link address 0 */
 101         u32     LinkAddress1Low;        /* 0x110 - Link address 1 */
 102         u32     LinkAddress1High;       /* 0x114 - Link address 1 */
 103         u32     LinkAddress2Low;        /* 0x118 - Link address 2 */
 104         u32     LinkAddress2High;       /* 0x11C - Link address 2 */
 105         u32     LinkAddress3Low;        /* 0x120 - Link address 3 */
 106         u32     LinkAddress3High;       /* 0x124 - Link address 3 */
 107         u32     ToeplitzKey[10];        /* 0x128 - 0x150 - Toeplitz key */
 108         u32     SocketKey[10];          /* 0x150 - 0x178 - Socket Key */
 109         u32     LinkStatus;             /* 0x178 - Link status */
 110         u32     ClearStats;             /* 0x17C - Clear Stats */
 111         u32     XmtErrorsLow;           /* 0x180 - Transmit stats - errors */
 112         u32     XmtErrorsHigh;          /* 0x184 - Transmit stats - errors */
 113         u32     XmtFramesLow;   /* 0x188 - Transmit stats - frame count */
 114         u32     XmtFramesHigh;  /* 0x18C - Transmit stats - frame count */
 115         u32     XmtBytesLow;    /* 0x190 - Transmit stats - byte count */
 116         u32     XmtBytesHigh;   /* 0x194 - Transmit stats - byte count */
 117         u32     XmtTcpSegmentsLow;      /* 0x198 - Transmit stats - TCP segments */
 118         u32     XmtTcpSegmentsHigh;     /* 0x19C - Transmit stats - TCP segments */
 119         u32     XmtTcpBytesLow;         /* 0x1A0 - Transmit stats - TCP bytes */
 120         u32     XmtTcpBytesHigh;        /* 0x1A4 - Transmit stats - TCP bytes */
 121         u32     RcvErrorsLow;           /* 0x1A8 - Receive stats - errors */
 122         u32     RcvErrorsHigh;          /* 0x1AC - Receive stats - errors */
 123         u32     RcvFramesLow;           /* 0x1B0 - Receive stats - frame count */
 124         u32     RcvFramesHigh;          /* 0x1B4 - Receive stats - frame count */
 125         u32     RcvBytesLow;            /* 0x1B8 - Receive stats - byte count */
 126         u32     RcvBytesHigh;           /* 0x1BC - Receive stats - byte count */
 127         u32     RcvTcpSegmentsLow;      /* 0x1C0 - Receive stats - TCP segments */
 128         u32     RcvTcpSegmentsHigh;     /* 0x1C4 - Receive stats - TCP segments */
 129         u32     RcvTcpBytesLow;         /* 0x1C8 - Receive stats - TCP bytes */
 130         u32     RcvTcpBytesHigh;        /* 0x1CC - Receive stats - TCP bytes */
 131         u32     PadTo0x200[12];         /* 0x1D0 - 0x200 - Pad */
 132         u32     Software[1920];         /* 0x200 - 0x2000 - Software defined (not used) */
 133         u32     MsixTable[1024];        /* 0x2000 - 0x3000 - MSIX Table */
 134         u32     MsixBitArray[1024];     /* 0x3000 - 0x4000 - MSIX Pending Bit Array */
 135 };
 136 #pragma pack(pop)
 137
 138 /* Microcode Address Flags */
 139 #define MICROCODE_ADDRESS_GO            0x80000000      /* Start microcode */
 140 #define MICROCODE_ADDRESS_WRITE         0x40000000      /* Store microcode */
 141 #define MICROCODE_ADDRESS_READ          0x20000000      /* Read microcode */
 142 #define MICROCODE_ADDRESS_PARITY        0x10000000/* Parity error detected */
 143 #define MICROCODE_ADDRESS_MASK          0x00001FFF      /* Address bits */
 144
 145 /* Link Address Registers */
 146 /* Applied to link address high */
 147 #define LINK_ADDRESS_ENABLE     0x80000000
 148
 149 /* Microsoft register space size */
 150 #define SXG_UCODEREG_MEMSIZE    0x40000         /* 256k */
 151
 152 /*
 153  * Sahara microcode register address format.  The command code,
 154  * extended command code, and associated processor are encoded in
 155  * the address bits as follows
 156  */
 157 #define SXG_ADDRESS_CODE_SHIFT          2               /* Base command code */
 158 #define SXG_ADDRESS_CODE_MASK           0x0000003C
 159 /* Extended (or sub) command code */
 160 #define SXG_ADDRESS_EXCODE_SHIFT        6
 161 #define SXG_ADDRESS_EXCODE_MASK         0x00001FC0
 162 #define SXG_ADDRESS_CPUID_SHIFT         13              /* CPU */
 163 #define SXG_ADDRESS_CPUID_MASK          0x0003E000
 164 /* Used to sanity check UCODE_REGS structure */
 165 #define SXG_REGISTER_SIZE_PER_CPU       0x00002000
 166
 167 /* Sahara receive sequencer status values */
 168 #define SXG_RCV_STATUS_ATTN                     0x80000000 /* Attention */
 169 #define SXG_RCV_STATUS_TRANSPORT_MASK           0x3F000000 /* Transport mask */
 170 #define SXG_RCV_STATUS_TRANSPORT_ERROR          0x20000000 /* Transport error */
 171 /* Transport cksum error */
 172 #define SXG_RCV_STATUS_TRANSPORT_CSUM           0x23000000
 173 /* Transport underflow */
 174 #define SXG_RCV_STATUS_TRANSPORT_UFLOW          0x22000000
 175  /* Transport header length */
 176 #define SXG_RCV_STATUS_TRANSPORT_HDRLEN         0x20000000
 177 /* Transport flags detected */
 178 #define SXG_RCV_STATUS_TRANSPORT_FLAGS          0x10000000
 179  /* Transport options detected */
 180 #define SXG_RCV_STATUS_TRANSPORT_OPTS           0x08000000
 181 #define SXG_RCV_STATUS_TRANSPORT_SESS_MASK      0x07000000 /* Transport DDP */
 182 #define SXG_RCV_STATUS_TRANSPORT_DDP            0x06000000 /* Transport DDP */
 183 #define SXG_RCV_STATUS_TRANSPORT_iSCSI          0x05000000 /* Transport iSCSI */
 184 #define SXG_RCV_STATUS_TRANSPORT_NFS            0x04000000 /* Transport NFS */
 185 #define SXG_RCV_STATUS_TRANSPORT_FTP            0x03000000 /* Transport FTP */
 186 #define SXG_RCV_STATUS_TRANSPORT_HTTP           0x02000000 /* Transport HTTP */
 187 #define SXG_RCV_STATUS_TRANSPORT_SMB            0x01000000 /* Transport SMB */
 188 #define SXG_RCV_STATUS_NETWORK_MASK             0x00FF0000 /* Network mask */
 189 #define SXG_RCV_STATUS_NETWORK_ERROR            0x00800000 /* Network error */
 190 /* Network cksum error */
 191 #define SXG_RCV_STATUS_NETWORK_CSUM             0x00830000
 192 /* Network underflow error */
 193 #define SXG_RCV_STATUS_NETWORK_UFLOW            0x00820000
 194  /* Network header length */
 195 #define SXG_RCV_STATUS_NETWORK_HDRLEN           0x00800000
 196  /* Network overflow detected */
 197 #define SXG_RCV_STATUS_NETWORK_OFLOW            0x00400000
 198 /* Network multicast detected */
 199 #define SXG_RCV_STATUS_NETWORK_MCAST            0x00200000
 200 /* Network options detected */
 201 #define SXG_RCV_STATUS_NETWORK_OPTIONS          0x00100000
 202 /* Network offset detected */
 203 #define SXG_RCV_STATUS_NETWORK_OFFSET           0x00080000
 204 /* Network fragment detected */
 205 #define SXG_RCV_STATUS_NETWORK_FRAGMENT         0x00040000
 206 /* Network transport type mask */
 207 #define SXG_RCV_STATUS_NETWORK_TRANS_MASK       0x00030000
 208 #define SXG_RCV_STATUS_NETWORK_UDP              0x00020000 /* UDP */
 209 #define SXG_RCV_STATUS_NETWORK_TCP              0x00010000 /* TCP */
 210 #define SXG_RCV_STATUS_IPONLY                   0x00008000 /* IP-only not TCP */
 211 /* Receive priority */
 212 #define SXG_RCV_STATUS_PKT_PRI                  0x00006000
 213 /* Receive priority shift */
 214 #define SXG_RCV_STATUS_PKT_PRI_SHFT             13
 215 /* MAC Receive RAM parity error */
 216 #define SXG_RCV_STATUS_PARITY                   0x00001000
 217 /* Link address detection mask */
 218 #define SXG_RCV_STATUS_ADDRESS_MASK             0x00000F00
 219
 220 #define SXG_RCV_STATUS_ADDRESS_D                0x00000B00 /* Link address D */
 221 #define SXG_RCV_STATUS_ADDRESS_C                0x00000A00 /* Link address C */
 222 #define SXG_RCV_STATUS_ADDRESS_B                0x00000900 /* Link address B */
 223 #define SXG_RCV_STATUS_ADDRESS_A                0x00000800 /* Link address A */
 224 /* Link address broadcast */
 225 #define SXG_RCV_STATUS_ADDRESS_BCAST            0x00000300
 226  /* Link address multicast */
 227 #define SXG_RCV_STATUS_ADDRESS_MCAST            0x00000200
 228 /* Link control multicast */
 229 #define SXG_RCV_STATUS_ADDRESS_CMCAST           0x00000100
 230 /* Link status mask */
 231 #define SXG_RCV_STATUS_LINK_MASK                0x000000FF
 232 #define SXG_RCV_STATUS_LINK_ERROR               0x00000080 /* Link error */
 233 /* Link status mask */
 234 #define SXG_RCV_STATUS_LINK_MASK                0x000000FF
 235 /* RcvMacQ parity error */
 236 #define SXG_RCV_STATUS_LINK_PARITY              0x00000087
 237 #define SXG_RCV_STATUS_LINK_EARLY               0x00000086 /* Data early */
 238 #define SXG_RCV_STATUS_LINK_BUFOFLOW            0x00000085 /* Buffer overflow */
 239 #define SXG_RCV_STATUS_LINK_CODE                0x00000084 /* Link code error */
 240 #define SXG_RCV_STATUS_LINK_DRIBBLE             0x00000083 /* Dribble nibble */
 241 #define SXG_RCV_STATUS_LINK_CRC                 0x00000082 /* CRC error */
 242 #define SXG_RCV_STATUS_LINK_OFLOW               0x00000081 /* Link overflow */
 243 #define SXG_RCV_STATUS_LINK_UFLOW               0x00000080 /* Link underflow */
 244 #define SXG_RCV_STATUS_LINK_8023                0x00000020 /* 802.3 */
 245 #define SXG_RCV_STATUS_LINK_SNAP                0x00000010 /* Snap */
 246 #define SXG_RCV_STATUS_LINK_VLAN                0x00000008 /* VLAN */
 247 /* Network type mask */
 248 #define SXG_RCV_STATUS_LINK_TYPE_MASK           0x00000007
 249 #define SXG_RCV_STATUS_LINK_CONTROL             0x00000003 /* Control packet */
 250 #define SXG_RCV_STATUS_LINK_IPV6                0x00000002 /* IPv6 packet */
 251 #define SXG_RCV_STATUS_LINK_IPV4                0x00000001 /* IPv4 packet */
 252
 253 /* Sahara receive and transmit configuration registers */
 254 /* RcvConfig register reset */
 255 #define RCV_CONFIG_RESET                0x80000000
 256 /* Enable the receive logic */
 257 #define RCV_CONFIG_ENABLE               0x40000000
 258 /* Enable the receive parser */
 259 #define RCV_CONFIG_ENPARSE              0x20000000
 260 /* Enable the socket detector */
 261 #define RCV_CONFIG_SOCKET               0x10000000
 262 #define RCV_CONFIG_RCVBAD               0x08000000 /* Receive all bad frames */
 263 /* Receive all control frames */
 264 #define RCV_CONFIG_CONTROL              0x04000000
 265 /* Enable pause transmit when attn */
 266 #define RCV_CONFIG_RCVPAUSE             0x02000000
 267 /* Include TCP port w/ IPv6 toeplitz */
 268 #define RCV_CONFIG_TZIPV6               0x01000000
 269 /* Include TCP port w/ IPv4 toeplitz */
 270 #define RCV_CONFIG_TZIPV4               0x00800000
 271 #define RCV_CONFIG_FLUSH                0x00400000 /* Flush buffers */
 272 #define RCV_CONFIG_PRIORITY_MASK        0x00300000 /* Priority level */
 273 #define RCV_CONFIG_CONN_MASK            0x000C0000 /* Number of connections */
 274 #define RCV_CONFIG_CONN_4K              0x00000000 /* 4k connections */
 275 #define RCV_CONFIG_CONN_2K              0x00040000 /* 2k connections */
 276 #define RCV_CONFIG_CONN_1K              0x00080000 /* 1k connections */
 277 #define RCV_CONFIG_CONN_512             0x000C0000 /* 512 connections */
 278 #define RCV_CONFIG_HASH_MASK            0x00030000 /* Hash depth */
 279 #define RCV_CONFIG_HASH_8               0x00000000 /* Hash depth 8 */
 280 #define RCV_CONFIG_HASH_16              0x00010000 /* Hash depth 16 */
 281 #define RCV_CONFIG_HASH_4               0x00020000 /* Hash depth 4 */
 282 #define RCV_CONFIG_HASH_2               0x00030000 /* Hash depth 2 */
 283 /* Buffer length bits 15:4. ie multiple of 16. */
 284 #define RCV_CONFIG_BUFLEN_MASK          0x0000FFE0
 285 /* Disable socket detection on attn */
 286 #define RCV_CONFIG_SKT_DIS              0x00000008
 287 #define RCV_CONFIG_HIPRICTL     0x00000002 /* Ctrl frames on high-prioirty RcvQ */
 288 #define RCV_CONFIG_NEWSTATUSFMT 0x00000001 /* Use RevB status format */
 289 /*
 290  * Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
 291  * We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
 292  * and round up to nearest 32 byte boundary
 293  */
 294 #define RCV_CONFIG_BUFSIZE(_MaxFrame)                                   \
 295                 ((((_MaxFrame) + 22) + 31) & RCV_CONFIG_BUFLEN_MASK)
 296
 297 /* XmtConfig register reset */
 298 #define XMT_CONFIG_RESET                0x80000000
 299 #define XMT_CONFIG_ENABLE               0x40000000 /* Enable transmit logic */
 300 /* Inhibit MAC RAM parity error */
 301 #define XMT_CONFIG_MAC_PARITY           0x20000000
 302 /* Inhibit D2F buffer parity error */
 303 #define XMT_CONFIG_BUF_PARITY           0x10000000
 304 /* Inhibit 1T SRAM parity error */
 305 #define XMT_CONFIG_MEM_PARITY           0x08000000
 306 #define XMT_CONFIG_INVERT_PARITY        0x04000000 /* Invert MAC RAM parity */
 307 #define XMT_CONFIG_INITIAL_IPID         0x0000FFFF /* Initial IPID */
 308
 309 /*
 310  * A-XGMAC Registers - Occupy 0x80 - 0xD4 of the struct sxg_hw_regs
 311  *
 312  * Full register descriptions can be found in axgmac.pdf
 313  */
 314 /* A-XGMAC Configuration Register 0 */
 315 #define AXGMAC_CFG0_SUB_RESET           0x80000000 /* Sub module reset */
 316 #define AXGMAC_CFG0_RCNTRL_RESET        0x00400000 /* Receive control reset */
 317 #define AXGMAC_CFG0_RFUNC_RESET         0x00200000 /* Receive function reset */
 318 #define AXGMAC_CFG0_TCNTRL_RESET        0x00040000 /* Transmit control reset */
 319 #define AXGMAC_CFG0_TFUNC_RESET         0x00020000 /* Transmit function reset */
 320 #define AXGMAC_CFG0_MII_RESET           0x00010000 /* MII Management reset */
 321
 322 /* A-XGMAC Configuration Register 1 */
 323 /* Allow the sending of Pause frames */
 324 #define AXGMAC_CFG1_XMT_PAUSE           0x80000000
 325 #define AXGMAC_CFG1_XMT_EN              0x40000000 /* Enable transmit */
 326 /* Allow the detection of Pause frames */
 327 #define AXGMAC_CFG1_RCV_PAUSE           0x20000000
 328 #define AXGMAC_CFG1_RCV_EN              0x10000000 /* Enable receive */
 329 /* Current transmit state - READ ONLY */
 330 #define AXGMAC_CFG1_XMT_STATE           0x04000000
 331 /* Current receive state - READ ONLY */
 332 #define AXGMAC_CFG1_RCV_STATE           0x01000000
 333 /* Only pause for 64 slot on XOFF */
 334 #define AXGMAC_CFG1_XOFF_SHORT          0x00001000
 335 /* Delay transmit FCS 1 4-byte word */
 336 #define AXGMAC_CFG1_XMG_FCS1            0x00000400
 337 /* Delay transmit FCS 2 4-byte words */
 338 #define AXGMAC_CFG1_XMG_FCS2            0x00000800
 339 /* Delay transmit FCS 3 4-byte words */
 340 #define AXGMAC_CFG1_XMG_FCS3            0x00000C00
 341 /* Delay receive FCS 1 4-byte word */
 342 #define AXGMAC_CFG1_RCV_FCS1            0x00000100
 343 /* Delay receive FCS 2 4-byte words */
 344 #define AXGMAC_CFG1_RCV_FCS2            0x00000200
 345 /* Delay receive FCS 3 4-byte words */
 346 #define AXGMAC_CFG1_RCV_FCS3            0x00000300
 347 /* Per-packet override enable */
 348 #define AXGMAC_CFG1_PKT_OVERRIDE        0x00000080
 349 #define AXGMAC_CFG1_SWAP                0x00000040 /* Byte swap enable */
 350 /* ASSERT srdrpfrm on short frame (<64) */
 351 #define AXGMAC_CFG1_SHORT_ASSERT        0x00000020
 352 /* RCV only 802.3AE when CLEAR */
 353 #define AXGMAC_CFG1_RCV_STRICT          0x00000010
 354 #define AXGMAC_CFG1_CHECK_LEN           0x00000008 /* Verify frame length */
 355 #define AXGMAC_CFG1_GEN_FCS             0x00000004 /* Generate FCS */
 356 #define AXGMAC_CFG1_PAD_MASK            0x00000003 /* Mask for pad bits */
 357 #define AXGMAC_CFG1_PAD_64              0x00000001 /* Pad frames to 64 bytes */
 358 /* Detect VLAN and pad to 68 bytes */
 359 #define AXGMAC_CFG1_PAD_VLAN            0x00000002
 360 #define AXGMAC_CFG1_PAD_68              0x00000003 /* Pad to 68 bytes */
 361
 362 /* A-XGMAC Configuration Register 2 */
 363 /* Generate single pause frame (test) */
 364 #define AXGMAC_CFG2_GEN_PAUSE           0x80000000
 365 /* Manual link fault sequence */
 366 #define AXGMAC_CFG2_LF_MANUAL           0x08000000
 367 /* Auto link fault sequence */
 368 #define AXGMAC_CFG2_LF_AUTO             0x04000000
 369 /* Remote link fault (READ ONLY) */
 370 #define AXGMAC_CFG2_LF_REMOTE           0x02000000
 371 /* Local link fault (READ ONLY) */
 372 #define AXGMAC_CFG2_LF_LOCAL            0x01000000
 373 #define AXGMAC_CFG2_IPG_MASK            0x001F0000 /* Inter packet gap */
 374 #define AXGMAC_CFG2_IPG_SHIFT                   16
 375 #define AXGMAC_CFG2_PAUSE_XMT           0x00008000 /* Pause transmit module */
 376 /* Enable IPG extension algorithm */
 377 #define AXGMAC_CFG2_IPG_EXTEN           0x00000020
 378 #define AXGMAC_CFG2_IPGEX_MASK          0x0000001F /* IPG extension */
 379
 380 /* A-XGMAC Configuration Register 3 */
 381 /* Receive frame drop filter */
 382 #define AXGMAC_CFG3_RCV_DROP            0xFFFF0000
 383 /* Receive frame don't care filter */
 384 #define AXGMAC_CFG3_RCV_DONT_CARE       0x0000FFFF
 385
 386 /* A-XGMAC Station Address Register - Octets 1-4 */
 387 #define AXGMAC_SARLOW_OCTET_ONE         0xFF000000      /* First octet */
 388 #define AXGMAC_SARLOW_OCTET_TWO         0x00FF0000      /* Second octet */
 389 #define AXGMAC_SARLOW_OCTET_THREE       0x0000FF00      /* Third octet */
 390 #define AXGMAC_SARLOW_OCTET_FOUR        0x000000FF      /* Fourth octet */
 391
 392 /* A-XGMAC Station Address Register - Octets 5-6 */
 393 #define AXGMAC_SARHIGH_OCTET_FIVE       0xFF000000      /* Fifth octet */
 394 #define AXGMAC_SARHIGH_OCTET_SIX        0x00FF0000      /* Sixth octet */
 395
 396 /* A-XGMAC Maximum frame length register */
 397 /* Maximum transmit frame length */
 398 #define AXGMAC_MAXFRAME_XMT             0x3FFF0000
 399 #define AXGMAC_MAXFRAME_XMT_SHIFT       16
 400 /* Maximum receive frame length */
 401 #define AXGMAC_MAXFRAME_RCV             0x0000FFFF
 402 /*
 403  * This register doesn't need to be written for standard MTU.
 404  * For jumbo, I'll just statically define the value here.  This
 405  * value sets the receive byte count to 9036 (0x234C) and the
 406  * transmit WORD count to 2259 (0x8D3).  These values include 22
 407  * bytes of padding beyond the jumbo MTU of 9014
 408  */
 409 #define AXGMAC_MAXFRAME_JUMBO           0x08D3234C
 410
 411 /* A-XGMAC Revision level */
 412 #define AXGMAC_REVISION_MASK            0x0000FFFF      /* Revision level */
 413
 414 /* A-XGMAC AMIIM Command Register */
 415 #define AXGMAC_AMIIM_CMD_START          0x00000008      /* Command start */
 416 #define AXGMAC_AMIIM_CMD_MASK           0x00000007      /* Command */
 417 /* 10/100/1000 Mbps Phy Write */
 418 #define AXGMAC_AMIIM_CMD_LEGACY_WRITE           1
 419 /* 10/100/1000 Mbps Phy Read */
 420 #define AXGMAC_AMIIM_CMD_LEGACY_READ            2
 421 #define AXGMAC_AMIIM_CMD_MONITOR_SINGLE         3       /* Monitor single PHY */
 422 /* Monitor multiple contiguous PHYs */
 423 #define AXGMAC_AMIIM_CMD_MONITOR_MULTIPLE       4
 424 /* Present AMIIM Field Reg */
 425 #define AXGMAC_AMIIM_CMD_10G_OPERATION          5
 426 /* Clear Link Fail Bit in MIIM */
 427 #define AXGMAC_AMIIM_CMD_CLEAR_LINK_FAIL        6
 428
 429 /* A-XGMAC AMIIM Field Register */
 430 #define AXGMAC_AMIIM_FIELD_ST           0xC0000000      /* 2-bit ST field */
 431 #define AXGMAC_AMIIM_FIELD_ST_SHIFT             30
 432 #define AXGMAC_AMIIM_FIELD_OP           0x30000000      /* 2-bit OP field */
 433 #define AXGMAC_AMIIM_FIELD_OP_SHIFT             28
 434 /* Port address field (hstphyadx in spec) */
 435 #define AXGMAC_AMIIM_FIELD_PORT_ADDR    0x0F800000
 436 #define AXGMAC_AMIIM_FIELD_PORT_SHIFT           23
 437 /* Device address field (hstregadx in spec) */
 438 #define AXGMAC_AMIIM_FIELD_DEV_ADDR     0x007C0000
 439 #define AXGMAC_AMIIM_FIELD_DEV_SHIFT            18
 440 #define AXGMAC_AMIIM_FIELD_TA           0x00030000      /* 2-bit TA field */
 441 #define AXGMAC_AMIIM_FIELD_TA_SHIFT             16
 442 #define AXGMAC_AMIIM_FIELD_DATA         0x0000FFFF      /* Data field */
 443
 444 /* Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register */
 445 #define MIIM_OP_ADDR            0       /* MIIM Address set operation */
 446 #define MIIM_OP_WRITE           1       /* MIIM Write register operation */
 447 #define MIIM_OP_READ            2       /* MIIM Read register operation */
 448 #define MIIM_OP_ADDR_SHIFT      (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT)
 449
 450 /*
 451  * Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM
 452  * Field Register
 453  */
 454 #define MIIM_PORT_NUM           1       /* All Sahara MIIM modules use port 1 */
 455
 456 /*
 457  * Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM
 458  * Field Register
 459  */
 460 /* PHY PMA/PMD module MIIM device number */
 461 #define MIIM_DEV_PHY_PMA        1
 462 /* PHY PCS module MIIM device number */
 463 #define MIIM_DEV_PHY_PCS        3
 464 /* PHY XS module MIIM device number */
 465 #define MIIM_DEV_PHY_XS         4
 466 #define MIIM_DEV_XGXS           5       /* XGXS MIIM device number */
 467
 468 /*
 469  * Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field
 470  * Register
 471  */
 472 #define MIIM_TA_10GB            2       /* set to 2 for 10 GB operation */
 473
 474 /* A-XGMAC AMIIM Configuration Register */
 475 /* Bypass preamble of mngmt frame */
 476 #define AXGMAC_AMIIM_CFG_NOPREAM        0x00000080
 477 /* half-clock duration of MDC output */
 478 #define AXGMAC_AMIIM_CFG_HALF_CLOCK     0x0000007F
 479
 480 /* A-XGMAC AMIIM Indicator Register */
 481 /* Link status from legacy PHY or MMD */
 482 #define AXGMAC_AMIIM_INDC_LINK          0x00000010
 483 /* Multiple phy operation in progress */
 484 #define AXGMAC_AMIIM_INDC_MPHY          0x00000008
 485 /* Single phy operation in progress */
 486 #define AXGMAC_AMIIM_INDC_SPHY          0x00000004
 487 /* Single or multiple monitor cmd */
 488 #define AXGMAC_AMIIM_INDC_MON           0x00000002
 489 /* Set until cmd operation complete */
 490 #define AXGMAC_AMIIM_INDC_BUSY          0x00000001
 491
 492 /* Link Status and Control Register */
 493 #define LS_PHY_CLR_RESET        0x80000000      /* Clear reset signal to PHY */
 494 #define LS_SERDES_POWER_DOWN    0x40000000      /* Power down the Sahara Serdes */
 495 #define LS_XGXS_ENABLE          0x20000000      /* Enable the XAUI XGXS logic */
 496 /* Hold XAUI XGXS logic reset until Serdes is up */
 497 #define LS_XGXS_CTL             0x10000000
 498 /* When 0, XAUI Serdes is up and initialization is complete */
 499 #define LS_SERDES_DOWN          0x08000000
 500 /* When 0, Trace Serdes is up and initialization is complete */
 501 #define LS_TRACE_DOWN           0x04000000
 502 /* Set PHY clock to 25 MHz (else 156.125 MHz) */
 503 #define LS_PHY_CLK_25MHZ        0x02000000
 504 #define LS_PHY_CLK_EN           0x01000000      /* Enable clock to PHY */
 505 #define LS_XAUI_LINK_UP         0x00000010      /* XAUI link is up */
 506 /* XAUI link status has changed */
 507 #define LS_XAUI_LINK_CHNG       0x00000008
 508 #define LS_LINK_ALARM           0x00000004      /* Link alarm pin */
 509 /* Mask link attention control bits */
 510 #define LS_ATTN_CTRL_MASK       0x00000003
 511 #define LS_ATTN_ALARM           0x00000000      /* 00 => Attn on link alarm */
 512 /* 01 => Attn on link alarm or status change */
 513 #define LS_ATTN_ALARM_OR_STAT_CHNG      0x00000001
 514 /* 10 => Attn on link status change */
 515 #define LS_ATTN_STAT_CHNG       0x00000002
 516 #define LS_ATTN_NONE            0x00000003      /* 11 => no Attn */
 517
 518 /* Link Address High Registers */
 519 #define LINK_ADDR_ENABLE        0x80000000      /* Enable this link address */
 520
 521
 522 /*
 523  * XGXS XAUI XGMII Extender registers
 524  *
 525  * Full register descriptions can be found in mxgxs.pdf
 526  */
 527 /* XGXS Register Map */
 528 #define XGXS_ADDRESS_CONTROL1   0x0000          /* XS Control 1 */
 529 #define XGXS_ADDRESS_STATUS1    0x0001          /* XS Status 1 */
 530 #define XGXS_ADDRESS_DEVID_LOW  0x0002          /* XS Device ID (low) */
 531 #define XGXS_ADDRESS_DEVID_HIGH 0x0003          /* XS Device ID (high) */
 532 #define XGXS_ADDRESS_SPEED      0x0004          /* XS Speed ability */
 533 #define XGXS_ADDRESS_DEV_LOW    0x0005          /* XS Devices in package */
 534 #define XGXS_ADDRESS_DEV_HIGH   0x0006          /* XS Devices in package */
 535 #define XGXS_ADDRESS_STATUS2    0x0008          /* XS Status 2 */
 536 #define XGXS_ADDRESS_PKGID_lOW  0x000E          /* XS Package Identifier */
 537 #define XGXS_ADDRESS_PKGID_HIGH 0x000F          /* XS Package Identifier */
 538 #define XGXS_ADDRESS_LANE_STATUS        0x0018  /* 10G XGXS Lane Status */
 539 #define XGXS_ADDRESS_TEST_CTRL  0x0019          /* 10G XGXS Test Control */
 540 #define XGXS_ADDRESS_RESET_LO1  0x8000          /* Vendor-Specific Reset Lo 1 */
 541 #define XGXS_ADDRESS_RESET_LO2  0x8001          /* Vendor-Specific Reset Lo 2 */
 542 #define XGXS_ADDRESS_RESET_HI1  0x8002          /* Vendor-Specific Reset Hi 1 */
 543 #define XGXS_ADDRESS_RESET_HI2  0x8003          /* Vendor-Specific Reset Hi 2 */
 544
 545 /* XS Control 1 register bit definitions */
 546 #define XGXS_CONTROL1_RESET     0x8000          /* Reset - self clearing */
 547 #define XGXS_CONTROL1_LOOPBACK  0x4000          /* Enable loopback */
 548 #define XGXS_CONTROL1_SPEED1    0x2000          /* 0 = unspecified, 1 = 10Gb+ */
 549 #define XGXS_CONTROL1_LOWPOWER  0x0400          /* 1 = Low power mode */
 550 #define XGXS_CONTROL1_SPEED2    0x0040          /* Same as SPEED1 (?) */
 551 /* Everything reserved except zero (?) */
 552 #define XGXS_CONTROL1_SPEED     0x003C
 553
 554 /* XS Status 1 register bit definitions */
 555 #define XGXS_STATUS1_FAULT      0x0080          /* Fault detected */
 556 #define XGXS_STATUS1_LINK       0x0004          /* 1 = Link up */
 557 #define XGXS_STATUS1_LOWPOWER   0x0002          /* 1 = Low power supported */
 558
 559 /* XS Speed register bit definitions */
 560 #define XGXS_SPEED_10G          0x0001          /* 1 = 10G capable */
 561
 562 /* XS Devices register bit definitions */
 563 #define XGXS_DEVICES_DTE        0x0020          /* DTE XS Present */
 564 #define XGXS_DEVICES_PHY        0x0010          /* PHY XS Present */
 565 #define XGXS_DEVICES_PCS        0x0008          /* PCS Present */
 566 #define XGXS_DEVICES_WIS        0x0004          /* WIS Present */
 567 #define XGXS_DEVICES_PMD        0x0002          /* PMD/PMA Present */
 568 #define XGXS_DEVICES_CLAUSE22   0x0001          /* Clause 22 registers present*/
 569
 570 /* XS Devices High register bit definitions */
 571 #define XGXS_DEVICES_VENDOR2    0x8000          /* Vendor specific device 2 */
 572 #define XGXS_DEVICES_VENDOR1    0x4000          /* Vendor specific device 1 */
 573
 574 /* XS Status 2 register bit definitions */
 575 #define XGXS_STATUS2_DEV_MASK   0xC000          /* Device present mask */
 576 #define XGXS_STATUS2_DEV_RESPOND        0x8000  /* Device responding */
 577 #define XGXS_STATUS2_XMT_FAULT  0x0800          /* Transmit fault */
 578 #define XGXS_STATUS2_RCV_FAULT  0x0400          /* Receive fault */
 579
 580 /* XS Package ID High register bit definitions */
 581 #define XGXS_PKGID_HIGH_ORG     0xFC00          /* Organizationally Unique */
 582 #define XGXS_PKGID_HIGH_MFG     0x03F0          /* Manufacturer Model */
 583 #define XGXS_PKGID_HIGH_REV     0x000F          /* Revision Number */
 584
 585 /* XS Lane Status register bit definitions */
 586 #define XGXS_LANE_PHY           0x1000  /* PHY/DTE lane alignment status */
 587 #define XGXS_LANE_PATTERN       0x0800          /* Pattern testing ability */
 588 #define XGXS_LANE_LOOPBACK      0x0400          /* PHY loopback ability */
 589 #define XGXS_LANE_SYNC3         0x0008          /* Lane 3 sync */
 590 #define XGXS_LANE_SYNC2         0x0004          /* Lane 2 sync */
 591 #define XGXS_LANE_SYNC1         0x0002          /* Lane 1 sync */
 592 #define XGXS_LANE_SYNC0         0x0001          /* Lane 0 sync */
 593
 594 /* XS Test Control register bit definitions */
 595 #define XGXS_TEST_PATTERN_ENABLE        0x0004  /* Test pattern enabled */
 596 #define XGXS_TEST_PATTERN_MASK  0x0003          /* Test patterns */
 597 #define XGXS_TEST_PATTERN_RSVD  0x0003          /* Test pattern - reserved */
 598 #define XGXS_TEST_PATTERN_MIX   0x0002          /* Test pattern - mixed */
 599 #define XGXS_TEST_PATTERN_LOW   0x0001          /* Test pattern - low */
 600 #define XGXS_TEST_PATTERN_HIGH  0x0001          /* Test pattern - high */
 601
 602 /*
 603  * External MDIO Bus Registers
 604  *
 605  * Full register descriptions can be found in PHY/XENPAK/IEEE specs
 606  */
 607 /*
 608  * LASI (Link Alarm Status Interrupt) Registers (located in
 609  * MIIM_DEV_PHY_PMA device)
 610  */
 611 #define LASI_RX_ALARM_CONTROL   0x9000          /* LASI RX_ALARM Control */
 612 #define LASI_TX_ALARM_CONTROL   0x9001          /* LASI TX_ALARM Control */
 613 #define LASI_CONTROL            0x9002          /* LASI Control */
 614 #define LASI_RX_ALARM_STATUS    0x9003          /* LASI RX_ALARM Status */
 615 #define LASI_TX_ALARM_STATUS    0x9004          /* LASI TX_ALARM Status */
 616 #define LASI_STATUS             0x9005          /* LASI Status */
 617
 618 /* LASI_CONTROL bit definitions */
 619 /* Enable RX_ALARM interrupts */
 620 #define LASI_CTL_RX_ALARM_ENABLE        0x0004
 621 /* Enable TX_ALARM interrupts */
 622 #define LASI_CTL_TX_ALARM_ENABLE        0x0002
 623 /* Enable Link Status interrupts */
 624 #define LASI_CTL_LS_ALARM_ENABLE        0x0001
 625
 626 /* LASI_STATUS bit definitions */
 627 #define LASI_STATUS_RX_ALARM    0x0004          /* RX_ALARM status */
 628 #define LASI_STATUS_TX_ALARM    0x0002          /* TX_ALARM status */
 629 #define LASI_STATUS_LS_ALARM    0x0001          /* Link Status */
 630
 631 /* PHY registers - PMA/PMD (device 1) */
 632 #define PHY_PMA_CONTROL1        0x0000          /* PMA/PMD Control 1 */
 633 #define PHY_PMA_STATUS1         0x0001          /* PMA/PMD Status 1 */
 634 #define PHY_PMA_RCV_DET         0x000A  /* PMA/PMD Receive Signal Detect */
 635                 /* other PMA/PMD registers exist and can be defined as needed */
 636
 637 /* PHY registers - PCS (device 3) */
 638 #define PHY_PCS_CONTROL1        0x0000          /* PCS Control 1 */
 639 #define PHY_PCS_STATUS1         0x0001          /* PCS Status 1 */
 640 #define PHY_PCS_10G_STATUS1     0x0020          /* PCS 10GBASE-R Status 1 */
 641                 /* other PCS registers exist and can be defined as needed */
 642
 643 /* PHY registers - XS (device 4) */
 644 #define PHY_XS_CONTROL1         0x0000          /* XS Control 1 */
 645 #define PHY_XS_STATUS1          0x0001          /* XS Status 1 */
 646 #define PHY_XS_LANE_STATUS      0x0018          /* XS Lane Status */
 647                 /* other XS registers exist and can be defined as needed */
 648
 649 /* PHY_PMA_CONTROL1 register bit definitions */
 650 #define PMA_CONTROL1_RESET      0x8000          /* PMA/PMD reset */
 651
 652 /* PHY_PMA_RCV_DET register bit definitions */
 653 #define PMA_RCV_DETECT          0x0001  /* PMA/PMD receive signal detect */
 654
 655 /* PHY_PCS_10G_STATUS1 register bit definitions */
 656 #define PCS_10B_BLOCK_LOCK      0x0001  /* PCS 10GBASE-R locked to receive blocks */
 657
 658 /* PHY_XS_LANE_STATUS register bit definitions */
 659 #define XS_LANE_ALIGN           0x1000          /* XS transmit lanes aligned */
 660
 661 #define XCVR_VENDOR_LEN         16  /* xcvr vendor len */
 662 #define XCVR_MODEL_LEN          16  /* xcvr model len */
 663
 664 /* PHY Microcode download data structure */
 665 struct phy_ucode {
 666         ushort  Addr;
 667         ushort  Data;
 668 };
 669
 670 /* Slow Bus Register Definitions */
 671
 672 /* Module 0 registers */
 673 #define GPIO_L_IN               0x15            /* GPIO input (low) */
 674 #define GPIO_L_OUT              0x16            /* GPIO output (low) */
 675 #define GPIO_L_DIR              0x17            /* GPIO direction (low) */
 676 #define GPIO_H_IN               0x19            /* GPIO input (high) */
 677 #define GPIO_H_OUT              0x1A            /* GPIO output (high) */
 678 #define GPIO_H_DIR              0x1B            /* GPIO direction (high) */
 679
 680 /* Definitions for other slow bus registers can be added as needed */
 681
 682
 683 /*
 684  * Transmit Sequencer Command Descriptor definitions
 685  *
 686  * This descriptor must be placed in GRAM.  The address of this descriptor
 687  * (along with a couple of control bits) is pushed onto the PxhCmdQ or PxlCmdQ
 688  * (Proxy high or low command queue).  This data is read by the Proxy Sequencer,
 689  * which pushes it onto the XmtCmdQ, which is (eventually) read by the Transmit
 690  * Sequencer, causing a packet to be transmitted.  Not all fields are valid for
 691  * all commands - see the Sahara spec for details.  Note that this structure is
 692  * only valid when compiled on a little endian machine.
 693  */
 694 #pragma pack(push, 1)
 695 struct xmt_desc {
 696         ushort          XmtLen;     /* word 0, bits [15:0] -  transmit length */
 697         /* word 0, bits [23:16] - transmit control byte */
 698         unsigned char   XmtCtl;
 699         /* word 0, bits [31:24] - transmit command plus misc. */
 700         unsigned char   Cmd;
 701         /* word 1, bits [31:0] -  transmit buffer ID */
 702         u32     XmtBufId;
 703         /* word 2, bits [7:0] -   byte address of TCP header */
 704         unsigned char   TcpStrt;
 705         /* word 2, bits [15:8] -  byte address of IP header */
 706         unsigned char   IpStrt;
 707         /* word 2, bits [31:16] - partial IP checksum */
 708         ushort  IpCkSum;
 709         /* word 3, bits [15:0] -  partial TCP checksum */
 710         ushort  TcpCkSum;
 711         ushort  Rsvd1;              /* word 3, bits [31:16] - PAD */
 712         u32     Rsvd2;              /* word 4, bits [31:0] -  PAD */
 713         u32     Rsvd3;              /* word 5, bits [31:0] -  PAD */
 714         u32     Rsvd4;              /* word 6, bits [31:0] -  PAD */
 715         u32     Rsvd5;              /* word 7, bits [31:0] -  PAD */
 716 };
 717 #pragma pack(pop)
 718
 719 /* struct xmt_desc Cmd byte definitions */
 720                 /* command codes */
 721 #define XMT_DESC_CMD_RAW_SEND           0       /* raw send descriptor */
 722 #define XMT_DESC_CMD_CSUM_INSERT        1       /* checksum insert descriptor */
 723 #define XMT_DESC_CMD_FORMAT             2       /* format descriptor */
 724 #define XMT_DESC_CMD_PRIME              3       /* prime descriptor */
 725 /* comand code shift (shift to bits [31:30] in word 0) */
 726 #define XMT_DESC_CMD_CODE_SHFT          6
 727                 /* shifted command codes */
 728 #define XMT_RAW_SEND    (XMT_DESC_CMD_RAW_SEND    << XMT_DESC_CMD_CODE_SHFT)
 729 #define XMT_CSUM_INSERT (XMT_DESC_CMD_CSUM_INSERT << XMT_DESC_CMD_CODE_SHFT)
 730 #define XMT_FORMAT      (XMT_DESC_CMD_FORMAT      << XMT_DESC_CMD_CODE_SHFT)
 731 #define XMT_PRIME       (XMT_DESC_CMD_PRIME       << XMT_DESC_CMD_CODE_SHFT)
 732
 733 /*
 734  * struct xmt_desc Control Byte (XmtCtl) definitions
 735  * NOTE:  These bits do not work on Sahara (Rev A)!
 736  */
 737 /* current frame is a pause control frame (for statistics) */
 738 #define XMT_CTL_PAUSE_FRAME             0x80
 739 /* current frame is a control frame (for statistics) */
 740 #define XMT_CTL_CONTROL_FRAME           0x40
 741 #define XMT_CTL_PER_PKT_QUAL            0x20    /* per packet qualifier */
 742 #define XMT_CTL_PAD_MODE_NONE           0x00    /* do not pad frame */
 743 #define XMT_CTL_PAD_MODE_64             0x08    /* pad frame to 64 bytes */
 744 /* pad frame to 64 bytes, and VLAN frames to 68 bytes */
 745 #define XMT_CTL_PAD_MODE_VLAN_68        0x10
 746 #define XMT_CTL_PAD_MODE_68             0x18    /* pad frame to 68 bytes */
 747 /* generate FCS (CRC) for this frame */
 748 #define XMT_CTL_GEN_FCS                 0x04
 749 #define XMT_CTL_DELAY_FCS_0             0x00    /* do not delay FCS calcution */
 750 /* delay FCS calculation by 1 (4-byte) word */
 751 #define XMT_CTL_DELAY_FCS_1             0x01
 752 /* delay FCS calculation by 2 (4-byte) words */
 753 #define XMT_CTL_DELAY_FCS_2             0x02
 754 /* delay FCS calculation by 3 (4-byte) words */
 755 #define XMT_CTL_DELAY_FCS_3             0x03
 756
 757 /* struct xmt_desc XmtBufId definition */
 758 /*
 759  * The Xmt buffer ID is formed by dividing the buffer (DRAM) address
 760  * by 256 (or << 8)
 761  */
 762
 763 #define XMT_BUF_ID_SHFT         8
 764
 765 /* Receiver Sequencer Definitions */
 766
 767 /* Receive Event Queue (queues 3 - 6) bit definitions */
 768 /* bit mask for the Receive Buffer ID */
 769 #define RCV_EVTQ_RBFID_MASK     0x0000FFFF
 770
 771 /* Receive Buffer ID definition */
 772 /*
 773  * The Rcv buffer ID is formed by dividing the buffer (DRAM) address
 774  * by 32 (or << 5)
 775  */
 776 #define RCV_BUF_ID_SHFT         5
 777
 778 /*
 779  * Format of the 18 byte Receive Buffer returned by the
 780  * Receive Sequencer for received packets
 781  */
 782 #pragma pack(push, 1)
 783 struct rcv_buf_hdr {
 784         u32     Status;         /* Status word from Rcv Seq Parser */
 785         ushort  Length;         /* Rcv packet byte count */
 786         union {
 787                 ushort          TcpCsum;        /* TCP checksum */
 788                 struct {
 789                         /* lower 8 bits of the TCP checksum */
 790                         unsigned char   TcpCsumL;
 791                         /* Link hash (multicast frames only) */
 792                         unsigned char   LinkHash;
 793                 };
 794         };
 795         ushort  SktHash;                /* Socket hash */
 796         unsigned char   TcpHdrOffset;   /* TCP header offset into packet */
 797         unsigned char   IpHdrOffset;    /* IP header offset into packet */
 798         u32             TpzHash;        /* Toeplitz hash */
 799         ushort          Reserved;       /* Reserved */
 800 };
 801 #pragma pack(pop)
 802
 803 /* Queue definitions */
 804
 805 /* Ingress (read only) queue numbers */
 806 #define PXY_BUF_Q       0       /* Proxy Buffer Queue */
 807 #define HST_EVT_Q       1       /* Host Event Queue */
 808 #define XMT_BUF_Q       2       /* Transmit Buffer Queue */
 809 #define SKT_EVL_Q       3       /* RcvSqr Socket Event Low Priority Queue */
 810 #define RCV_EVL_Q       4       /* RcvSqr Rcv Event Low Priority Queue */
 811 #define SKT_EVH_Q       5       /* RcvSqr Socket Event High Priority Queue */
 812 #define RCV_EVH_Q       6       /* RcvSqr Rcv Event High Priority Queue */
 813 #define DMA_RSP_Q       7       /* Dma Response Queue - one per CPU context */
 814 /* Local (read/write) queue numbers */
 815 #define LOCAL_A_Q       8       /* Spare local Queue */
 816 #define LOCAL_B_Q       9       /* Spare local Queue */
 817 #define LOCAL_C_Q       10      /* Spare local Queue */
 818 #define FSM_EVT_Q       11      /* Finite-State-Machine Event Queue */
 819 #define SBF_PAL_Q       12      /* System Buffer Physical Address (low) Queue */
 820 #define SBF_PAH_Q       13      /* System Buffer Physical Address (high) Queue*/
 821 #define SBF_VAL_Q       14      /* System Buffer Virtual Address (low) Queue */
 822 #define SBF_VAH_Q       15      /* System Buffer Virtual Address (high) Queue */
 823 /* Egress (write only) queue numbers */
 824 #define H2G_CMD_Q       16      /* Host to GlbRam DMA Command Queue */
 825 #define H2D_CMD_Q       17      /* Host to DRAM DMA Command Queue */
 826 #define G2H_CMD_Q       18      /* GlbRam to Host DMA Command Queue */
 827 #define G2D_CMD_Q       19      /* GlbRam to DRAM DMA Command Queue */
 828 #define D2H_CMD_Q       20      /* DRAM to Host DMA Command Queue */
 829 #define D2G_CMD_Q       21      /* DRAM to GlbRam DMA Command Queue */
 830 #define D2D_CMD_Q       22      /* DRAM to DRAM DMA Command Queue */
 831 #define PXL_CMD_Q       23      /* Low Priority Proxy Command Queue */
 832 #define PXH_CMD_Q       24      /* High Priority Proxy Command Queue */
 833 #define RSQ_CMD_Q       25      /* Receive Sequencer Command Queue */
 834 #define RCV_BUF_Q       26      /* Receive Buffer Queue */
 835
 836 /* Bit definitions for the Proxy Command queues (PXL_CMD_Q and PXH_CMD_Q) */
 837 /* enable copy of xmt descriptor to xmt command queue */
 838 #define PXY_COPY_EN     0x00200000
 839 #define PXY_SIZE_16     0x00000000      /* copy 16 bytes */
 840 #define PXY_SIZE_32     0x00100000      /* copy 32 bytes */
 841
 842 /* SXG EEPROM/Flash Configuration Definitions */
 843
 844 /* Location of configuration data in EEPROM or Flash */
 845 /* start addr for config info in EEPROM */
 846 #define EEPROM_CONFIG_START_ADDR        0x00
 847 /* start addr for config info in Flash */
 848 #define FLASH_CONFIG_START_ADDR         0x80
 849
 850 /* Configuration data section defines */
 851 #define HW_CFG_SECTION_SIZE     512     /* size of H/W section */
 852 #define HW_CFG_SECTION_SIZE_A   256     /* size of H/W section (Sahara rev A) */
 853 /* starting location (offset) of S/W section */
 854 #define SW_CFG_SECTION_START    512
 855 /* starting location (offset) of S/W section (Sahara rev A) */
 856 #define SW_CFG_SECTION_START_A  256
 857 #define SW_CFG_SECTION_SIZE     128     /* size of S/W section */
 858 /*
 859  * H/W configuration data magic word Goes in Addr field of first
 860  * struct hw_cfg_data entry
 861  */
 862 #define HW_CFG_MAGIC_WORD       0xA5A5
 863 /*
 864  * H/W configuration data terminator  Goes in Addr field of last
 865  * struct hw_cfg_data entry
 866  */
 867 #define HW_CFG_TERMINATOR       0xFFFF
 868
 869 #define SW_CFG_MAGIC_WORD       0x5A5A  /* S/W configuration data magic word */
 870
 871 #pragma pack(push, 1)
 872 /*
 873  * Structure for an element of H/W configuration data.
 874  * Read by the Sahara hardware
 875  */
 876 struct hw_cfg_data {
 877         ushort  Addr;
 878         ushort  Data;
 879 };
 880
 881 /*
 882  * Number of struct hw_cfg_data structures to put in the configuration data
 883  * data structure (struct sxg_config or struct sxg_config_a).  The number is
 884  * computed to fill the entire H/W config section of the structure.
 885  */
 886 #define NUM_HW_CFG_ENTRIES                                              \
 887                         (HW_CFG_SECTION_SIZE / sizeof(struct hw_cfg_data))
 888 #define NUM_HW_CFG_ENTRIES_A                                            \
 889                         (HW_CFG_SECTION_SIZE_A / sizeof(struct hw_cfg_data))
 890
 891 /* MAC address structure */
 892 struct sxg_config_mac {
 893         unsigned char   MacAddr[6];     /* MAC Address */
 894 };
 895
 896 /* FRU data structure */
 897 struct atk_fru {
 898         unsigned char           PartNum[6];
 899         unsigned char           Revision[2];
 900         unsigned char           Serial[14];
 901 };
 902
 903 /* OEM FRU Format types */
 904 #define ATK_FRU_FORMAT          0x0000
 905 #define CPQ_FRU_FORMAT          0x0001
 906 #define DELL_FRU_FORMAT         0x0002
 907 #define HP_FRU_FORMAT           0x0003
 908 #define IBM_FRU_FORMAT          0x0004
 909 #define EMC_FRU_FORMAT          0x0005
 910 #define NO_FRU_FORMAT           0xFFFF
 911
 912 #define ATK_OEM_ASSY_SIZE       10      /* assy num is 9 chars plus \0 */
 913
 914 /* OEM FRU structure for Alacritech */
 915 struct atk_oem {
 916         unsigned char Assy[ATK_OEM_ASSY_SIZE];
 917 };
 918
 919 #define OEM_EEPROM_FRUSIZE      74      /* size of OEM fru info - size */
 920 /* chosen to fill out the S/W section */
 921
 922 union oem_fru {                 /* OEM FRU information */
 923         unsigned char OemFru[OEM_EEPROM_FRUSIZE];
 924         struct atk_oem AtkOem;
 925 };
 926
 927 /* Structure to hold the S/W configuration data. */
 928 struct sw_cfg_data {
 929         ushort                  MagicWord;      /* Magic word for section 2 */
 930         ushort                  Version;        /* Format version */
 931         struct sxg_config_mac   MacAddr[4];     /* space for 4 MAC addresses */
 932         struct atk_fru          AtkFru;         /* FRU information */
 933         ushort                  OemFruFormat;   /* OEM FRU format type */
 934         union oem_fru           OemFru;         /* OEM FRU information */
 935         ushort                  Checksum;       /* Checksum of section 2 */
 936 };
 937
 938
 939 /* EEPROM/Flash Format */
 940 struct sxg_config {
 941         /* H/W Section - Read by Sahara hardware (512 bytes) */
 942         struct hw_cfg_data              HwCfg[NUM_HW_CFG_ENTRIES];
 943         /* S/W Section - Other configuration data (128 bytes) */
 944         struct sw_cfg_data      SwCfg;
 945 };
 946
 947 #ifdef WINDOWS_COMPILER
 948 /*
 949  *  The following macro is something of a kludge, but it is the only way
 950  * that I could find to catch certain programming errors at compile time.
 951  * If the asserted condition is true, then nothing happens.  If false, then
 952  * the compiler tries to typedef an array with -1 members, which generates
 953  * an error.  Unfortunately, the error message is meaningless, but at least
 954  * it catches the problem.  This macro would be unnecessary if the compiler
 955  * allowed the sizeof and offsetof macros to be used in the #if directive.
 956  */
 957 #define compile_time_assert(cond) \
 958     typedef char comp_error[(cond) ? 1 : -1]
 959
 960 /*
 961  * A compiler error on either of the next two lines indicates that the struct sxg_config
 962  * structure was built incorrectly.  Unfortunately, the error message produced
 963  * is meaningless.  But this is apparently the only way to catch this problem
 964  * at compile time.
 965  */
 966 compile_time_assert (offsetof(struct sxg_config, SwCfg) == SW_CFG_SECTION_START);
 967 compile_time_assert (sizeof(struct sxg_config) == HW_CFG_SECTION_SIZE
 968                                                         + SW_CFG_SECTION_SIZE);
 969
 970 compile_time_assert (offsetof(struct sxg_config_a, SwCfg)
 971                                                  == SW_CFG_SECTION_START_A);
 972 compile_time_assert (sizeof(struct sxg_config_a) == HW_CFG_SECTION_SIZE_A
 973                                                  + SW_CFG_SECTION_SIZE);
 974 #endif
 975 /*
 976  * Structure used to pass information between driver and user-mode
 977  * control application
 978  */
 979 struct adapt_userinfo {
 980         bool                LinkUp;
 981         /* use LinkUp - any need for other states? */
 982         /* u32              LinkState; */
 983         u32                 LinkSpeed;          /* not currently needed */
 984         u32                 LinkDuplex;         /* not currently needed */
 985         enum xcvr_type      XcvrType;           /* type of xcvr on fiber card */
 986         /* fiber card xcvr vendor */
 987         unsigned char           XcvrVendor[XCVR_VENDOR_LEN];
 988         unsigned char           XcvrMode[XCVR_MODEL_LEN];
 989         u32                 Port;               /* not currently needed */
 990         u32                 PhysPort;           /* not currently needed */
 991         ushort              PciLanes;
 992         unsigned char   MacAddr[6];
 993         unsigned char   CurrMacAddr[6];
 994         struct atk_fru      AtkFru;
 995         ushort              OemFruFormat;
 996         union oem_fru       OemFru;
 997 };
 998
 999 #pragma pack(pop)
1000
1001 /* Miscellaneous Hardware definitions */
1002
1003 /* Hardware Type definitions  */
1004
1005 /* Sahara (ASIC level) defines */
1006 #define SAHARA_GRAM_SIZE        0x020000        /* GRAM size - 128 KB */
1007 #define SAHARA_DRAM_SIZE        0x200000        /* DRAM size - 2 MB */
1008 /* QRAM size - 16K entries (64 KB) */
1009 #define SAHARA_QRAM_SIZE        0x004000
1010 /* WCS - 8K instructions (x 108 bits) */
1011 #define SAHARA_WCS_SIZE         0x002000
1012
1013 /* Arabia (board level) defines */
1014 #define FLASH_SIZE              0x080000        /* 512 KB (4 Mb) */
1015 /* EEPROM size (bytes), including xfmr area */
1016 #define EEPROM_SIZE_XFMR        1024
1017 /* EEPROM size excluding xfmr area (512 + 128) */
1018 #define EEPROM_SIZE_NO_XFMR     640
1019 /* EEPROM size for Sahara rev A */
1020 #define EEPROM_SIZE_REV_A       512