arch/powerpc/math-emu/math_efp.c

   1 /*
   2  * arch/powerpc/math-emu/math_efp.c
   3  *
   4  * Copyright (C) 2006-2008, 2010 Freescale Semiconductor, Inc.
   5  *
   6  * Author: Ebony Zhu,   <ebony.zhu@freescale.com>
   7  *         Yu Liu,      <yu.liu@freescale.com>
   8  *
   9  * Derived from arch/alpha/math-emu/math.c
  10  *              arch/powerpc/math-emu/math.c
  11  *
  12  * Description:
  13  * This file is the exception handler to make E500 SPE instructions
  14  * fully comply with IEEE-754 floating point standard.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License
  18  * as published by the Free Software Foundation; either version
  19  * 2 of the License, or (at your option) any later version.
  20  */
  21
  22 #include <linux/types.h>
  23
  24 #include <asm/uaccess.h>
  25 #include <asm/reg.h>
  26
  27 #define FP_EX_BOOKE_E500_SPE
  28 #include <asm/sfp-machine.h>
  29
  30 #include <math-emu/soft-fp.h>
  31 #include <math-emu/single.h>
  32 #include <math-emu/double.h>
  33
  34 #define EFAPU           0x4
  35
  36 #define VCT             0x4
  37 #define SPFP            0x6
  38 #define DPFP            0x7
  39
  40 #define EFSADD          0x2c0
  41 #define EFSSUB          0x2c1
  42 #define EFSABS          0x2c4
  43 #define EFSNABS         0x2c5
  44 #define EFSNEG          0x2c6
  45 #define EFSMUL          0x2c8
  46 #define EFSDIV          0x2c9
  47 #define EFSCMPGT        0x2cc
  48 #define EFSCMPLT        0x2cd
  49 #define EFSCMPEQ        0x2ce
  50 #define EFSCFD          0x2cf
  51 #define EFSCFSI         0x2d1
  52 #define EFSCTUI         0x2d4
  53 #define EFSCTSI         0x2d5
  54 #define EFSCTUF         0x2d6
  55 #define EFSCTSF         0x2d7
  56 #define EFSCTUIZ        0x2d8
  57 #define EFSCTSIZ        0x2da
  58
  59 #define EVFSADD         0x280
  60 #define EVFSSUB         0x281
  61 #define EVFSABS         0x284
  62 #define EVFSNABS        0x285
  63 #define EVFSNEG         0x286
  64 #define EVFSMUL         0x288
  65 #define EVFSDIV         0x289
  66 #define EVFSCMPGT       0x28c
  67 #define EVFSCMPLT       0x28d
  68 #define EVFSCMPEQ       0x28e
  69 #define EVFSCTUI        0x294
  70 #define EVFSCTSI        0x295
  71 #define EVFSCTUF        0x296
  72 #define EVFSCTSF        0x297
  73 #define EVFSCTUIZ       0x298
  74 #define EVFSCTSIZ       0x29a
  75
  76 #define EFDADD          0x2e0
  77 #define EFDSUB          0x2e1
  78 #define EFDABS          0x2e4
  79 #define EFDNABS         0x2e5
  80 #define EFDNEG          0x2e6
  81 #define EFDMUL          0x2e8
  82 #define EFDDIV          0x2e9
  83 #define EFDCTUIDZ       0x2ea
  84 #define EFDCTSIDZ       0x2eb
  85 #define EFDCMPGT        0x2ec
  86 #define EFDCMPLT        0x2ed
  87 #define EFDCMPEQ        0x2ee
  88 #define EFDCFS          0x2ef
  89 #define EFDCTUI         0x2f4
  90 #define EFDCTSI         0x2f5
  91 #define EFDCTUF         0x2f6
  92 #define EFDCTSF         0x2f7
  93 #define EFDCTUIZ        0x2f8
  94 #define EFDCTSIZ        0x2fa
  95
  96 #define AB      2
  97 #define XA      3
  98 #define XB      4
  99 #define XCR     5
 100 #define NOTYPE  0
 101
 102 #define SIGN_BIT_S      (1UL << 31)
 103 #define SIGN_BIT_D      (1ULL << 63)
 104 #define FP_EX_MASK      (FP_EX_INEXACT | FP_EX_INVALID | FP_EX_DIVZERO | \
 105                         FP_EX_UNDERFLOW | FP_EX_OVERFLOW)
 106
 107 static int have_e500_cpu_a005_erratum;
 108
 109 union dw_union {
 110         u64 dp[1];
 111         u32 wp[2];
 112 };
 113
 114 static unsigned long insn_type(unsigned long speinsn)
 115 {
 116         unsigned long ret = NOTYPE;
 117
 118         switch (speinsn & 0x7ff) {
 119         case EFSABS:    ret = XA;       break;
 120         case EFSADD:    ret = AB;       break;
 121         case EFSCFD:    ret = XB;       break;
 122         case EFSCMPEQ:  ret = XCR;      break;
 123         case EFSCMPGT:  ret = XCR;      break;
 124         case EFSCMPLT:  ret = XCR;      break;
 125         case EFSCTSF:   ret = XB;       break;
 126         case EFSCTSI:   ret = XB;       break;
 127         case EFSCTSIZ:  ret = XB;       break;
 128         case EFSCTUF:   ret = XB;       break;
 129         case EFSCTUI:   ret = XB;       break;
 130         case EFSCTUIZ:  ret = XB;       break;
 131         case EFSDIV:    ret = AB;       break;
 132         case EFSMUL:    ret = AB;       break;
 133         case EFSNABS:   ret = XA;       break;
 134         case EFSNEG:    ret = XA;       break;
 135         case EFSSUB:    ret = AB;       break;
 136         case EFSCFSI:   ret = XB;       break;
 137
 138         case EVFSABS:   ret = XA;       break;
 139         case EVFSADD:   ret = AB;       break;
 140         case EVFSCMPEQ: ret = XCR;      break;
 141         case EVFSCMPGT: ret = XCR;      break;
 142         case EVFSCMPLT: ret = XCR;      break;
 143         case EVFSCTSF:  ret = XB;       break;
 144         case EVFSCTSI:  ret = XB;       break;
 145         case EVFSCTSIZ: ret = XB;       break;
 146         case EVFSCTUF:  ret = XB;       break;
 147         case EVFSCTUI:  ret = XB;       break;
 148         case EVFSCTUIZ: ret = XB;       break;
 149         case EVFSDIV:   ret = AB;       break;
 150         case EVFSMUL:   ret = AB;       break;
 151         case EVFSNABS:  ret = XA;       break;
 152         case EVFSNEG:   ret = XA;       break;
 153         case EVFSSUB:   ret = AB;       break;
 154
 155         case EFDABS:    ret = XA;       break;
 156         case EFDADD:    ret = AB;       break;
 157         case EFDCFS:    ret = XB;       break;
 158         case EFDCMPEQ:  ret = XCR;      break;
 159         case EFDCMPGT:  ret = XCR;      break;
 160         case EFDCMPLT:  ret = XCR;      break;
 161         case EFDCTSF:   ret = XB;       break;
 162         case EFDCTSI:   ret = XB;       break;
 163         case EFDCTSIDZ: ret = XB;       break;
 164         case EFDCTSIZ:  ret = XB;       break;
 165         case EFDCTUF:   ret = XB;       break;
 166         case EFDCTUI:   ret = XB;       break;
 167         case EFDCTUIDZ: ret = XB;       break;
 168         case EFDCTUIZ:  ret = XB;       break;
 169         case EFDDIV:    ret = AB;       break;
 170         case EFDMUL:    ret = AB;       break;
 171         case EFDNABS:   ret = XA;       break;
 172         case EFDNEG:    ret = XA;       break;
 173         case EFDSUB:    ret = AB;       break;
 174         }
 175
 176         return ret;
 177 }
 178
 179 int do_spe_mathemu(struct pt_regs *regs)
 180 {
 181         FP_DECL_EX;
 182         int IR, cmp;
 183
 184         unsigned long type, func, fc, fa, fb, src, speinsn;
 185         union dw_union vc, va, vb;
 186
 187         if (get_user(speinsn, (unsigned int __user *) regs->nip))
 188                 return -EFAULT;
 189         if ((speinsn >> 26) != EFAPU)
 190                 return -EINVAL;         /* not an spe instruction */
 191
 192         type = insn_type(speinsn);
 193         if (type == NOTYPE)
 194                 goto illegal;
 195
 196         func = speinsn & 0x7ff;
 197         fc = (speinsn >> 21) & 0x1f;
 198         fa = (speinsn >> 16) & 0x1f;
 199         fb = (speinsn >> 11) & 0x1f;
 200         src = (speinsn >> 5) & 0x7;
 201
 202         vc.wp[0] = current->thread.evr[fc];
 203         vc.wp[1] = regs->gpr[fc];
 204         va.wp[0] = current->thread.evr[fa];
 205         va.wp[1] = regs->gpr[fa];
 206         vb.wp[0] = current->thread.evr[fb];
 207         vb.wp[1] = regs->gpr[fb];
 208
 209         __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
 210
 211         pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
 212         pr_debug("vc: %08x  %08x\n", vc.wp[0], vc.wp[1]);
 213         pr_debug("va: %08x  %08x\n", va.wp[0], va.wp[1]);
 214         pr_debug("vb: %08x  %08x\n", vb.wp[0], vb.wp[1]);
 215
 216         switch (src) {
 217         case SPFP: {
 218                 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
 219
 220                 switch (type) {
 221                 case AB:
 222                 case XCR:
 223                         FP_UNPACK_SP(SA, va.wp + 1);
 224                 case XB:
 225                         FP_UNPACK_SP(SB, vb.wp + 1);
 226                         break;
 227                 case XA:
 228                         FP_UNPACK_SP(SA, va.wp + 1);
 229                         break;
 230                 }
 231
 232                 pr_debug("SA: %ld %08lx %ld (%ld)\n", SA_s, SA_f, SA_e, SA_c);
 233                 pr_debug("SB: %ld %08lx %ld (%ld)\n", SB_s, SB_f, SB_e, SB_c);
 234
 235                 switch (func) {
 236                 case EFSABS:
 237                         vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
 238                         goto update_regs;
 239
 240                 case EFSNABS:
 241                         vc.wp[1] = va.wp[1] | SIGN_BIT_S;
 242                         goto update_regs;
 243
 244                 case EFSNEG:
 245                         vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
 246                         goto update_regs;
 247
 248                 case EFSADD:
 249                         FP_ADD_S(SR, SA, SB);
 250                         goto pack_s;
 251
 252                 case EFSSUB:
 253                         FP_SUB_S(SR, SA, SB);
 254                         goto pack_s;
 255
 256                 case EFSMUL:
 257                         FP_MUL_S(SR, SA, SB);
 258                         goto pack_s;
 259
 260                 case EFSDIV:
 261                         FP_DIV_S(SR, SA, SB);
 262                         goto pack_s;
 263
 264                 case EFSCMPEQ:
 265                         cmp = 0;
 266                         goto cmp_s;
 267
 268                 case EFSCMPGT:
 269                         cmp = 1;
 270                         goto cmp_s;
 271
 272                 case EFSCMPLT:
 273                         cmp = -1;
 274                         goto cmp_s;
 275
 276                 case EFSCTSF:
 277                 case EFSCTUF:
 278                         if (!((vb.wp[1] >> 23) == 0xff && ((vb.wp[1] & 0x7fffff) > 0))) {
 279                                 /* NaN */
 280                                 if (((vb.wp[1] >> 23) & 0xff) == 0) {
 281                                         /* denorm */
 282                                         vc.wp[1] = 0x0;
 283                                 } else if ((vb.wp[1] >> 31) == 0) {
 284                                         /* positive normal */
 285                                         vc.wp[1] = (func == EFSCTSF) ?
 286                                                 0x7fffffff : 0xffffffff;
 287                                 } else { /* negative normal */
 288                                         vc.wp[1] = (func == EFSCTSF) ?
 289                                                 0x80000000 : 0x0;
 290                                 }
 291                         } else { /* rB is NaN */
 292                                 vc.wp[1] = 0x0;
 293                         }
 294                         goto update_regs;
 295
 296                 case EFSCFD: {
 297                         FP_DECL_D(DB);
 298                         FP_CLEAR_EXCEPTIONS;
 299                         FP_UNPACK_DP(DB, vb.dp);
 300
 301                         pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
 302                                         DB_s, DB_f1, DB_f0, DB_e, DB_c);
 303
 304                         FP_CONV(S, D, 1, 2, SR, DB);
 305                         goto pack_s;
 306                 }
 307
 308                 case EFSCTSI:
 309                 case EFSCTSIZ:
 310                 case EFSCTUI:
 311                 case EFSCTUIZ:
 312                         if (func & 0x4) {
 313                                 _FP_ROUND(1, SB);
 314                         } else {
 315                                 _FP_ROUND_ZERO(1, SB);
 316                         }
 317                         FP_TO_INT_S(vc.wp[1], SB, 32,
 318                                         (((func & 0x3) != 0) || SB_s));
 319                         goto update_regs;
 320
 321                 default:
 322                         goto illegal;
 323                 }
 324                 break;
 325
 326 pack_s:
 327                 pr_debug("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c);
 328
 329                 FP_PACK_SP(vc.wp + 1, SR);
 330                 goto update_regs;
 331
 332 cmp_s:
 333                 FP_CMP_S(IR, SA, SB, 3);
 334                 if (IR == 3 && (FP_ISSIGNAN_S(SA) || FP_ISSIGNAN_S(SB)))
 335                         FP_SET_EXCEPTION(FP_EX_INVALID);
 336                 if (IR == cmp) {
 337                         IR = 0x4;
 338                 } else {
 339                         IR = 0;
 340                 }
 341                 goto update_ccr;
 342         }
 343
 344         case DPFP: {
 345                 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
 346
 347                 switch (type) {
 348                 case AB:
 349                 case XCR:
 350                         FP_UNPACK_DP(DA, va.dp);
 351                 case XB:
 352                         FP_UNPACK_DP(DB, vb.dp);
 353                         break;
 354                 case XA:
 355                         FP_UNPACK_DP(DA, va.dp);
 356                         break;
 357                 }
 358
 359                 pr_debug("DA: %ld %08lx %08lx %ld (%ld)\n",
 360                                 DA_s, DA_f1, DA_f0, DA_e, DA_c);
 361                 pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
 362                                 DB_s, DB_f1, DB_f0, DB_e, DB_c);
 363
 364                 switch (func) {
 365                 case EFDABS:
 366                         vc.dp[0] = va.dp[0] & ~SIGN_BIT_D;
 367                         goto update_regs;
 368
 369                 case EFDNABS:
 370                         vc.dp[0] = va.dp[0] | SIGN_BIT_D;
 371                         goto update_regs;
 372
 373                 case EFDNEG:
 374                         vc.dp[0] = va.dp[0] ^ SIGN_BIT_D;
 375                         goto update_regs;
 376
 377                 case EFDADD:
 378                         FP_ADD_D(DR, DA, DB);
 379                         goto pack_d;
 380
 381                 case EFDSUB:
 382                         FP_SUB_D(DR, DA, DB);
 383                         goto pack_d;
 384
 385                 case EFDMUL:
 386                         FP_MUL_D(DR, DA, DB);
 387                         goto pack_d;
 388
 389                 case EFDDIV:
 390                         FP_DIV_D(DR, DA, DB);
 391                         goto pack_d;
 392
 393                 case EFDCMPEQ:
 394                         cmp = 0;
 395                         goto cmp_d;
 396
 397                 case EFDCMPGT:
 398                         cmp = 1;
 399                         goto cmp_d;
 400
 401                 case EFDCMPLT:
 402                         cmp = -1;
 403                         goto cmp_d;
 404
 405                 case EFDCTSF:
 406                 case EFDCTUF:
 407                         if (!((vb.wp[0] >> 20) == 0x7ff &&
 408                            ((vb.wp[0] & 0xfffff) > 0 || (vb.wp[1] > 0)))) {
 409                                 /* not a NaN */
 410                                 if (((vb.wp[0] >> 20) & 0x7ff) == 0) {
 411                                         /* denorm */
 412                                         vc.wp[1] = 0x0;
 413                                 } else if ((vb.wp[0] >> 31) == 0) {
 414                                         /* positive normal */
 415                                         vc.wp[1] = (func == EFDCTSF) ?
 416                                                 0x7fffffff : 0xffffffff;
 417                                 } else { /* negative normal */
 418                                         vc.wp[1] = (func == EFDCTSF) ?
 419                                                 0x80000000 : 0x0;
 420                                 }
 421                         } else { /* NaN */
 422                                 vc.wp[1] = 0x0;
 423                         }
 424                         goto update_regs;
 425
 426                 case EFDCFS: {
 427                         FP_DECL_S(SB);
 428                         FP_CLEAR_EXCEPTIONS;
 429                         FP_UNPACK_SP(SB, vb.wp + 1);
 430
 431                         pr_debug("SB: %ld %08lx %ld (%ld)\n",
 432                                         SB_s, SB_f, SB_e, SB_c);
 433
 434                         FP_CONV(D, S, 2, 1, DR, SB);
 435                         goto pack_d;
 436                 }
 437
 438                 case EFDCTUIDZ:
 439                 case EFDCTSIDZ:
 440                         _FP_ROUND_ZERO(2, DB);
 441                         FP_TO_INT_D(vc.dp[0], DB, 64, ((func & 0x1) == 0));
 442                         goto update_regs;
 443
 444                 case EFDCTUI:
 445                 case EFDCTSI:
 446                 case EFDCTUIZ:
 447                 case EFDCTSIZ:
 448                         if (func & 0x4) {
 449                                 _FP_ROUND(2, DB);
 450                         } else {
 451                                 _FP_ROUND_ZERO(2, DB);
 452                         }
 453                         FP_TO_INT_D(vc.wp[1], DB, 32,
 454                                         (((func & 0x3) != 0) || DB_s));
 455                         goto update_regs;
 456
 457                 default:
 458                         goto illegal;
 459                 }
 460                 break;
 461
 462 pack_d:
 463                 pr_debug("DR: %ld %08lx %08lx %ld (%ld)\n",
 464                                 DR_s, DR_f1, DR_f0, DR_e, DR_c);
 465
 466                 FP_PACK_DP(vc.dp, DR);
 467                 goto update_regs;
 468
 469 cmp_d:
 470                 FP_CMP_D(IR, DA, DB, 3);
 471                 if (IR == 3 && (FP_ISSIGNAN_D(DA) || FP_ISSIGNAN_D(DB)))
 472                         FP_SET_EXCEPTION(FP_EX_INVALID);
 473                 if (IR == cmp) {
 474                         IR = 0x4;
 475                 } else {
 476                         IR = 0;
 477                 }
 478                 goto update_ccr;
 479
 480         }
 481
 482         case VCT: {
 483                 FP_DECL_S(SA0); FP_DECL_S(SB0); FP_DECL_S(SR0);
 484                 FP_DECL_S(SA1); FP_DECL_S(SB1); FP_DECL_S(SR1);
 485                 int IR0, IR1;
 486
 487                 switch (type) {
 488                 case AB:
 489                 case XCR:
 490                         FP_UNPACK_SP(SA0, va.wp);
 491                         FP_UNPACK_SP(SA1, va.wp + 1);
 492                 case XB:
 493                         FP_UNPACK_SP(SB0, vb.wp);
 494                         FP_UNPACK_SP(SB1, vb.wp + 1);
 495                         break;
 496                 case XA:
 497                         FP_UNPACK_SP(SA0, va.wp);
 498                         FP_UNPACK_SP(SA1, va.wp + 1);
 499                         break;
 500                 }
 501
 502                 pr_debug("SA0: %ld %08lx %ld (%ld)\n",
 503                                 SA0_s, SA0_f, SA0_e, SA0_c);
 504                 pr_debug("SA1: %ld %08lx %ld (%ld)\n",
 505                                 SA1_s, SA1_f, SA1_e, SA1_c);
 506                 pr_debug("SB0: %ld %08lx %ld (%ld)\n",
 507                                 SB0_s, SB0_f, SB0_e, SB0_c);
 508                 pr_debug("SB1: %ld %08lx %ld (%ld)\n",
 509                                 SB1_s, SB1_f, SB1_e, SB1_c);
 510
 511                 switch (func) {
 512                 case EVFSABS:
 513                         vc.wp[0] = va.wp[0] & ~SIGN_BIT_S;
 514                         vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
 515                         goto update_regs;
 516
 517                 case EVFSNABS:
 518                         vc.wp[0] = va.wp[0] | SIGN_BIT_S;
 519                         vc.wp[1] = va.wp[1] | SIGN_BIT_S;
 520                         goto update_regs;
 521
 522                 case EVFSNEG:
 523                         vc.wp[0] = va.wp[0] ^ SIGN_BIT_S;
 524                         vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
 525                         goto update_regs;
 526
 527                 case EVFSADD:
 528                         FP_ADD_S(SR0, SA0, SB0);
 529                         FP_ADD_S(SR1, SA1, SB1);
 530                         goto pack_vs;
 531
 532                 case EVFSSUB:
 533                         FP_SUB_S(SR0, SA0, SB0);
 534                         FP_SUB_S(SR1, SA1, SB1);
 535                         goto pack_vs;
 536
 537                 case EVFSMUL:
 538                         FP_MUL_S(SR0, SA0, SB0);
 539                         FP_MUL_S(SR1, SA1, SB1);
 540                         goto pack_vs;
 541
 542                 case EVFSDIV:
 543                         FP_DIV_S(SR0, SA0, SB0);
 544                         FP_DIV_S(SR1, SA1, SB1);
 545                         goto pack_vs;
 546
 547                 case EVFSCMPEQ:
 548                         cmp = 0;
 549                         goto cmp_vs;
 550
 551                 case EVFSCMPGT:
 552                         cmp = 1;
 553                         goto cmp_vs;
 554
 555                 case EVFSCMPLT:
 556                         cmp = -1;
 557                         goto cmp_vs;
 558
 559                 case EVFSCTSF:
 560                         __asm__ __volatile__ ("mtspr 512, %4\n"
 561                                 "efsctsf %0, %2\n"
 562                                 "efsctsf %1, %3\n"
 563                                 : "=r" (vc.wp[0]), "=r" (vc.wp[1])
 564                                 : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0));
 565                         goto update_regs;
 566
 567                 case EVFSCTUF:
 568                         __asm__ __volatile__ ("mtspr 512, %4\n"
 569                                 "efsctuf %0, %2\n"
 570                                 "efsctuf %1, %3\n"
 571                                 : "=r" (vc.wp[0]), "=r" (vc.wp[1])
 572                                 : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0));
 573                         goto update_regs;
 574
 575                 case EVFSCTUI:
 576                 case EVFSCTSI:
 577                 case EVFSCTUIZ:
 578                 case EVFSCTSIZ:
 579                         if (func & 0x4) {
 580                                 _FP_ROUND(1, SB0);
 581                                 _FP_ROUND(1, SB1);
 582                         } else {
 583                                 _FP_ROUND_ZERO(1, SB0);
 584                                 _FP_ROUND_ZERO(1, SB1);
 585                         }
 586                         FP_TO_INT_S(vc.wp[0], SB0, 32,
 587                                         (((func & 0x3) != 0) || SB0_s));
 588                         FP_TO_INT_S(vc.wp[1], SB1, 32,
 589                                         (((func & 0x3) != 0) || SB1_s));
 590                         goto update_regs;
 591
 592                 default:
 593                         goto illegal;
 594                 }
 595                 break;
 596
 597 pack_vs:
 598                 pr_debug("SR0: %ld %08lx %ld (%ld)\n",
 599                                 SR0_s, SR0_f, SR0_e, SR0_c);
 600                 pr_debug("SR1: %ld %08lx %ld (%ld)\n",
 601                                 SR1_s, SR1_f, SR1_e, SR1_c);
 602
 603                 FP_PACK_SP(vc.wp, SR0);
 604                 FP_PACK_SP(vc.wp + 1, SR1);
 605                 goto update_regs;
 606
 607 cmp_vs:
 608                 {
 609                         int ch, cl;
 610
 611                         FP_CMP_S(IR0, SA0, SB0, 3);
 612                         FP_CMP_S(IR1, SA1, SB1, 3);
 613                         if (IR0 == 3 && (FP_ISSIGNAN_S(SA0) || FP_ISSIGNAN_S(SB0)))
 614                                 FP_SET_EXCEPTION(FP_EX_INVALID);
 615                         if (IR1 == 3 && (FP_ISSIGNAN_S(SA1) || FP_ISSIGNAN_S(SB1)))
 616                                 FP_SET_EXCEPTION(FP_EX_INVALID);
 617                         ch = (IR0 == cmp) ? 1 : 0;
 618                         cl = (IR1 == cmp) ? 1 : 0;
 619                         IR = (ch << 3) | (cl << 2) | ((ch | cl) << 1) |
 620                                 ((ch & cl) << 0);
 621                         goto update_ccr;
 622                 }
 623         }
 624         default:
 625                 return -EINVAL;
 626         }
 627
 628 update_ccr:
 629         regs->ccr &= ~(15 << ((7 - ((speinsn >> 23) & 0x7)) << 2));
 630         regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
 631
 632 update_regs:
 633         __FPU_FPSCR &= ~FP_EX_MASK;
 634         __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK);
 635         mtspr(SPRN_SPEFSCR, __FPU_FPSCR);
 636
 637         current->thread.evr[fc] = vc.wp[0];
 638         regs->gpr[fc] = vc.wp[1];
 639
 640         pr_debug("ccr = %08lx\n", regs->ccr);
 641         pr_debug("cur exceptions = %08x spefscr = %08lx\n",
 642                         FP_CUR_EXCEPTIONS, __FPU_FPSCR);
 643         pr_debug("vc: %08x  %08x\n", vc.wp[0], vc.wp[1]);
 644         pr_debug("va: %08x  %08x\n", va.wp[0], va.wp[1]);
 645         pr_debug("vb: %08x  %08x\n", vb.wp[0], vb.wp[1]);
 646
 647         return 0;
 648
 649 illegal:
 650         if (have_e500_cpu_a005_erratum) {
 651                 /* according to e500 cpu a005 erratum, reissue efp inst */
 652                 regs->nip -= 4;
 653                 pr_debug("re-issue efp inst: %08lx\n", speinsn);
 654                 return 0;
 655         }
 656
 657         printk(KERN_ERR "\nOoops! IEEE-754 compliance handler encountered un-supported instruction.\ninst code: %08lx\n", speinsn);
 658         return -ENOSYS;
 659 }
 660
 661 int speround_handler(struct pt_regs *regs)
 662 {
 663         union dw_union fgpr;
 664         int s_lo, s_hi;
 665         unsigned long speinsn, type, fc;
 666
 667         if (get_user(speinsn, (unsigned int __user *) regs->nip))
 668                 return -EFAULT;
 669         if ((speinsn >> 26) != 4)
 670                 return -EINVAL;         /* not an spe instruction */
 671
 672         type = insn_type(speinsn & 0x7ff);
 673         if (type == XCR) return -ENOSYS;
 674
 675         __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
 676         pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
 677
 678         /* No need to round if the result is exact */
 679         if (!(__FPU_FPSCR & FP_EX_INEXACT))
 680                 return 0;
 681
 682         fc = (speinsn >> 21) & 0x1f;
 683         s_lo = regs->gpr[fc] & SIGN_BIT_S;
 684         s_hi = current->thread.evr[fc] & SIGN_BIT_S;
 685         fgpr.wp[0] = current->thread.evr[fc];
 686         fgpr.wp[1] = regs->gpr[fc];
 687
 688         pr_debug("round fgpr: %08x  %08x\n", fgpr.wp[0], fgpr.wp[1]);
 689
 690         switch ((speinsn >> 5) & 0x7) {
 691         /* Since SPE instructions on E500 core can handle round to nearest
 692          * and round toward zero with IEEE-754 complied, we just need
 693          * to handle round toward +Inf and round toward -Inf by software.
 694          */
 695         case SPFP:
 696                 if ((FP_ROUNDMODE) == FP_RND_PINF) {
 697                         if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */
 698                 } else { /* round to -Inf */
 699                         if (s_lo) fgpr.wp[1]++; /* Z < 0, choose Z2 */
 700                 }
 701                 break;
 702
 703         case DPFP:
 704                 if (FP_ROUNDMODE == FP_RND_PINF) {
 705                         if (!s_hi) fgpr.dp[0]++; /* Z > 0, choose Z1 */
 706                 } else { /* round to -Inf */
 707                         if (s_hi) fgpr.dp[0]++; /* Z < 0, choose Z2 */
 708                 }
 709                 break;
 710
 711         case VCT:
 712                 if (FP_ROUNDMODE == FP_RND_PINF) {
 713                         if (!s_lo) fgpr.wp[1]++; /* Z_low > 0, choose Z1 */
 714                         if (!s_hi) fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */
 715                 } else { /* round to -Inf */
 716                         if (s_lo) fgpr.wp[1]++; /* Z_low < 0, choose Z2 */
 717                         if (s_hi) fgpr.wp[0]++; /* Z_high < 0, choose Z2 */
 718                 }
 719                 break;
 720
 721         default:
 722                 return -EINVAL;
 723         }
 724
 725         current->thread.evr[fc] = fgpr.wp[0];
 726         regs->gpr[fc] = fgpr.wp[1];
 727
 728         pr_debug("  to fgpr: %08x  %08x\n", fgpr.wp[0], fgpr.wp[1]);
 729
 730         return 0;
 731 }
 732
 733 int __init spe_mathemu_init(void)
 734 {
 735         u32 pvr, maj, min;
 736
 737         pvr = mfspr(SPRN_PVR);
 738
 739         if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
 740             (PVR_VER(pvr) == PVR_VER_E500V2)) {
 741                 maj = PVR_MAJ(pvr);
 742                 min = PVR_MIN(pvr);
 743
 744                 /*
 745                  * E500 revision below 1.1, 2.3, 3.1, 4.1, 5.1
 746                  * need cpu a005 errata workaround
 747                  */
 748                 switch (maj) {
 749                 case 1:
 750                         if (min < 1)
 751                                 have_e500_cpu_a005_erratum = 1;
 752                         break;
 753                 case 2:
 754                         if (min < 3)
 755                                 have_e500_cpu_a005_erratum = 1;
 756                         break;
 757                 case 3:
 758                 case 4:
 759                 case 5:
 760                         if (min < 1)
 761                                 have_e500_cpu_a005_erratum = 1;
 762                         break;
 763                 default:
 764                         break;
 765                 }
 766         }
 767
 768         return 0;
 769 }
 770
 771 module_init(spe_mathemu_init);