drivers/mtd/spi-nor/nxp-spifi.c

   1 /*
   2  * SPI-NOR driver for NXP SPI Flash Interface (SPIFI)
   3  *
   4  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
   5  *
   6  * Based on Freescale QuadSPI driver:
   7  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/module.h>
  20 #include <linux/mtd/mtd.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/mtd/spi-nor.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/spi/spi.h>
  27
  28 /* NXP SPIFI registers, bits and macros */
  29 #define SPIFI_CTRL                              0x000
  30 #define  SPIFI_CTRL_TIMEOUT(timeout)            (timeout)
  31 #define  SPIFI_CTRL_CSHIGH(cshigh)              ((cshigh) << 16)
  32 #define  SPIFI_CTRL_MODE3                       BIT(23)
  33 #define  SPIFI_CTRL_DUAL                        BIT(28)
  34 #define  SPIFI_CTRL_FBCLK                       BIT(30)
  35 #define SPIFI_CMD                               0x004
  36 #define  SPIFI_CMD_DATALEN(dlen)                ((dlen) & 0x3fff)
  37 #define  SPIFI_CMD_DOUT                         BIT(15)
  38 #define  SPIFI_CMD_INTLEN(ilen)                 ((ilen) << 16)
  39 #define  SPIFI_CMD_FIELDFORM(field)             ((field) << 19)
  40 #define  SPIFI_CMD_FIELDFORM_ALL_SERIAL         SPIFI_CMD_FIELDFORM(0x0)
  41 #define  SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA     SPIFI_CMD_FIELDFORM(0x1)
  42 #define  SPIFI_CMD_FRAMEFORM(frame)             ((frame) << 21)
  43 #define  SPIFI_CMD_FRAMEFORM_OPCODE_ONLY        SPIFI_CMD_FRAMEFORM(0x1)
  44 #define  SPIFI_CMD_OPCODE(op)                   ((op) << 24)
  45 #define SPIFI_ADDR                              0x008
  46 #define SPIFI_IDATA                             0x00c
  47 #define SPIFI_CLIMIT                            0x010
  48 #define SPIFI_DATA                              0x014
  49 #define SPIFI_MCMD                              0x018
  50 #define SPIFI_STAT                              0x01c
  51 #define  SPIFI_STAT_MCINIT                      BIT(0)
  52 #define  SPIFI_STAT_CMD                         BIT(1)
  53 #define  SPIFI_STAT_RESET                       BIT(4)
  54
  55 #define SPI_NOR_MAX_ID_LEN      6
  56
  57 struct nxp_spifi {
  58         struct device *dev;
  59         struct clk *clk_spifi;
  60         struct clk *clk_reg;
  61         void __iomem *io_base;
  62         void __iomem *flash_base;
  63         struct spi_nor nor;
  64         bool memory_mode;
  65         u32 mcmd;
  66 };
  67
  68 static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
  69 {
  70         u8 stat;
  71         int ret;
  72
  73         ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
  74                                  !(stat & SPIFI_STAT_CMD), 10, 30);
  75         if (ret)
  76                 dev_warn(spifi->dev, "command timed out\n");
  77
  78         return ret;
  79 }
  80
  81 static int nxp_spifi_reset(struct nxp_spifi *spifi)
  82 {
  83         u8 stat;
  84         int ret;
  85
  86         writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
  87         ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
  88                                  !(stat & SPIFI_STAT_RESET), 10, 30);
  89         if (ret)
  90                 dev_warn(spifi->dev, "state reset timed out\n");
  91
  92         return ret;
  93 }
  94
  95 static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
  96 {
  97         int ret;
  98
  99         if (!spifi->memory_mode)
 100                 return 0;
 101
 102         ret = nxp_spifi_reset(spifi);
 103         if (ret)
 104                 dev_err(spifi->dev, "unable to enter command mode\n");
 105         else
 106                 spifi->memory_mode = false;
 107
 108         return ret;
 109 }
 110
 111 static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
 112 {
 113         u8 stat;
 114         int ret;
 115
 116         if (spifi->memory_mode)
 117                 return 0;
 118
 119         writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
 120         ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
 121                                  stat & SPIFI_STAT_MCINIT, 10, 30);
 122         if (ret)
 123                 dev_err(spifi->dev, "unable to enter memory mode\n");
 124         else
 125                 spifi->memory_mode = true;
 126
 127         return ret;
 128 }
 129
 130 static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 131 {
 132         struct nxp_spifi *spifi = nor->priv;
 133         u32 cmd;
 134         int ret;
 135
 136         ret = nxp_spifi_set_memory_mode_off(spifi);
 137         if (ret)
 138                 return ret;
 139
 140         cmd = SPIFI_CMD_DATALEN(len) |
 141               SPIFI_CMD_OPCODE(opcode) |
 142               SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 143               SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
 144         writel(cmd, spifi->io_base + SPIFI_CMD);
 145
 146         while (len--)
 147                 *buf++ = readb(spifi->io_base + SPIFI_DATA);
 148
 149         return nxp_spifi_wait_for_cmd(spifi);
 150 }
 151
 152 static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 153 {
 154         struct nxp_spifi *spifi = nor->priv;
 155         u32 cmd;
 156         int ret;
 157
 158         ret = nxp_spifi_set_memory_mode_off(spifi);
 159         if (ret)
 160                 return ret;
 161
 162         cmd = SPIFI_CMD_DOUT |
 163               SPIFI_CMD_DATALEN(len) |
 164               SPIFI_CMD_OPCODE(opcode) |
 165               SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 166               SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
 167         writel(cmd, spifi->io_base + SPIFI_CMD);
 168
 169         while (len--)
 170                 writeb(*buf++, spifi->io_base + SPIFI_DATA);
 171
 172         return nxp_spifi_wait_for_cmd(spifi);
 173 }
 174
 175 static int nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
 176                           size_t *retlen, u_char *buf)
 177 {
 178         struct nxp_spifi *spifi = nor->priv;
 179         int ret;
 180
 181         ret = nxp_spifi_set_memory_mode_on(spifi);
 182         if (ret)
 183                 return ret;
 184
 185         memcpy_fromio(buf, spifi->flash_base + from, len);
 186         *retlen += len;
 187
 188         return 0;
 189 }
 190
 191 static void nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
 192                             size_t *retlen, const u_char *buf)
 193 {
 194         struct nxp_spifi *spifi = nor->priv;
 195         u32 cmd;
 196         int ret;
 197
 198         ret = nxp_spifi_set_memory_mode_off(spifi);
 199         if (ret)
 200                 return;
 201
 202         writel(to, spifi->io_base + SPIFI_ADDR);
 203         *retlen += len;
 204
 205         cmd = SPIFI_CMD_DOUT |
 206               SPIFI_CMD_DATALEN(len) |
 207               SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 208               SPIFI_CMD_OPCODE(nor->program_opcode) |
 209               SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
 210         writel(cmd, spifi->io_base + SPIFI_CMD);
 211
 212         while (len--)
 213                 writeb(*buf++, spifi->io_base + SPIFI_DATA);
 214
 215         nxp_spifi_wait_for_cmd(spifi);
 216 }
 217
 218 static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
 219 {
 220         struct nxp_spifi *spifi = nor->priv;
 221         u32 cmd;
 222         int ret;
 223
 224         ret = nxp_spifi_set_memory_mode_off(spifi);
 225         if (ret)
 226                 return ret;
 227
 228         writel(offs, spifi->io_base + SPIFI_ADDR);
 229
 230         cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 231               SPIFI_CMD_OPCODE(nor->erase_opcode) |
 232               SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
 233         writel(cmd, spifi->io_base + SPIFI_CMD);
 234
 235         return nxp_spifi_wait_for_cmd(spifi);
 236 }
 237
 238 static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
 239 {
 240         switch (spifi->nor.flash_read) {
 241         case SPI_NOR_NORMAL:
 242         case SPI_NOR_FAST:
 243                 spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
 244                 break;
 245         case SPI_NOR_DUAL:
 246         case SPI_NOR_QUAD:
 247                 spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
 248                 break;
 249         default:
 250                 dev_err(spifi->dev, "unsupported SPI read mode\n");
 251                 return -EINVAL;
 252         }
 253
 254         /* Memory mode supports address length between 1 and 4 */
 255         if (spifi->nor.addr_width < 1 || spifi->nor.addr_width > 4)
 256                 return -EINVAL;
 257
 258         spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
 259                        SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
 260                        SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
 261
 262         return 0;
 263 }
 264
 265 static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
 266 {
 267         u8 id[SPI_NOR_MAX_ID_LEN];
 268         nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
 269 }
 270
 271 static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
 272                                  struct device_node *np)
 273 {
 274         enum read_mode flash_read;
 275         u32 ctrl, property;
 276         u16 mode = 0;
 277         int ret;
 278
 279         if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
 280                 switch (property) {
 281                 case 1:
 282                         break;
 283                 case 2:
 284                         mode |= SPI_RX_DUAL;
 285                         break;
 286                 case 4:
 287                         mode |= SPI_RX_QUAD;
 288                         break;
 289                 default:
 290                         dev_err(spifi->dev, "unsupported rx-bus-width\n");
 291                         return -EINVAL;
 292                 }
 293         }
 294
 295         if (of_find_property(np, "spi-cpha", NULL))
 296                 mode |= SPI_CPHA;
 297
 298         if (of_find_property(np, "spi-cpol", NULL))
 299                 mode |= SPI_CPOL;
 300
 301         /* Setup control register defaults */
 302         ctrl = SPIFI_CTRL_TIMEOUT(1000) |
 303                SPIFI_CTRL_CSHIGH(15) |
 304                SPIFI_CTRL_FBCLK;
 305
 306         if (mode & SPI_RX_DUAL) {
 307                 ctrl |= SPIFI_CTRL_DUAL;
 308                 flash_read = SPI_NOR_DUAL;
 309         } else if (mode & SPI_RX_QUAD) {
 310                 ctrl &= ~SPIFI_CTRL_DUAL;
 311                 flash_read = SPI_NOR_QUAD;
 312         } else {
 313                 ctrl |= SPIFI_CTRL_DUAL;
 314                 flash_read = SPI_NOR_NORMAL;
 315         }
 316
 317         switch (mode & (SPI_CPHA | SPI_CPOL)) {
 318         case SPI_MODE_0:
 319                 ctrl &= ~SPIFI_CTRL_MODE3;
 320                 break;
 321         case SPI_MODE_3:
 322                 ctrl |= SPIFI_CTRL_MODE3;
 323                 break;
 324         default:
 325                 dev_err(spifi->dev, "only mode 0 and 3 supported\n");
 326                 return -EINVAL;
 327         }
 328
 329         writel(ctrl, spifi->io_base + SPIFI_CTRL);
 330
 331         spifi->nor.dev   = spifi->dev;
 332         spi_nor_set_flash_node(&spifi->nor, np);
 333         spifi->nor.priv  = spifi;
 334         spifi->nor.read  = nxp_spifi_read;
 335         spifi->nor.write = nxp_spifi_write;
 336         spifi->nor.erase = nxp_spifi_erase;
 337         spifi->nor.read_reg  = nxp_spifi_read_reg;
 338         spifi->nor.write_reg = nxp_spifi_write_reg;
 339
 340         /*
 341          * The first read on a hard reset isn't reliable so do a
 342          * dummy read of the id before calling spi_nor_scan().
 343          * The reason for this problem is unknown.
 344          *
 345          * The official NXP spifilib uses more or less the same
 346          * workaround that is applied here by reading the device
 347          * id multiple times.
 348          */
 349         nxp_spifi_dummy_id_read(&spifi->nor);
 350
 351         ret = spi_nor_scan(&spifi->nor, NULL, flash_read);
 352         if (ret) {
 353                 dev_err(spifi->dev, "device scan failed\n");
 354                 return ret;
 355         }
 356
 357         ret = nxp_spifi_setup_memory_cmd(spifi);
 358         if (ret) {
 359                 dev_err(spifi->dev, "memory command setup failed\n");
 360                 return ret;
 361         }
 362
 363         ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
 364         if (ret) {
 365                 dev_err(spifi->dev, "mtd device parse failed\n");
 366                 return ret;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static int nxp_spifi_probe(struct platform_device *pdev)
 373 {
 374         struct device_node *flash_np;
 375         struct nxp_spifi *spifi;
 376         struct resource *res;
 377         int ret;
 378
 379         spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
 380         if (!spifi)
 381                 return -ENOMEM;
 382
 383         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spifi");
 384         spifi->io_base = devm_ioremap_resource(&pdev->dev, res);
 385         if (IS_ERR(spifi->io_base))
 386                 return PTR_ERR(spifi->io_base);
 387
 388         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash");
 389         spifi->flash_base = devm_ioremap_resource(&pdev->dev, res);
 390         if (IS_ERR(spifi->flash_base))
 391                 return PTR_ERR(spifi->flash_base);
 392
 393         spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi");
 394         if (IS_ERR(spifi->clk_spifi)) {
 395                 dev_err(&pdev->dev, "spifi clock not found\n");
 396                 return PTR_ERR(spifi->clk_spifi);
 397         }
 398
 399         spifi->clk_reg = devm_clk_get(&pdev->dev, "reg");
 400         if (IS_ERR(spifi->clk_reg)) {
 401                 dev_err(&pdev->dev, "reg clock not found\n");
 402                 return PTR_ERR(spifi->clk_reg);
 403         }
 404
 405         ret = clk_prepare_enable(spifi->clk_reg);
 406         if (ret) {
 407                 dev_err(&pdev->dev, "unable to enable reg clock\n");
 408                 return ret;
 409         }
 410
 411         ret = clk_prepare_enable(spifi->clk_spifi);
 412         if (ret) {
 413                 dev_err(&pdev->dev, "unable to enable spifi clock\n");
 414                 goto dis_clk_reg;
 415         }
 416
 417         spifi->dev = &pdev->dev;
 418         platform_set_drvdata(pdev, spifi);
 419
 420         /* Initialize and reset device */
 421         nxp_spifi_reset(spifi);
 422         writel(0, spifi->io_base + SPIFI_IDATA);
 423         writel(0, spifi->io_base + SPIFI_MCMD);
 424         nxp_spifi_reset(spifi);
 425
 426         flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
 427         if (!flash_np) {
 428                 dev_err(&pdev->dev, "no SPI flash device to configure\n");
 429                 ret = -ENODEV;
 430                 goto dis_clks;
 431         }
 432
 433         ret = nxp_spifi_setup_flash(spifi, flash_np);
 434         if (ret) {
 435                 dev_err(&pdev->dev, "unable to setup flash chip\n");
 436                 goto dis_clks;
 437         }
 438
 439         return 0;
 440
 441 dis_clks:
 442         clk_disable_unprepare(spifi->clk_spifi);
 443 dis_clk_reg:
 444         clk_disable_unprepare(spifi->clk_reg);
 445         return ret;
 446 }
 447
 448 static int nxp_spifi_remove(struct platform_device *pdev)
 449 {
 450         struct nxp_spifi *spifi = platform_get_drvdata(pdev);
 451
 452         mtd_device_unregister(&spifi->nor.mtd);
 453         clk_disable_unprepare(spifi->clk_spifi);
 454         clk_disable_unprepare(spifi->clk_reg);
 455
 456         return 0;
 457 }
 458
 459 static const struct of_device_id nxp_spifi_match[] = {
 460         {.compatible = "nxp,lpc1773-spifi"},
 461         { /* sentinel */ }
 462 };
 463 MODULE_DEVICE_TABLE(of, nxp_spifi_match);
 464
 465 static struct platform_driver nxp_spifi_driver = {
 466         .probe  = nxp_spifi_probe,
 467         .remove = nxp_spifi_remove,
 468         .driver = {
 469                 .name = "nxp-spifi",
 470                 .of_match_table = nxp_spifi_match,
 471         },
 472 };
 473 module_platform_driver(nxp_spifi_driver);
 474
 475 MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
 476 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
 477 MODULE_LICENSE("GPL v2");