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[PATCH] use cycle_t instead of u64 in struct time_interpolator
[linux/fpc-iii.git] / drivers / pcmcia / m8xx_pcmcia.c
blob3b72be880401398d93b6465c82333aa84af5e585
1 /*
2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
3 *
4 * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
5 * (C) 2001-2002 Montavista Software, Inc.
6 * <mlocke@mvista.com>
7 *
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
12 *
13 * Some fixes, additions (C) 2005 Montavista Software, Inc.
14 * <vbordug@ru.mvista.com>
15 *
16 * "The ExCA standard specifies that socket controllers should provide
17 * two IO and five memory windows per socket, which can be independently
18 * configured and positioned in the host address space and mapped to
19 * arbitrary segments of card address space. " - David A Hinds. 1999
20 *
21 * This controller does _not_ meet the ExCA standard.
22 *
23 * m8xx pcmcia controller brief info:
24 * + 8 windows (attrib, mem, i/o)
25 * + up to two slots (SLOT_A and SLOT_B)
26 * + inputpins, outputpins, event and mask registers.
27 * - no offset register. sigh.
28 *
29 * Because of the lacking offset register we must map the whole card.
30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34 * They are maximum 64KByte each...
35 */
36
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/fcntl.h>
41 #include <linux/string.h>
42
43 #include <asm/io.h>
44 #include <asm/bitops.h>
45 #include <asm/system.h>
46
47 #include <linux/kernel.h>
48 #include <linux/errno.h>
49 #include <linux/sched.h>
50 #include <linux/slab.h>
51 #include <linux/timer.h>
52 #include <linux/ioport.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/platform_device.h>
56
57 #include <asm/mpc8xx.h>
58 #include <asm/8xx_immap.h>
59 #include <asm/irq.h>
60
61 #include <pcmcia/version.h>
62 #include <pcmcia/cs_types.h>
63 #include <pcmcia/cs.h>
64 #include <pcmcia/ss.h>
65
66 #ifdef PCMCIA_DEBUG
67 static int pc_debug = PCMCIA_DEBUG;
68 module_param(pc_debug, int, 0);
69 #define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
70 #else
71 #define dprintk(args...)
72 #endif
73
74 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
75 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
76
77 static const char *version = "Version 0.06, Aug 2005";
78 MODULE_LICENSE("Dual MPL/GPL");
79
80 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
81
82 /* The RPX series use SLOT_B */
83 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
84 #define CONFIG_PCMCIA_SLOT_B
85 #define CONFIG_BD_IS_MHZ
86 #endif
87
88 /* The ADS board use SLOT_A */
89 #ifdef CONFIG_ADS
90 #define CONFIG_PCMCIA_SLOT_A
91 #define CONFIG_BD_IS_MHZ
92 #endif
93
94 /* The FADS series are a mess */
95 #ifdef CONFIG_FADS
96 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
97 #define CONFIG_PCMCIA_SLOT_A
98 #else
99 #define CONFIG_PCMCIA_SLOT_B
100 #endif
101 #endif
102
103 #if defined(CONFIG_MPC885ADS)
104 #define CONFIG_PCMCIA_SLOT_A
105 #define PCMCIA_GLITCHY_CD
106 #endif
107
108 /* Cyclades ACS uses both slots */
109 #ifdef CONFIG_PRxK
110 #define CONFIG_PCMCIA_SLOT_A
111 #define CONFIG_PCMCIA_SLOT_B
112 #endif
113
114 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
115
116 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
117
118 #define PCMCIA_SOCKETS_NO 2
119 /* We have only 8 windows, dualsocket support will be limited. */
120 #define PCMCIA_MEM_WIN_NO 2
121 #define PCMCIA_IO_WIN_NO 2
122 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
123
124 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
125
126 #define PCMCIA_SOCKETS_NO 1
127 /* full support for one slot */
128 #define PCMCIA_MEM_WIN_NO 5
129 #define PCMCIA_IO_WIN_NO 2
130
131 /* define _slot_ to be able to optimize macros */
132
133 #ifdef CONFIG_PCMCIA_SLOT_A
134 #define _slot_ 0
135 #define PCMCIA_SLOT_MSG "SLOT_A"
136 #else
137 #define _slot_ 1
138 #define PCMCIA_SLOT_MSG "SLOT_B"
139 #endif
140
141 #else
142 #error m8xx_pcmcia: Bad configuration!
143 #endif
144
145 /* ------------------------------------------------------------------------- */
146
147 #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
148 #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
149 #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
150
151 #define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
152
153 /* ------------------------------------------------------------------------- */
154
155 /* 2.4.x and newer has this always in HZ */
156 #define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
157
158 static int pcmcia_schlvl = PCMCIA_SCHLVL;
159
160 static DEFINE_SPINLOCK(events_lock);
161
162
163 #define PCMCIA_SOCKET_KEY_5V 1
164 #define PCMCIA_SOCKET_KEY_LV 2
165
166 /* look up table for pgcrx registers */
167 static u32 *m8xx_pgcrx[2] = {
168 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
169 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
170 };
171
172 /*
173 * This structure is used to address each window in the PCMCIA controller.
174 *
175 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
176 * after pcmcia_win[n]...
177 */
178
179 struct pcmcia_win {
180 u32 br;
181 u32 or;
182 };
183
184 /*
185 * For some reason the hardware guys decided to make both slots share
186 * some registers.
187 *
188 * Could someone invent object oriented hardware ?
189 *
190 * The macros are used to get the right bit from the registers.
191 * SLOT_A : slot = 0
192 * SLOT_B : slot = 1
193 */
194
195 #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
196 #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
197 #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
198 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
199
200 #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
201 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
202 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
203 #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
204 #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
205 #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
206 #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
207 #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
208 #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
209 #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
210 #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
211
212 #define M8XX_PCMCIA_POR_VALID 0x00000001
213 #define M8XX_PCMCIA_POR_WRPROT 0x00000002
214 #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
215 #define M8XX_PCMCIA_POR_IO 0x00000018
216 #define M8XX_PCMCIA_POR_16BIT 0x00000040
217
218 #define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
219
220 #define M8XX_PGCRX_CXOE 0x00000080
221 #define M8XX_PGCRX_CXRESET 0x00000040
222
223 /* we keep one lookup table per socket to check flags */
224
225 #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
226
227 struct event_table {
228 u32 regbit;
229 u32 eventbit;
230 };
231
232 struct socket_info {
233 void (*handler)(void *info, u32 events);
234 void *info;
235
236 u32 slot;
237
238 socket_state_t state;
239 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
240 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
241 struct event_table events[PCMCIA_EVENTS_MAX];
242 struct pcmcia_socket socket;
243 };
244
245 static struct socket_info socket[PCMCIA_SOCKETS_NO];
246
247 /*
248 * Search this table to see if the windowsize is
249 * supported...
250 */
251
252 #define M8XX_SIZES_NO 32
253
254 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
255 {
256 0x00000001, 0x00000002, 0x00000008, 0x00000004,
257 0x00000080, 0x00000040, 0x00000010, 0x00000020,
258 0x00008000, 0x00004000, 0x00001000, 0x00002000,
259 0x00000100, 0x00000200, 0x00000800, 0x00000400,
260
261 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
262 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
263 0x00010000, 0x00020000, 0x00080000, 0x00040000,
264 0x00800000, 0x00400000, 0x00100000, 0x00200000
265 };
266
267 /* ------------------------------------------------------------------------- */
268
269 static irqreturn_t m8xx_interrupt(int irq, void *dev);
270
271 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
272
273 /* ------------------------------------------------------------------------- */
274 /* board specific stuff: */
275 /* voltage_set(), hardware_enable() and hardware_disable() */
276 /* ------------------------------------------------------------------------- */
277 /* RPX Boards from Embedded Planet */
278
279 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
280
281 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
282 * SYPCR is write once only, therefore must the slowest memory be faster
283 * than the bus monitor or we will get a machine check due to the bus timeout.
284 */
285
286 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
287
288 #undef PCMCIA_BMT_LIMIT
289 #define PCMCIA_BMT_LIMIT (6*8)
290
291 static int voltage_set(int slot, int vcc, int vpp)
292 {
293 u32 reg = 0;
294
295 switch(vcc) {
296 case 0: break;
297 case 33:
298 reg |= BCSR1_PCVCTL4;
299 break;
300 case 50:
301 reg |= BCSR1_PCVCTL5;
302 break;
303 default:
304 return 1;
305 }
306
307 switch(vpp) {
308 case 0: break;
309 case 33:
310 case 50:
311 if(vcc == vpp)
312 reg |= BCSR1_PCVCTL6;
313 else
314 return 1;
315 break;
316 case 120:
317 reg |= BCSR1_PCVCTL7;
318 default:
319 return 1;
320 }
321
322 if(!((vcc == 50) || (vcc == 0)))
323 return 1;
324
325 /* first, turn off all power */
326
327 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
328
329 /* enable new powersettings */
330
331 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
332
333 return 0;
334 }
335
336 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
337 #define hardware_enable(_slot_) /* No hardware to enable */
338 #define hardware_disable(_slot_) /* No hardware to disable */
339
340 #endif /* CONFIG_RPXCLASSIC */
341
342 /* FADS Boards from Motorola */
343
344 #if defined(CONFIG_FADS)
345
346 #define PCMCIA_BOARD_MSG "FADS"
347
348 static int voltage_set(int slot, int vcc, int vpp)
349 {
350 u32 reg = 0;
351
352 switch(vcc) {
353 case 0:
354 break;
355 case 33:
356 reg |= BCSR1_PCCVCC0;
357 break;
358 case 50:
359 reg |= BCSR1_PCCVCC1;
360 break;
361 default:
362 return 1;
363 }
364
365 switch(vpp) {
366 case 0:
367 break;
368 case 33:
369 case 50:
370 if(vcc == vpp)
371 reg |= BCSR1_PCCVPP1;
372 else
373 return 1;
374 break;
375 case 120:
376 if ((vcc == 33) || (vcc == 50))
377 reg |= BCSR1_PCCVPP0;
378 else
379 return 1;
380 default:
381 return 1;
382 }
383
384 /* first, turn off all power */
385 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
386
387 /* enable new powersettings */
388 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | reg);
389
390 return 0;
391 }
392
393 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
394
395 static void hardware_enable(int slot)
396 {
397 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~BCSR1_PCCEN);
398 }
399
400 static void hardware_disable(int slot)
401 {
402 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | BCSR1_PCCEN);
403 }
404
405 #endif
406
407 /* MPC885ADS Boards */
408
409 #if defined(CONFIG_MPC885ADS)
410
411 #define PCMCIA_BOARD_MSG "MPC885ADS"
412
413 static int voltage_set(int slot, int vcc, int vpp)
414 {
415 u32 reg = 0;
416 unsigned *bcsr_io;
417
418 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
419
420 switch(vcc) {
421 case 0:
422 break;
423 case 33:
424 reg |= BCSR1_PCCVCC0;
425 break;
426 case 50:
427 reg |= BCSR1_PCCVCC1;
428 break;
429 default:
430 goto out_unmap;
431 }
432
433 switch(vpp) {
434 case 0:
435 break;
436 case 33:
437 case 50:
438 if(vcc == vpp)
439 reg |= BCSR1_PCCVPP1;
440 else
441 goto out_unmap;
442 break;
443 case 120:
444 if ((vcc == 33) || (vcc == 50))
445 reg |= BCSR1_PCCVPP0;
446 else
447 goto out_unmap;
448 default:
449 goto out_unmap;
450 }
451
452 /* first, turn off all power */
453 out_be32(bcsr_io, in_be32(bcsr_io) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
454
455 /* enable new powersettings */
456 out_be32(bcsr_io, in_be32(bcsr_io) | reg);
457
458 iounmap(bcsr_io);
459 return 0;
460
461 out_unmap:
462 iounmap(bcsr_io);
463 return 1;
464 }
465
466 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
467
468 static void hardware_enable(int slot)
469 {
470 unsigned *bcsr_io;
471
472 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
473 out_be32(bcsr_io, in_be32(bcsr_io) & ~BCSR1_PCCEN);
474 iounmap(bcsr_io);
475 }
476
477 static void hardware_disable(int slot)
478 {
479 unsigned *bcsr_io;
480
481 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
482 out_be32(bcsr_io, in_be32(bcsr_io) | BCSR1_PCCEN);
483 iounmap(bcsr_io);
484 }
485
486 #endif
487
488 /* ------------------------------------------------------------------------- */
489 /* Motorola MBX860 */
490
491 #if defined(CONFIG_MBX)
492
493 #define PCMCIA_BOARD_MSG "MBX"
494
495 static int voltage_set(int slot, int vcc, int vpp)
496 {
497 u8 reg = 0;
498
499 switch(vcc) {
500 case 0:
501 break;
502 case 33:
503 reg |= CSR2_VCC_33;
504 break;
505 case 50:
506 reg |= CSR2_VCC_50;
507 break;
508 default:
509 return 1;
510 }
511
512 switch(vpp) {
513 case 0:
514 break;
515 case 33:
516 case 50:
517 if(vcc == vpp)
518 reg |= CSR2_VPP_VCC;
519 else
520 return 1;
521 break;
522 case 120:
523 if ((vcc == 33) || (vcc == 50))
524 reg |= CSR2_VPP_12;
525 else
526 return 1;
527 default:
528 return 1;
529 }
530
531 /* first, turn off all power */
532 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
533
534 /* enable new powersettings */
535 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) | reg);
536
537 return 0;
538 }
539
540 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
541 #define hardware_enable(_slot_) /* No hardware to enable */
542 #define hardware_disable(_slot_) /* No hardware to disable */
543
544 #endif /* CONFIG_MBX */
545
546 #if defined(CONFIG_PRxK)
547 #include <asm/cpld.h>
548 extern volatile fpga_pc_regs *fpga_pc;
549
550 #define PCMCIA_BOARD_MSG "MPC855T"
551
552 static int voltage_set(int slot, int vcc, int vpp)
553 {
554 u8 reg = 0;
555 u8 regread;
556 cpld_regs *ccpld = get_cpld();
557
558 switch(vcc) {
559 case 0:
560 break;
561 case 33:
562 reg |= PCMCIA_VCC_33;
563 break;
564 case 50:
565 reg |= PCMCIA_VCC_50;
566 break;
567 default:
568 return 1;
569 }
570
571 switch(vpp) {
572 case 0:
573 break;
574 case 33:
575 case 50:
576 if(vcc == vpp)
577 reg |= PCMCIA_VPP_VCC;
578 else
579 return 1;
580 break;
581 case 120:
582 if ((vcc == 33) || (vcc == 50))
583 reg |= PCMCIA_VPP_12;
584 else
585 return 1;
586 default:
587 return 1;
588 }
589
590 reg = reg >> (slot << 2);
591 regread = in_8(&ccpld->fpga_pc_ctl);
592 if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
593 /* enable new powersettings */
594 regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
595 out_8(&ccpld->fpga_pc_ctl, reg | regread);
596 msleep(100);
597 }
598
599 return 0;
600 }
601
602 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
603 #define hardware_enable(_slot_) /* No hardware to enable */
604 #define hardware_disable(_slot_) /* No hardware to disable */
605
606 #endif /* CONFIG_PRxK */
607
608 static void m8xx_shutdown(void)
609 {
610 u32 m, i;
611 struct pcmcia_win *w;
612
613 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
614 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
615
616 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i));
617 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i));
618
619 /* turn off interrupt and disable CxOE */
620 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
621
622 /* turn off memory windows */
623 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
624 out_be32(&w->or, 0); /* set to not valid */
625 w++;
626 }
627
628 /* turn off voltage */
629 voltage_set(i, 0, 0);
630
631 /* disable external hardware */
632 hardware_disable(i);
633 }
634
635 free_irq(pcmcia_schlvl, NULL);
636 }
637
638 static struct device_driver m8xx_driver = {
639 .name = "m8xx-pcmcia",
640 .bus = &platform_bus_type,
641 .suspend = pcmcia_socket_dev_suspend,
642 .resume = pcmcia_socket_dev_resume,
643 };
644
645 static struct platform_device m8xx_device = {
646 .name = "m8xx-pcmcia",
647 .id = 0,
648 };
649
650 static u32 pending_events[PCMCIA_SOCKETS_NO];
651 static DEFINE_SPINLOCK(pending_event_lock);
652
653 static irqreturn_t m8xx_interrupt(int irq, void *dev)
654 {
655 struct socket_info *s;
656 struct event_table *e;
657 unsigned int i, events, pscr, pipr, per;
658
659 dprintk("Interrupt!\n");
660 /* get interrupt sources */
661
662 pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr);
663 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
664 per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per);
665
666 for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
667 s = &socket[i];
668 e = &s->events[0];
669 events = 0;
670
671 while(e->regbit) {
672 if(pscr & e->regbit)
673 events |= e->eventbit;
674
675 e++;
676 }
677
678 /*
679 * report only if both card detect signals are the same
680 * not too nice done,
681 * we depend on that CD2 is the bit to the left of CD1...
682 */
683 if(events & SS_DETECT)
684 if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
685 (pipr & M8XX_PCMCIA_CD1(i)))
686 {
687 events &= ~SS_DETECT;
688 }
689
690 #ifdef PCMCIA_GLITCHY_CD
691 /*
692 * I've experienced CD problems with my ADS board.
693 * We make an extra check to see if there was a
694 * real change of Card detection.
695 */
696
697 if((events & SS_DETECT) &&
698 ((pipr &
699 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
700 (s->state.Vcc | s->state.Vpp)) {
701 events &= ~SS_DETECT;
702 /*printk( "CD glitch workaround - CD = 0x%08x!\n",
703 (pipr & (M8XX_PCMCIA_CD2(i)
704 | M8XX_PCMCIA_CD1(i))));*/
705 }
706 #endif
707
708 /* call the handler */
709
710 dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
711 "pipr = 0x%08x\n",
712 i, events, pscr, pipr);
713
714 if(events) {
715 spin_lock(&pending_event_lock);
716 pending_events[i] |= events;
717 spin_unlock(&pending_event_lock);
718 /*
719 * Turn off RDY_L bits in the PER mask on
720 * CD interrupt receival.
721 *
722 * They can generate bad interrupts on the
723 * ACS4,8,16,32. - marcelo
724 */
725 per &= ~M8XX_PCMCIA_RDY_L(0);
726 per &= ~M8XX_PCMCIA_RDY_L(1);
727
728 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per);
729
730 if (events)
731 pcmcia_parse_events(&socket[i].socket, events);
732 }
733 }
734
735 /* clear the interrupt sources */
736 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr);
737
738 dprintk("Interrupt done.\n");
739
740 return IRQ_HANDLED;
741 }
742
743 static u32 m8xx_get_graycode(u32 size)
744 {
745 u32 k;
746
747 for(k = 0; k < M8XX_SIZES_NO; k++)
748 if(m8xx_size_to_gray[k] == size)
749 break;
750
751 if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
752 k = -1;
753
754 return k;
755 }
756
757 static u32 m8xx_get_speed(u32 ns, u32 is_io)
758 {
759 u32 reg, clocks, psst, psl, psht;
760
761 if(!ns) {
762
763 /*
764 * We get called with IO maps setup to 0ns
765 * if not specified by the user.
766 * They should be 255ns.
767 */
768
769 if(is_io)
770 ns = 255;
771 else
772 ns = 100; /* fast memory if 0 */
773 }
774
775 /*
776 * In PSST, PSL, PSHT fields we tell the controller
777 * timing parameters in CLKOUT clock cycles.
778 * CLKOUT is the same as GCLK2_50.
779 */
780
781 /* how we want to adjust the timing - in percent */
782
783 #define ADJ 180 /* 80 % longer accesstime - to be sure */
784
785 clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
786 clocks = (clocks * ADJ) / (100*1000);
787 if(clocks >= PCMCIA_BMT_LIMIT) {
788 printk( "Max access time limit reached\n");
789 clocks = PCMCIA_BMT_LIMIT-1;
790 }
791
792 psst = clocks / 7; /* setup time */
793 psht = clocks / 7; /* hold time */
794 psl = (clocks * 5) / 7; /* strobe length */
795
796 psst += clocks - (psst + psht + psl);
797
798 reg = psst << 12;
799 reg |= psl << 7;
800 reg |= psht << 16;
801
802 return reg;
803 }
804
805 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
806 {
807 int lsock = container_of(sock, struct socket_info, socket)->slot;
808 struct socket_info *s = &socket[lsock];
809 unsigned int pipr, reg;
810
811 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
812
813 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
814 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
815 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
816
817 if (s->state.flags & SS_IOCARD)
818 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
819 else {
820 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
821 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
822 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
823 }
824
825 if (s->state.Vcc | s->state.Vpp)
826 *value |= SS_POWERON;
827
828 /*
829 * Voltage detection:
830 * This driver only supports 16-Bit pc-cards.
831 * Cardbus is not handled here.
832 *
833 * To determine what voltage to use we must read the VS1 and VS2 pin.
834 * Depending on what socket type is present,
835 * different combinations mean different things.
836 *
837 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
838 *
839 * 5V 5V, LV* NC NC 5V only 5V (if available)
840 *
841 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
842 *
843 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
844 *
845 * LV* 5V - - shall not fit into socket
846 *
847 * LV* LV* GND NC 3.3V only 3.3V
848 *
849 * LV* LV* NC GND x.xV x.xV (if avail.)
850 *
851 * LV* LV* GND GND 3.3 or x.xV as low as possible
852 *
853 * *LV means Low Voltage
854 *
855 *
856 * That gives us the following table:
857 *
858 * Socket VS1 VS2 Voltage
859 *
860 * 5V NC NC 5V
861 * 5V NC GND none (should not be possible)
862 * 5V GND NC >= 3.3V
863 * 5V GND GND >= x.xV
864 *
865 * LV NC NC 5V (if available)
866 * LV NC GND x.xV (if available)
867 * LV GND NC 3.3V
868 * LV GND GND >= x.xV
869 *
870 * So, how do I determine if I have a 5V or a LV
871 * socket on my board? Look at the socket!
872 *
873 *
874 * Socket with 5V key:
875 * ++--------------------------------------------+
876 * || |
877 * || ||
878 * || ||
879 * | |
880 * +---------------------------------------------+
881 *
882 * Socket with LV key:
883 * ++--------------------------------------------+
884 * || |
885 * | ||
886 * | ||
887 * | |
888 * +---------------------------------------------+
889 *
890 *
891 * With other words - LV only cards does not fit
892 * into the 5V socket!
893 */
894
895 /* read out VS1 and VS2 */
896
897 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
898 >> M8XX_PCMCIA_VS_SHIFT(lsock);
899
900 if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
901 switch(reg) {
902 case 1:
903 *value |= SS_3VCARD;
904 break; /* GND, NC - 3.3V only */
905 case 2:
906 *value |= SS_XVCARD;
907 break; /* NC. GND - x.xV only */
908 };
909 }
910
911 dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
912 return 0;
913 }
914
915 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
916 {
917 int lsock = container_of(sock, struct socket_info, socket)->slot;
918 struct socket_info *s = &socket[lsock];
919 struct event_table *e;
920 unsigned int reg;
921 unsigned long flags;
922
923 dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
924 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
925 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
926
927 /* First, set voltage - bail out if invalid */
928 if(voltage_set(lsock, state->Vcc, state->Vpp))
929 return -EINVAL;
930
931 /* Take care of reset... */
932 if(state->flags & SS_RESET)
933 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
934 else
935 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
936
937 /* ... and output enable. */
938
939 /* The CxOE signal is connected to a 74541 on the ADS.
940 I guess most other boards used the ADS as a reference.
941 I tried to control the CxOE signal with SS_OUTPUT_ENA,
942 but the reset signal seems connected via the 541.
943 If the CxOE is left high are some signals tristated and
944 no pullups are present -> the cards act wierd.
945 So right now the buffers are enabled if the power is on. */
946
947 if(state->Vcc || state->Vpp)
948 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
949 else
950 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
951
952 /*
953 * We'd better turn off interrupts before
954 * we mess with the events-table..
955 */
956
957 spin_lock_irqsave(&events_lock, flags);
958
959 /*
960 * Play around with the interrupt mask to be able to
961 * give the events the generic pcmcia driver wants us to.
962 */
963
964 e = &s->events[0];
965 reg = 0;
966
967 if(state->csc_mask & SS_DETECT) {
968 e->eventbit = SS_DETECT;
969 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
970 | M8XX_PCMCIA_CD1(lsock));
971 e++;
972 }
973 if(state->flags & SS_IOCARD) {
974 /*
975 * I/O card
976 */
977 if(state->csc_mask & SS_STSCHG) {
978 e->eventbit = SS_STSCHG;
979 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
980 e++;
981 }
982 /*
983 * If io_irq is non-zero we should enable irq.
984 */
985 if(state->io_irq) {
986 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24);
987 /*
988 * Strange thing here:
989 * The manual does not tell us which interrupt
990 * the sources generate.
991 * Anyhow, I found out that RDY_L generates IREQLVL.
992 *
993 * We use level triggerd interrupts, and they don't
994 * have to be cleared in PSCR in the interrupt handler.
995 */
996 reg |= M8XX_PCMCIA_RDY_L(lsock);
997 }
998 else
999 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
1000 }
1001 else {
1002 /*
1003 * Memory card
1004 */
1005 if(state->csc_mask & SS_BATDEAD) {
1006 e->eventbit = SS_BATDEAD;
1007 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
1008 e++;
1009 }
1010 if(state->csc_mask & SS_BATWARN) {
1011 e->eventbit = SS_BATWARN;
1012 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
1013 e++;
1014 }
1015 /* What should I trigger on - low/high,raise,fall? */
1016 if(state->csc_mask & SS_READY) {
1017 e->eventbit = SS_READY;
1018 reg |= e->regbit = 0; //??
1019 e++;
1020 }
1021 }
1022
1023 e->regbit = 0; /* terminate list */
1024
1025 /*
1026 * Clear the status changed .
1027 * Port A and Port B share the same port.
1028 * Writing ones will clear the bits.
1029 */
1030
1031 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg);
1032
1033 /*
1034 * Write the mask.
1035 * Port A and Port B share the same port.
1036 * Need for read-modify-write.
1037 * Ones will enable the interrupt.
1038 */
1039
1040 /*
1041 reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
1042 & M8XX_PCMCIA_MASK(lsock);
1043 */
1044
1045 reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
1046 (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1047
1048 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg);
1049
1050 spin_unlock_irqrestore(&events_lock, flags);
1051
1052 /* copy the struct and modify the copy */
1053
1054 s->state = *state;
1055
1056 return 0;
1057 }
1058
1059 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
1060 {
1061 int lsock = container_of(sock, struct socket_info, socket)->slot;
1062
1063 struct socket_info *s = &socket[lsock];
1064 struct pcmcia_win *w;
1065 unsigned int reg, winnr;
1066
1067 #define M8XX_SIZE (io->stop - io->start + 1)
1068 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
1069
1070 dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
1071 "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
1072 io->speed, io->start, io->stop);
1073
1074 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
1075 || (io->stop > 0xffff) || (io->stop < io->start))
1076 return -EINVAL;
1077
1078 if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
1079 return -EINVAL;
1080
1081 if(io->flags & MAP_ACTIVE) {
1082
1083 dprintk( "io->flags & MAP_ACTIVE\n");
1084
1085 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1086 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1087
1088 /* setup registers */
1089
1090 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1091 w += winnr;
1092
1093 out_be32(&w->or, 0); /* turn off window first */
1094 out_be32(&w->br, M8XX_BASE);
1095
1096 reg <<= 27;
1097 reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
1098
1099 reg |= m8xx_get_speed(io->speed, 1);
1100
1101 if(io->flags & MAP_WRPROT)
1102 reg |= M8XX_PCMCIA_POR_WRPROT;
1103
1104 if(io->flags & (MAP_16BIT | MAP_AUTOSZ))
1105 reg |= M8XX_PCMCIA_POR_16BIT;
1106
1107 if(io->flags & MAP_ACTIVE)
1108 reg |= M8XX_PCMCIA_POR_VALID;
1109
1110 out_be32(&w->or, reg);
1111
1112 dprintk("Socket %u: Mapped io window %u at %#8.8x, "
1113 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1114 } else {
1115 /* shutdown IO window */
1116 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1117 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1118
1119 /* setup registers */
1120
1121 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1122 w += winnr;
1123
1124 out_be32(&w->or, 0); /* turn off window */
1125 out_be32(&w->br, 0); /* turn off base address */
1126
1127 dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
1128 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1129 }
1130
1131 /* copy the struct and modify the copy */
1132 s->io_win[io->map] = *io;
1133 s->io_win[io->map].flags &= (MAP_WRPROT
1134 | MAP_16BIT
1135 | MAP_ACTIVE);
1136 dprintk("SetIOMap exit\n");
1137
1138 return 0;
1139 }
1140
1141 static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
1142 {
1143 int lsock = container_of(sock, struct socket_info, socket)->slot;
1144 struct socket_info *s = &socket[lsock];
1145 struct pcmcia_win *w;
1146 struct pccard_mem_map *old;
1147 unsigned int reg, winnr;
1148
1149 dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
1150 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1151 mem->speed, mem->static_start, mem->card_start);
1152
1153 if ((mem->map >= PCMCIA_MEM_WIN_NO)
1154 // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1155 || (mem->card_start >= 0x04000000)
1156 || (mem->static_start & 0xfff) /* 4KByte resolution */
1157 || (mem->card_start & 0xfff))
1158 return -EINVAL;
1159
1160 if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1161 printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1162 return -EINVAL;
1163 }
1164 reg <<= 27;
1165
1166 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1167
1168 /* Setup the window in the pcmcia controller */
1169
1170 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1171 w += winnr;
1172
1173 reg |= lsock << 2;
1174
1175 reg |= m8xx_get_speed(mem->speed, 0);
1176
1177 if(mem->flags & MAP_ATTRIB)
1178 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1179
1180 if(mem->flags & MAP_WRPROT)
1181 reg |= M8XX_PCMCIA_POR_WRPROT;
1182
1183 if(mem->flags & MAP_16BIT)
1184 reg |= M8XX_PCMCIA_POR_16BIT;
1185
1186 if(mem->flags & MAP_ACTIVE)
1187 reg |= M8XX_PCMCIA_POR_VALID;
1188
1189 out_be32(&w->or, reg);
1190
1191 dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
1192 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1193
1194 if(mem->flags & MAP_ACTIVE) {
1195 /* get the new base address */
1196 mem->static_start = PCMCIA_MEM_WIN_BASE +
1197 (PCMCIA_MEM_WIN_SIZE * winnr)
1198 + mem->card_start;
1199 }
1200
1201 dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1202 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1203 mem->speed, mem->static_start, mem->card_start);
1204
1205 /* copy the struct and modify the copy */
1206
1207 old = &s->mem_win[mem->map];
1208
1209 *old = *mem;
1210 old->flags &= (MAP_ATTRIB
1211 | MAP_WRPROT
1212 | MAP_16BIT
1213 | MAP_ACTIVE);
1214
1215 return 0;
1216 }
1217
1218 static int m8xx_sock_init(struct pcmcia_socket *sock)
1219 {
1220 int i;
1221 pccard_io_map io = { 0, 0, 0, 0, 1 };
1222 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1223
1224 dprintk( "sock_init(%d)\n", s);
1225
1226 m8xx_set_socket(sock, &dead_socket);
1227 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1228 io.map = i;
1229 m8xx_set_io_map(sock, &io);
1230 }
1231 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1232 mem.map = i;
1233 m8xx_set_mem_map(sock, &mem);
1234 }
1235
1236 return 0;
1237
1238 }
1239
1240 static int m8xx_suspend(struct pcmcia_socket *sock)
1241 {
1242 return m8xx_set_socket(sock, &dead_socket);
1243 }
1244
1245 static struct pccard_operations m8xx_services = {
1246 .init = m8xx_sock_init,
1247 .suspend = m8xx_suspend,
1248 .get_status = m8xx_get_status,
1249 .set_socket = m8xx_set_socket,
1250 .set_io_map = m8xx_set_io_map,
1251 .set_mem_map = m8xx_set_mem_map,
1252 };
1253
1254 static int __init m8xx_init(void)
1255 {
1256 struct pcmcia_win *w;
1257 unsigned int i,m;
1258
1259 pcmcia_info("%s\n", version);
1260
1261 if (driver_register(&m8xx_driver))
1262 return -1;
1263
1264 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1265 " with IRQ %u.\n", pcmcia_schlvl);
1266
1267 /* Configure Status change interrupt */
1268
1269 if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0,
1270 "m8xx_pcmcia", NULL)) {
1271 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1272 pcmcia_schlvl);
1273 return -1;
1274 }
1275
1276 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1277
1278 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr,
1279 M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
1280
1281 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per,
1282 in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
1283 ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)));
1284
1285 /* connect interrupt and disable CxOE */
1286
1287 out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
1288 out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
1289
1290 /* intialize the fixed memory windows */
1291
1292 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
1293 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1294 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1295 (PCMCIA_MEM_WIN_SIZE
1296 * (m + i * PCMCIA_MEM_WIN_NO)));
1297
1298 out_be32(&w->or, 0); /* set to not valid */
1299
1300 w++;
1301 }
1302 }
1303
1304 /* turn off voltage */
1305 voltage_set(0, 0, 0);
1306 voltage_set(1, 0, 0);
1307
1308 /* Enable external hardware */
1309 hardware_enable(0);
1310 hardware_enable(1);
1311
1312 platform_device_register(&m8xx_device);
1313
1314 for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
1315 socket[i].slot = i;
1316 socket[i].socket.owner = THIS_MODULE;
1317 socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1318 socket[i].socket.irq_mask = 0x000;
1319 socket[i].socket.map_size = 0x1000;
1320 socket[i].socket.io_offset = 0;
1321 socket[i].socket.pci_irq = i ? 7 : 9;
1322 socket[i].socket.ops = &m8xx_services;
1323 socket[i].socket.resource_ops = &pccard_iodyn_ops;
1324 socket[i].socket.cb_dev = NULL;
1325 socket[i].socket.dev.dev = &m8xx_device.dev;
1326 }
1327
1328 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1329 pcmcia_register_socket(&socket[i].socket);
1330
1331 return 0;
1332 }
1333
1334 static void __exit m8xx_exit(void)
1335 {
1336 int i;
1337
1338 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1339 pcmcia_unregister_socket(&socket[i].socket);
1340
1341 m8xx_shutdown();
1342
1343 platform_device_unregister(&m8xx_device);
1344 driver_unregister(&m8xx_driver);
1345 }
1346
1347 module_init(m8xx_init);
1348 module_exit(m8xx_exit);
Linux with added FPC-III support