arch/mips/kernel/proc.c

   1 /*
   2  *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
   3  *  Copyright (C) 2001, 2004  MIPS Technologies, Inc.
   4  *  Copyright (C) 2004  Maciej W. Rozycki
   5  */
   6 #include <linux/delay.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/seq_file.h>
  10 #include <asm/bootinfo.h>
  11 #include <asm/cpu.h>
  12 #include <asm/cpu-features.h>
  13 #include <asm/idle.h>
  14 #include <asm/mipsregs.h>
  15 #include <asm/processor.h>
  16 #include <asm/prom.h>
  17
  18 unsigned int vced_count, vcei_count;
  19
  20 /*
  21  *  * No lock; only written during early bootup by CPU 0.
  22  *   */
  23 static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
  24
  25 int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
  26 {
  27         return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
  28 }
  29
  30 int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
  31 {
  32         return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
  33 }
  34
  35 static int show_cpuinfo(struct seq_file *m, void *v)
  36 {
  37         struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
  38         unsigned long n = (unsigned long) v - 1;
  39         unsigned int version = cpu_data[n].processor_id;
  40         unsigned int fp_vers = cpu_data[n].fpu_id;
  41         char fmt [64];
  42         int i;
  43
  44 #ifdef CONFIG_SMP
  45         if (!cpu_online(n))
  46                 return 0;
  47 #endif
  48
  49         /*
  50          * For the first processor also print the system type
  51          */
  52         if (n == 0) {
  53                 seq_printf(m, "system type\t\t: %s\n", get_system_type());
  54                 if (mips_get_machine_name())
  55                         seq_printf(m, "machine\t\t\t: %s\n",
  56                                    mips_get_machine_name());
  57         }
  58
  59         seq_printf(m, "processor\t\t: %ld\n", n);
  60         sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
  61                       cpu_data[n].options & MIPS_CPU_FPU ? "  FPU V%d.%d" : "");
  62         seq_printf(m, fmt, __cpu_name[n],
  63                       (version >> 4) & 0x0f, version & 0x0f,
  64                       (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
  65         seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
  66                       cpu_data[n].udelay_val / (500000/HZ),
  67                       (cpu_data[n].udelay_val / (5000/HZ)) % 100);
  68         seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
  69         seq_printf(m, "microsecond timers\t: %s\n",
  70                       cpu_has_counter ? "yes" : "no");
  71         seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
  72         seq_printf(m, "extra interrupt vector\t: %s\n",
  73                       cpu_has_divec ? "yes" : "no");
  74         seq_printf(m, "hardware watchpoint\t: %s",
  75                       cpu_has_watch ? "yes, " : "no\n");
  76         if (cpu_has_watch) {
  77                 seq_printf(m, "count: %d, address/irw mask: [",
  78                       cpu_data[n].watch_reg_count);
  79                 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
  80                         seq_printf(m, "%s0x%04x", i ? ", " : "" ,
  81                                 cpu_data[n].watch_reg_masks[i]);
  82                 seq_printf(m, "]\n");
  83         }
  84
  85         seq_printf(m, "isa\t\t\t:");
  86         if (cpu_has_mips_r1)
  87                 seq_printf(m, " mips1");
  88         if (cpu_has_mips_2)
  89                 seq_printf(m, "%s", " mips2");
  90         if (cpu_has_mips_3)
  91                 seq_printf(m, "%s", " mips3");
  92         if (cpu_has_mips_4)
  93                 seq_printf(m, "%s", " mips4");
  94         if (cpu_has_mips_5)
  95                 seq_printf(m, "%s", " mips5");
  96         if (cpu_has_mips32r1)
  97                 seq_printf(m, "%s", " mips32r1");
  98         if (cpu_has_mips32r2)
  99                 seq_printf(m, "%s", " mips32r2");
 100         if (cpu_has_mips32r6)
 101                 seq_printf(m, "%s", " mips32r6");
 102         if (cpu_has_mips64r1)
 103                 seq_printf(m, "%s", " mips64r1");
 104         if (cpu_has_mips64r2)
 105                 seq_printf(m, "%s", " mips64r2");
 106         if (cpu_has_mips64r6)
 107                 seq_printf(m, "%s", " mips64r6");
 108         seq_printf(m, "\n");
 109
 110         seq_printf(m, "ASEs implemented\t:");
 111         if (cpu_has_mips16)     seq_printf(m, "%s", " mips16");
 112         if (cpu_has_mdmx)       seq_printf(m, "%s", " mdmx");
 113         if (cpu_has_mips3d)     seq_printf(m, "%s", " mips3d");
 114         if (cpu_has_smartmips)  seq_printf(m, "%s", " smartmips");
 115         if (cpu_has_dsp)        seq_printf(m, "%s", " dsp");
 116         if (cpu_has_dsp2)       seq_printf(m, "%s", " dsp2");
 117         if (cpu_has_dsp3)       seq_printf(m, "%s", " dsp3");
 118         if (cpu_has_mipsmt)     seq_printf(m, "%s", " mt");
 119         if (cpu_has_mmips)      seq_printf(m, "%s", " micromips");
 120         if (cpu_has_vz)         seq_printf(m, "%s", " vz");
 121         if (cpu_has_msa)        seq_printf(m, "%s", " msa");
 122         if (cpu_has_eva)        seq_printf(m, "%s", " eva");
 123         if (cpu_has_htw)        seq_printf(m, "%s", " htw");
 124         if (cpu_has_xpa)        seq_printf(m, "%s", " xpa");
 125         seq_printf(m, "\n");
 126
 127         if (cpu_has_mmips) {
 128                 seq_printf(m, "micromips kernel\t: %s\n",
 129                       (read_c0_config3() & MIPS_CONF3_ISA_OE) ?  "yes" : "no");
 130         }
 131         seq_printf(m, "shadow register sets\t: %d\n",
 132                       cpu_data[n].srsets);
 133         seq_printf(m, "kscratch registers\t: %d\n",
 134                       hweight8(cpu_data[n].kscratch_mask));
 135         seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
 136         seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
 137
 138 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
 139         if (cpu_has_mipsmt)
 140                 seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
 141         else if (cpu_has_vp)
 142                 seq_printf(m, "VP\t\t\t: %d\n", cpu_data[n].vpe_id);
 143 #endif
 144
 145         sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
 146                       cpu_has_vce ? "%u" : "not available");
 147         seq_printf(m, fmt, 'D', vced_count);
 148         seq_printf(m, fmt, 'I', vcei_count);
 149
 150         proc_cpuinfo_notifier_args.m = m;
 151         proc_cpuinfo_notifier_args.n = n;
 152
 153         raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
 154                                 &proc_cpuinfo_notifier_args);
 155
 156         seq_printf(m, "\n");
 157
 158         return 0;
 159 }
 160
 161 static void *c_start(struct seq_file *m, loff_t *pos)
 162 {
 163         unsigned long i = *pos;
 164
 165         return i < NR_CPUS ? (void *) (i + 1) : NULL;
 166 }
 167
 168 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 169 {
 170         ++*pos;
 171         return c_start(m, pos);
 172 }
 173
 174 static void c_stop(struct seq_file *m, void *v)
 175 {
 176 }
 177
 178 const struct seq_operations cpuinfo_op = {
 179         .start  = c_start,
 180         .next   = c_next,
 181         .stop   = c_stop,
 182         .show   = show_cpuinfo,
 183 };