staging: octeon-usb: remove useless prefix from pipe flags
[linux/fpc-iii.git] / drivers / staging / octeon-usb / octeon-hcd.c
blobd0f346cf8e89c9ffc8e39d4e66316fe6746f99ee
1 /*
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3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2008 Cavium Networks
8 * Some parts of the code were originally released under BSD license:
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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15 * met:
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46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/prefetch.h>
51 #include <linux/interrupt.h>
52 #include <linux/platform_device.h>
53 #include <linux/usb.h>
55 #include <linux/time.h>
56 #include <linux/delay.h>
58 #include <asm/octeon/cvmx.h>
59 #include <asm/octeon/cvmx-iob-defs.h>
61 #include <linux/usb/hcd.h>
63 #include <linux/err.h>
65 #include <asm/octeon/octeon.h>
66 #include <asm/octeon/cvmx-helper.h>
67 #include <asm/octeon/cvmx-sysinfo.h>
68 #include <asm/octeon/cvmx-helper-board.h>
70 #include "octeon-hcd.h"
72 /**
73 * enum cvmx_usb_speed - the possible USB device speeds
75 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
76 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
77 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
79 enum cvmx_usb_speed {
80 CVMX_USB_SPEED_HIGH = 0,
81 CVMX_USB_SPEED_FULL = 1,
82 CVMX_USB_SPEED_LOW = 2,
85 /**
86 * enum cvmx_usb_transfer - the possible USB transfer types
88 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
89 * transfers
90 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
91 * priority periodic transfers
92 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
93 * transfers
94 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
95 * periodic transfers
97 enum cvmx_usb_transfer {
98 CVMX_USB_TRANSFER_CONTROL = 0,
99 CVMX_USB_TRANSFER_ISOCHRONOUS = 1,
100 CVMX_USB_TRANSFER_BULK = 2,
101 CVMX_USB_TRANSFER_INTERRUPT = 3,
105 * enum cvmx_usb_direction - the transfer directions
107 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
108 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
110 enum cvmx_usb_direction {
111 CVMX_USB_DIRECTION_OUT,
112 CVMX_USB_DIRECTION_IN,
116 * enum cvmx_usb_complete - possible callback function status codes
118 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
119 * any errors
120 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
121 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
122 * by a user call to cvmx_usb_cancel
123 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
124 * error status
125 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
126 * from the device
127 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
128 * device even after a number of retries
129 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
130 * error even after a number of retries
131 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
132 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
133 * even after a number of retries
135 enum cvmx_usb_complete {
136 CVMX_USB_COMPLETE_SUCCESS,
137 CVMX_USB_COMPLETE_SHORT,
138 CVMX_USB_COMPLETE_CANCEL,
139 CVMX_USB_COMPLETE_ERROR,
140 CVMX_USB_COMPLETE_STALL,
141 CVMX_USB_COMPLETE_XACTERR,
142 CVMX_USB_COMPLETE_DATATGLERR,
143 CVMX_USB_COMPLETE_BABBLEERR,
144 CVMX_USB_COMPLETE_FRAMEERR,
148 * struct cvmx_usb_port_status - the USB port status information
150 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
151 * @port_over_current: 1 = Over current detected, 0 = Over current not
152 * detected. Octeon doesn't support over current detection.
153 * @port_powered: 1 = Port power is being supplied to the device, 0 =
154 * power is off. Octeon doesn't support turning port power
155 * off.
156 * @port_speed: Current port speed.
157 * @connected: 1 = A device is connected to the port, 0 = No device is
158 * connected.
159 * @connect_change: 1 = Device connected state changed since the last set
160 * status call.
162 struct cvmx_usb_port_status {
163 uint32_t reserved : 25;
164 uint32_t port_enabled : 1;
165 uint32_t port_over_current : 1;
166 uint32_t port_powered : 1;
167 enum cvmx_usb_speed port_speed : 2;
168 uint32_t connected : 1;
169 uint32_t connect_change : 1;
173 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
175 * @offset: This is the offset in bytes into the main buffer where this data
176 * is stored.
177 * @length: This is the length in bytes of the data.
178 * @status: This is the status of this individual packet transfer.
180 struct cvmx_usb_iso_packet {
181 int offset;
182 int length;
183 enum cvmx_usb_complete status;
187 * enum cvmx_usb_initialize_flags - flags used by the initialization function
189 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
190 * as clock source at USB_XO and
191 * USB_XI.
192 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
193 * board clock source at USB_XO.
194 * USB_XI should be tied to GND.
195 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
196 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
197 * crystal
198 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
199 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
200 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
201 * data transfer use for the USB
203 enum cvmx_usb_initialize_flags {
204 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0,
205 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1,
206 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3,
207 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3,
208 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3,
209 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3,
210 /* Bits 3-4 used to encode the clock frequency */
211 CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5,
215 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
217 * @CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
218 * actively using hardware.
219 * @CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high speed
220 * pipe is in the ping state.
222 enum cvmx_usb_pipe_flags {
223 CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17,
224 CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18,
227 /* Maximum number of times to retry failed transactions */
228 #define MAX_RETRIES 3
230 /* Maximum number of hardware channels supported by the USB block */
231 #define MAX_CHANNELS 8
234 * The low level hardware can transfer a maximum of this number of bytes in each
235 * transfer. The field is 19 bits wide
237 #define MAX_TRANSFER_BYTES ((1<<19)-1)
240 * The low level hardware can transfer a maximum of this number of packets in
241 * each transfer. The field is 10 bits wide
243 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
246 * Logical transactions may take numerous low level
247 * transactions, especially when splits are concerned. This
248 * enum represents all of the possible stages a transaction can
249 * be in. Note that split completes are always even. This is so
250 * the NAK handler can backup to the previous low level
251 * transaction with a simple clearing of bit 0.
253 enum cvmx_usb_stage {
254 CVMX_USB_STAGE_NON_CONTROL,
255 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
256 CVMX_USB_STAGE_SETUP,
257 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
258 CVMX_USB_STAGE_DATA,
259 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
260 CVMX_USB_STAGE_STATUS,
261 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
265 * struct cvmx_usb_transaction - describes each pending USB transaction
266 * regardless of type. These are linked together
267 * to form a list of pending requests for a pipe.
269 * @node: List node for transactions in the pipe.
270 * @type: Type of transaction, duplicated of the pipe.
271 * @flags: State flags for this transaction.
272 * @buffer: User's physical buffer address to read/write.
273 * @buffer_length: Size of the user's buffer in bytes.
274 * @control_header: For control transactions, physical address of the 8
275 * byte standard header.
276 * @iso_start_frame: For ISO transactions, the starting frame number.
277 * @iso_number_packets: For ISO transactions, the number of packets in the
278 * request.
279 * @iso_packets: For ISO transactions, the sub packets in the request.
280 * @actual_bytes: Actual bytes transfer for this transaction.
281 * @stage: For control transactions, the current stage.
282 * @urb: URB.
284 struct cvmx_usb_transaction {
285 struct list_head node;
286 enum cvmx_usb_transfer type;
287 uint64_t buffer;
288 int buffer_length;
289 uint64_t control_header;
290 int iso_start_frame;
291 int iso_number_packets;
292 struct cvmx_usb_iso_packet *iso_packets;
293 int xfersize;
294 int pktcnt;
295 int retries;
296 int actual_bytes;
297 enum cvmx_usb_stage stage;
298 struct urb *urb;
302 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
303 * and some USB device. It contains a list of pending
304 * request to the device.
306 * @node: List node for pipe list
307 * @next: Pipe after this one in the list
308 * @transactions: List of pending transactions
309 * @interval: For periodic pipes, the interval between packets in
310 * frames
311 * @next_tx_frame: The next frame this pipe is allowed to transmit on
312 * @flags: State flags for this pipe
313 * @device_speed: Speed of device connected to this pipe
314 * @transfer_type: Type of transaction supported by this pipe
315 * @transfer_dir: IN or OUT. Ignored for Control
316 * @multi_count: Max packet in a row for the device
317 * @max_packet: The device's maximum packet size in bytes
318 * @device_addr: USB device address at other end of pipe
319 * @endpoint_num: USB endpoint number at other end of pipe
320 * @hub_device_addr: Hub address this device is connected to
321 * @hub_port: Hub port this device is connected to
322 * @pid_toggle: This toggles between 0/1 on every packet send to track
323 * the data pid needed
324 * @channel: Hardware DMA channel for this pipe
325 * @split_sc_frame: The low order bits of the frame number the split
326 * complete should be sent on
328 struct cvmx_usb_pipe {
329 struct list_head node;
330 struct list_head transactions;
331 uint64_t interval;
332 uint64_t next_tx_frame;
333 enum cvmx_usb_pipe_flags flags;
334 enum cvmx_usb_speed device_speed;
335 enum cvmx_usb_transfer transfer_type;
336 enum cvmx_usb_direction transfer_dir;
337 int multi_count;
338 uint16_t max_packet;
339 uint8_t device_addr;
340 uint8_t endpoint_num;
341 uint8_t hub_device_addr;
342 uint8_t hub_port;
343 uint8_t pid_toggle;
344 uint8_t channel;
345 int8_t split_sc_frame;
348 struct cvmx_usb_tx_fifo {
349 struct {
350 int channel;
351 int size;
352 uint64_t address;
353 } entry[MAX_CHANNELS+1];
354 int head;
355 int tail;
359 * struct cvmx_usb_state - the state of the USB block
361 * init_flags: Flags passed to initialize.
362 * index: Which USB block this is for.
363 * idle_hardware_channels: Bit set for every idle hardware channel.
364 * usbcx_hprt: Stored port status so we don't need to read a CSR to
365 * determine splits.
366 * pipe_for_channel: Map channels to pipes.
367 * pipe: Storage for pipes.
368 * indent: Used by debug output to indent functions.
369 * port_status: Last port status used for change notification.
370 * idle_pipes: List of open pipes that have no transactions.
371 * active_pipes: Active pipes indexed by transfer type.
372 * frame_number: Increments every SOF interrupt for time keeping.
373 * active_split: Points to the current active split, or NULL.
375 struct cvmx_usb_state {
376 int init_flags;
377 int index;
378 int idle_hardware_channels;
379 union cvmx_usbcx_hprt usbcx_hprt;
380 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
381 int indent;
382 struct cvmx_usb_port_status port_status;
383 struct list_head idle_pipes;
384 struct list_head active_pipes[4];
385 uint64_t frame_number;
386 struct cvmx_usb_transaction *active_split;
387 struct cvmx_usb_tx_fifo periodic;
388 struct cvmx_usb_tx_fifo nonperiodic;
391 struct octeon_hcd {
392 spinlock_t lock;
393 struct cvmx_usb_state usb;
396 /* This macro spins on a field waiting for it to reach a value */
397 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
398 ({int result; \
399 do { \
400 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
401 octeon_get_clock_rate() / 1000000; \
402 type c; \
403 while (1) { \
404 c.u32 = cvmx_usb_read_csr32(usb, address); \
405 if (c.s.field op (value)) { \
406 result = 0; \
407 break; \
408 } else if (cvmx_get_cycle() > done) { \
409 result = -1; \
410 break; \
411 } else \
412 cvmx_wait(100); \
414 } while (0); \
415 result; })
418 * This macro logically sets a single field in a CSR. It does the sequence
419 * read, modify, and write
421 #define USB_SET_FIELD32(address, type, field, value) \
422 do { \
423 type c; \
424 c.u32 = cvmx_usb_read_csr32(usb, address); \
425 c.s.field = value; \
426 cvmx_usb_write_csr32(usb, address, c.u32); \
427 } while (0)
429 /* Returns the IO address to push/pop stuff data from the FIFOs */
430 #define USB_FIFO_ADDRESS(channel, usb_index) \
431 (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
434 * struct octeon_temp_buffer - a bounce buffer for USB transfers
435 * @temp_buffer: the newly allocated temporary buffer (including meta-data)
436 * @orig_buffer: the original buffer passed by the USB stack
437 * @data: the newly allocated temporary buffer (excluding meta-data)
439 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If
440 * the buffer is too short, we need to allocate a temporary one, and this struct
441 * represents it.
443 struct octeon_temp_buffer {
444 void *temp_buffer;
445 void *orig_buffer;
446 u8 data[0];
449 static inline struct octeon_hcd *cvmx_usb_to_octeon(struct cvmx_usb_state *p)
451 return container_of(p, struct octeon_hcd, usb);
454 static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p)
456 return container_of((void *)p, struct usb_hcd, hcd_priv);
460 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer
461 * (if needed)
462 * @urb: URB.
463 * @mem_flags: Memory allocation flags.
465 * This function allocates a temporary bounce buffer whenever it's needed
466 * due to HW limitations.
468 static int octeon_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
470 struct octeon_temp_buffer *temp;
472 if (urb->num_sgs || urb->sg ||
473 (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) ||
474 !(urb->transfer_buffer_length % sizeof(u32)))
475 return 0;
477 temp = kmalloc(ALIGN(urb->transfer_buffer_length, sizeof(u32)) +
478 sizeof(*temp), mem_flags);
479 if (!temp)
480 return -ENOMEM;
482 temp->temp_buffer = temp;
483 temp->orig_buffer = urb->transfer_buffer;
484 if (usb_urb_dir_out(urb))
485 memcpy(temp->data, urb->transfer_buffer,
486 urb->transfer_buffer_length);
487 urb->transfer_buffer = temp->data;
488 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
490 return 0;
494 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers.
495 * @urb: URB.
497 * Frees a buffer allocated by octeon_alloc_temp_buffer().
499 static void octeon_free_temp_buffer(struct urb *urb)
501 struct octeon_temp_buffer *temp;
503 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
504 return;
506 temp = container_of(urb->transfer_buffer, struct octeon_temp_buffer,
507 data);
508 if (usb_urb_dir_in(urb))
509 memcpy(temp->orig_buffer, urb->transfer_buffer,
510 urb->actual_length);
511 urb->transfer_buffer = temp->orig_buffer;
512 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
513 kfree(temp->temp_buffer);
517 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma().
518 * @hcd: USB HCD structure.
519 * @urb: URB.
520 * @mem_flags: Memory allocation flags.
522 static int octeon_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
523 gfp_t mem_flags)
525 int ret;
527 ret = octeon_alloc_temp_buffer(urb, mem_flags);
528 if (ret)
529 return ret;
531 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
532 if (ret)
533 octeon_free_temp_buffer(urb);
535 return ret;
539 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma()
540 * @hcd: USB HCD structure.
541 * @urb: URB.
543 static void octeon_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
545 usb_hcd_unmap_urb_for_dma(hcd, urb);
546 octeon_free_temp_buffer(urb);
550 * Read a USB 32bit CSR. It performs the necessary address swizzle
551 * for 32bit CSRs and logs the value in a readable format if
552 * debugging is on.
554 * @usb: USB block this access is for
555 * @address: 64bit address to read
557 * Returns: Result of the read
559 static inline uint32_t cvmx_usb_read_csr32(struct cvmx_usb_state *usb,
560 uint64_t address)
562 uint32_t result = cvmx_read64_uint32(address ^ 4);
563 return result;
568 * Write a USB 32bit CSR. It performs the necessary address
569 * swizzle for 32bit CSRs and logs the value in a readable format
570 * if debugging is on.
572 * @usb: USB block this access is for
573 * @address: 64bit address to write
574 * @value: Value to write
576 static inline void cvmx_usb_write_csr32(struct cvmx_usb_state *usb,
577 uint64_t address, uint32_t value)
579 cvmx_write64_uint32(address ^ 4, value);
580 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
584 * Return non zero if this pipe connects to a non HIGH speed
585 * device through a high speed hub.
587 * @usb: USB block this access is for
588 * @pipe: Pipe to check
590 * Returns: Non zero if we need to do split transactions
592 static inline int cvmx_usb_pipe_needs_split(struct cvmx_usb_state *usb,
593 struct cvmx_usb_pipe *pipe)
595 return pipe->device_speed != CVMX_USB_SPEED_HIGH &&
596 usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH;
601 * Trivial utility function to return the correct PID for a pipe
603 * @pipe: pipe to check
605 * Returns: PID for pipe
607 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
609 if (pipe->pid_toggle)
610 return 2; /* Data1 */
611 return 0; /* Data0 */
615 * Initialize a USB port for use. This must be called before any
616 * other access to the Octeon USB port is made. The port starts
617 * off in the disabled state.
619 * @usb: Pointer to an empty struct cvmx_usb_state
620 * that will be populated by the initialize call.
621 * This structure is then passed to all other USB
622 * functions.
623 * @usb_port_number:
624 * Which Octeon USB port to initialize.
626 * Returns: 0 or a negative error code.
628 static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
629 int usb_port_number,
630 enum cvmx_usb_initialize_flags flags)
632 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
633 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
634 int i;
636 memset(usb, 0, sizeof(*usb));
637 usb->init_flags = flags;
639 /* Initialize the USB state structure */
640 usb->index = usb_port_number;
641 INIT_LIST_HEAD(&usb->idle_pipes);
642 for (i = 0; i < ARRAY_SIZE(usb->active_pipes); i++)
643 INIT_LIST_HEAD(&usb->active_pipes[i]);
646 * Power On Reset and PHY Initialization
648 * 1. Wait for DCOK to assert (nothing to do)
650 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
651 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
653 usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index));
654 usbn_clk_ctl.s.por = 1;
655 usbn_clk_ctl.s.hrst = 0;
656 usbn_clk_ctl.s.prst = 0;
657 usbn_clk_ctl.s.hclk_rst = 0;
658 usbn_clk_ctl.s.enable = 0;
660 * 2b. Select the USB reference clock/crystal parameters by writing
661 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
663 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
665 * The USB port uses 12/24/48MHz 2.5V board clock
666 * source at USB_XO. USB_XI should be tied to GND.
667 * Most Octeon evaluation boards require this setting
669 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) ||
670 OCTEON_IS_MODEL(OCTEON_CN56XX) ||
671 OCTEON_IS_MODEL(OCTEON_CN50XX))
672 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
673 usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */
674 else
675 /* From CN52XX manual */
676 usbn_clk_ctl.s.p_rtype = 1;
678 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
679 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
680 usbn_clk_ctl.s.p_c_sel = 0;
681 break;
682 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
683 usbn_clk_ctl.s.p_c_sel = 1;
684 break;
685 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
686 usbn_clk_ctl.s.p_c_sel = 2;
687 break;
689 } else {
691 * The USB port uses a 12MHz crystal as clock source
692 * at USB_XO and USB_XI
694 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
695 /* From CN31XX,CN30XX manual */
696 usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */
697 else
698 /* From CN56XX,CN52XX,CN50XX manuals. */
699 usbn_clk_ctl.s.p_rtype = 0;
701 usbn_clk_ctl.s.p_c_sel = 0;
704 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
705 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
706 * such that USB is as close as possible to 125Mhz
709 int divisor = DIV_ROUND_UP(octeon_get_clock_rate(), 125000000);
710 /* Lower than 4 doesn't seem to work properly */
711 if (divisor < 4)
712 divisor = 4;
713 usbn_clk_ctl.s.divide = divisor;
714 usbn_clk_ctl.s.divide2 = 0;
716 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
717 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
718 usbn_clk_ctl.s.hclk_rst = 1;
719 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
720 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
721 cvmx_wait(64);
723 * 3. Program the power-on reset field in the USBN clock-control
724 * register:
725 * USBN_CLK_CTL[POR] = 0
727 usbn_clk_ctl.s.por = 0;
728 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
729 /* 4. Wait 1 ms for PHY clock to start */
730 mdelay(1);
732 * 5. Program the Reset input from automatic test equipment field in the
733 * USBP control and status register:
734 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
736 usbn_usbp_ctl_status.u64 =
737 cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index));
738 usbn_usbp_ctl_status.s.ate_reset = 1;
739 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
740 usbn_usbp_ctl_status.u64);
741 /* 6. Wait 10 cycles */
742 cvmx_wait(10);
744 * 7. Clear ATE_RESET field in the USBN clock-control register:
745 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
747 usbn_usbp_ctl_status.s.ate_reset = 0;
748 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
749 usbn_usbp_ctl_status.u64);
751 * 8. Program the PHY reset field in the USBN clock-control register:
752 * USBN_CLK_CTL[PRST] = 1
754 usbn_clk_ctl.s.prst = 1;
755 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
757 * 9. Program the USBP control and status register to select host or
758 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
759 * device
761 usbn_usbp_ctl_status.s.hst_mode = 0;
762 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
763 usbn_usbp_ctl_status.u64);
764 /* 10. Wait 1 us */
765 udelay(1);
767 * 11. Program the hreset_n field in the USBN clock-control register:
768 * USBN_CLK_CTL[HRST] = 1
770 usbn_clk_ctl.s.hrst = 1;
771 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
772 /* 12. Proceed to USB core initialization */
773 usbn_clk_ctl.s.enable = 1;
774 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
775 udelay(1);
778 * USB Core Initialization
780 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
781 * determine USB core configuration parameters.
783 * Nothing needed
785 * 2. Program the following fields in the global AHB configuration
786 * register (USBC_GAHBCFG)
787 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
788 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
789 * Nonperiodic TxFIFO empty level (slave mode only),
790 * USBC_GAHBCFG[NPTXFEMPLVL]
791 * Periodic TxFIFO empty level (slave mode only),
792 * USBC_GAHBCFG[PTXFEMPLVL]
793 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
796 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
797 /* Due to an errata, CN31XX doesn't support DMA */
798 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
799 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
800 usbcx_gahbcfg.u32 = 0;
801 usbcx_gahbcfg.s.dmaen = !(usb->init_flags &
802 CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
803 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
804 /* Only use one channel with non DMA */
805 usb->idle_hardware_channels = 0x1;
806 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
807 /* CN5XXX have an errata with channel 3 */
808 usb->idle_hardware_channels = 0xf7;
809 else
810 usb->idle_hardware_channels = 0xff;
811 usbcx_gahbcfg.s.hbstlen = 0;
812 usbcx_gahbcfg.s.nptxfemplvl = 1;
813 usbcx_gahbcfg.s.ptxfemplvl = 1;
814 usbcx_gahbcfg.s.glblintrmsk = 1;
815 cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
816 usbcx_gahbcfg.u32);
819 * 3. Program the following fields in USBC_GUSBCFG register.
820 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
821 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
822 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
823 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
826 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
828 usbcx_gusbcfg.u32 = cvmx_usb_read_csr32(usb,
829 CVMX_USBCX_GUSBCFG(usb->index));
830 usbcx_gusbcfg.s.toutcal = 0;
831 usbcx_gusbcfg.s.ddrsel = 0;
832 usbcx_gusbcfg.s.usbtrdtim = 0x5;
833 usbcx_gusbcfg.s.phylpwrclksel = 0;
834 cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
835 usbcx_gusbcfg.u32);
838 * 4. The software must unmask the following bits in the USBC_GINTMSK
839 * register.
840 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
841 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
844 union cvmx_usbcx_gintmsk usbcx_gintmsk;
845 int channel;
847 usbcx_gintmsk.u32 = cvmx_usb_read_csr32(usb,
848 CVMX_USBCX_GINTMSK(usb->index));
849 usbcx_gintmsk.s.otgintmsk = 1;
850 usbcx_gintmsk.s.modemismsk = 1;
851 usbcx_gintmsk.s.hchintmsk = 1;
852 usbcx_gintmsk.s.sofmsk = 0;
853 /* We need RX FIFO interrupts if we don't have DMA */
854 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
855 usbcx_gintmsk.s.rxflvlmsk = 1;
856 cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
857 usbcx_gintmsk.u32);
860 * Disable all channel interrupts. We'll enable them per channel
861 * later.
863 for (channel = 0; channel < 8; channel++)
864 cvmx_usb_write_csr32(usb,
865 CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
870 * Host Port Initialization
872 * 1. Program the host-port interrupt-mask field to unmask,
873 * USBC_GINTMSK[PRTINT] = 1
875 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
876 union cvmx_usbcx_gintmsk, prtintmsk, 1);
877 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
878 union cvmx_usbcx_gintmsk, disconnintmsk, 1);
880 * 2. Program the USBC_HCFG register to select full-speed host
881 * or high-speed host.
884 union cvmx_usbcx_hcfg usbcx_hcfg;
886 usbcx_hcfg.u32 = cvmx_usb_read_csr32(usb,
887 CVMX_USBCX_HCFG(usb->index));
888 usbcx_hcfg.s.fslssupp = 0;
889 usbcx_hcfg.s.fslspclksel = 0;
890 cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index),
891 usbcx_hcfg.u32);
894 * 3. Program the port power bit to drive VBUS on the USB,
895 * USBC_HPRT[PRTPWR] = 1
897 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index),
898 union cvmx_usbcx_hprt, prtpwr, 1);
901 * Steps 4-15 from the manual are done later in the port enable
905 return 0;
910 * Shutdown a USB port after a call to cvmx_usb_initialize().
911 * The port should be disabled with all pipes closed when this
912 * function is called.
914 * @usb: USB device state populated by cvmx_usb_initialize().
916 * Returns: 0 or a negative error code.
918 static int cvmx_usb_shutdown(struct cvmx_usb_state *usb)
920 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
922 /* Make sure all pipes are closed */
923 if (!list_empty(&usb->idle_pipes) ||
924 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS]) ||
925 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT]) ||
926 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_CONTROL]) ||
927 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_BULK]))
928 return -EBUSY;
930 /* Disable the clocks and put them in power on reset */
931 usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index));
932 usbn_clk_ctl.s.enable = 1;
933 usbn_clk_ctl.s.por = 1;
934 usbn_clk_ctl.s.hclk_rst = 1;
935 usbn_clk_ctl.s.prst = 0;
936 usbn_clk_ctl.s.hrst = 0;
937 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
938 return 0;
943 * Enable a USB port. After this call succeeds, the USB port is
944 * online and servicing requests.
946 * @usb: USB device state populated by cvmx_usb_initialize().
948 * Returns: 0 or a negative error code.
950 static int cvmx_usb_enable(struct cvmx_usb_state *usb)
952 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
954 usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb,
955 CVMX_USBCX_HPRT(usb->index));
958 * If the port is already enabled the just return. We don't need to do
959 * anything
961 if (usb->usbcx_hprt.s.prtena)
962 return 0;
964 /* If there is nothing plugged into the port then fail immediately */
965 if (!usb->usbcx_hprt.s.prtconnsts)
966 return -ETIMEDOUT;
968 /* Program the port reset bit to start the reset process */
969 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
970 prtrst, 1);
973 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
974 * process to complete.
976 mdelay(50);
978 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
979 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
980 prtrst, 0);
982 /* Wait for the USBC_HPRT[PRTENA]. */
983 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index),
984 union cvmx_usbcx_hprt, prtena, ==, 1, 100000))
985 return -ETIMEDOUT;
988 * Read the port speed field to get the enumerated speed,
989 * USBC_HPRT[PRTSPD].
991 usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb,
992 CVMX_USBCX_HPRT(usb->index));
993 usbcx_ghwcfg3.u32 = cvmx_usb_read_csr32(usb,
994 CVMX_USBCX_GHWCFG3(usb->index));
997 * 13. Program the USBC_GRXFSIZ register to select the size of the
998 * receive FIFO (25%).
1000 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index),
1001 union cvmx_usbcx_grxfsiz, rxfdep,
1002 usbcx_ghwcfg3.s.dfifodepth / 4);
1004 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
1005 * start address of the non- periodic transmit FIFO for nonperiodic
1006 * transactions (50%).
1009 union cvmx_usbcx_gnptxfsiz siz;
1011 siz.u32 = cvmx_usb_read_csr32(usb,
1012 CVMX_USBCX_GNPTXFSIZ(usb->index));
1013 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
1014 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
1015 cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index),
1016 siz.u32);
1019 * 15. Program the USBC_HPTXFSIZ register to select the size and start
1020 * address of the periodic transmit FIFO for periodic transactions
1021 * (25%).
1024 union cvmx_usbcx_hptxfsiz siz;
1026 siz.u32 = cvmx_usb_read_csr32(usb,
1027 CVMX_USBCX_HPTXFSIZ(usb->index));
1028 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
1029 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
1030 cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index),
1031 siz.u32);
1033 /* Flush all FIFOs */
1034 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1035 union cvmx_usbcx_grstctl, txfnum, 0x10);
1036 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1037 union cvmx_usbcx_grstctl, txfflsh, 1);
1038 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1039 union cvmx_usbcx_grstctl,
1040 txfflsh, ==, 0, 100);
1041 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1042 union cvmx_usbcx_grstctl, rxfflsh, 1);
1043 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1044 union cvmx_usbcx_grstctl,
1045 rxfflsh, ==, 0, 100);
1047 return 0;
1052 * Disable a USB port. After this call the USB port will not
1053 * generate data transfers and will not generate events.
1054 * Transactions in process will fail and call their
1055 * associated callbacks.
1057 * @usb: USB device state populated by cvmx_usb_initialize().
1059 * Returns: 0 or a negative error code.
1061 static int cvmx_usb_disable(struct cvmx_usb_state *usb)
1063 /* Disable the port */
1064 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1065 prtena, 1);
1066 return 0;
1071 * Get the current state of the USB port. Use this call to
1072 * determine if the usb port has anything connected, is enabled,
1073 * or has some sort of error condition. The return value of this
1074 * call has "changed" bits to signal of the value of some fields
1075 * have changed between calls.
1077 * @usb: USB device state populated by cvmx_usb_initialize().
1079 * Returns: Port status information
1081 static struct cvmx_usb_port_status cvmx_usb_get_status(
1082 struct cvmx_usb_state *usb)
1084 union cvmx_usbcx_hprt usbc_hprt;
1085 struct cvmx_usb_port_status result;
1087 memset(&result, 0, sizeof(result));
1089 usbc_hprt.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1090 result.port_enabled = usbc_hprt.s.prtena;
1091 result.port_over_current = usbc_hprt.s.prtovrcurract;
1092 result.port_powered = usbc_hprt.s.prtpwr;
1093 result.port_speed = usbc_hprt.s.prtspd;
1094 result.connected = usbc_hprt.s.prtconnsts;
1095 result.connect_change =
1096 (result.connected != usb->port_status.connected);
1098 return result;
1102 * Open a virtual pipe between the host and a USB device. A pipe
1103 * must be opened before data can be transferred between a device
1104 * and Octeon.
1106 * @usb: USB device state populated by cvmx_usb_initialize().
1107 * @device_addr:
1108 * USB device address to open the pipe to
1109 * (0-127).
1110 * @endpoint_num:
1111 * USB endpoint number to open the pipe to
1112 * (0-15).
1113 * @device_speed:
1114 * The speed of the device the pipe is going
1115 * to. This must match the device's speed,
1116 * which may be different than the port speed.
1117 * @max_packet: The maximum packet length the device can
1118 * transmit/receive (low speed=0-8, full
1119 * speed=0-1023, high speed=0-1024). This value
1120 * comes from the standard endpoint descriptor
1121 * field wMaxPacketSize bits <10:0>.
1122 * @transfer_type:
1123 * The type of transfer this pipe is for.
1124 * @transfer_dir:
1125 * The direction the pipe is in. This is not
1126 * used for control pipes.
1127 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1128 * this is how often the transfer is scheduled
1129 * for. All other transfers should specify
1130 * zero. The units are in frames (8000/sec at
1131 * high speed, 1000/sec for full speed).
1132 * @multi_count:
1133 * For high speed devices, this is the maximum
1134 * allowed number of packet per microframe.
1135 * Specify zero for non high speed devices. This
1136 * value comes from the standard endpoint descriptor
1137 * field wMaxPacketSize bits <12:11>.
1138 * @hub_device_addr:
1139 * Hub device address this device is connected
1140 * to. Devices connected directly to Octeon
1141 * use zero. This is only used when the device
1142 * is full/low speed behind a high speed hub.
1143 * The address will be of the high speed hub,
1144 * not and full speed hubs after it.
1145 * @hub_port: Which port on the hub the device is
1146 * connected. Use zero for devices connected
1147 * directly to Octeon. Like hub_device_addr,
1148 * this is only used for full/low speed
1149 * devices behind a high speed hub.
1151 * Returns: A non-NULL value is a pipe. NULL means an error.
1153 static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct cvmx_usb_state *usb,
1154 int device_addr,
1155 int endpoint_num,
1156 enum cvmx_usb_speed
1157 device_speed,
1158 int max_packet,
1159 enum cvmx_usb_transfer
1160 transfer_type,
1161 enum cvmx_usb_direction
1162 transfer_dir,
1163 int interval, int multi_count,
1164 int hub_device_addr,
1165 int hub_port)
1167 struct cvmx_usb_pipe *pipe;
1169 pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC);
1170 if (!pipe)
1171 return NULL;
1172 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1173 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1174 (transfer_type == CVMX_USB_TRANSFER_BULK))
1175 pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING;
1176 pipe->device_addr = device_addr;
1177 pipe->endpoint_num = endpoint_num;
1178 pipe->device_speed = device_speed;
1179 pipe->max_packet = max_packet;
1180 pipe->transfer_type = transfer_type;
1181 pipe->transfer_dir = transfer_dir;
1182 INIT_LIST_HEAD(&pipe->transactions);
1185 * All pipes use interval to rate limit NAK processing. Force an
1186 * interval if one wasn't supplied
1188 if (!interval)
1189 interval = 1;
1190 if (cvmx_usb_pipe_needs_split(usb, pipe)) {
1191 pipe->interval = interval*8;
1192 /* Force start splits to be schedule on uFrame 0 */
1193 pipe->next_tx_frame = ((usb->frame_number+7)&~7) +
1194 pipe->interval;
1195 } else {
1196 pipe->interval = interval;
1197 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1199 pipe->multi_count = multi_count;
1200 pipe->hub_device_addr = hub_device_addr;
1201 pipe->hub_port = hub_port;
1202 pipe->pid_toggle = 0;
1203 pipe->split_sc_frame = -1;
1204 list_add_tail(&pipe->node, &usb->idle_pipes);
1207 * We don't need to tell the hardware about this pipe yet since
1208 * it doesn't have any submitted requests
1211 return pipe;
1216 * Poll the RX FIFOs and remove data as needed. This function is only used
1217 * in non DMA mode. It is very important that this function be called quickly
1218 * enough to prevent FIFO overflow.
1220 * @usb: USB device state populated by cvmx_usb_initialize().
1222 static void cvmx_usb_poll_rx_fifo(struct cvmx_usb_state *usb)
1224 union cvmx_usbcx_grxstsph rx_status;
1225 int channel;
1226 int bytes;
1227 uint64_t address;
1228 uint32_t *ptr;
1230 rx_status.u32 = cvmx_usb_read_csr32(usb,
1231 CVMX_USBCX_GRXSTSPH(usb->index));
1232 /* Only read data if IN data is there */
1233 if (rx_status.s.pktsts != 2)
1234 return;
1235 /* Check if no data is available */
1236 if (!rx_status.s.bcnt)
1237 return;
1239 channel = rx_status.s.chnum;
1240 bytes = rx_status.s.bcnt;
1241 if (!bytes)
1242 return;
1244 /* Get where the DMA engine would have written this data */
1245 address = cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) +
1246 channel * 8);
1248 ptr = cvmx_phys_to_ptr(address);
1249 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel * 8,
1250 address + bytes);
1252 /* Loop writing the FIFO data for this packet into memory */
1253 while (bytes > 0) {
1254 *ptr++ = cvmx_usb_read_csr32(usb,
1255 USB_FIFO_ADDRESS(channel, usb->index));
1256 bytes -= 4;
1258 CVMX_SYNCW;
1263 * Fill the TX hardware fifo with data out of the software
1264 * fifos
1266 * @usb: USB device state populated by cvmx_usb_initialize().
1267 * @fifo: Software fifo to use
1268 * @available: Amount of space in the hardware fifo
1270 * Returns: Non zero if the hardware fifo was too small and needs
1271 * to be serviced again.
1273 static int cvmx_usb_fill_tx_hw(struct cvmx_usb_state *usb,
1274 struct cvmx_usb_tx_fifo *fifo, int available)
1277 * We're done either when there isn't anymore space or the software FIFO
1278 * is empty
1280 while (available && (fifo->head != fifo->tail)) {
1281 int i = fifo->tail;
1282 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1283 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel,
1284 usb->index) ^ 4;
1285 int words = available;
1287 /* Limit the amount of data to waht the SW fifo has */
1288 if (fifo->entry[i].size <= available) {
1289 words = fifo->entry[i].size;
1290 fifo->tail++;
1291 if (fifo->tail > MAX_CHANNELS)
1292 fifo->tail = 0;
1295 /* Update the next locations and counts */
1296 available -= words;
1297 fifo->entry[i].address += words * 4;
1298 fifo->entry[i].size -= words;
1301 * Write the HW fifo data. The read every three writes is due
1302 * to an errata on CN3XXX chips
1304 while (words > 3) {
1305 cvmx_write64_uint32(csr_address, *ptr++);
1306 cvmx_write64_uint32(csr_address, *ptr++);
1307 cvmx_write64_uint32(csr_address, *ptr++);
1308 cvmx_read64_uint64(
1309 CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1310 words -= 3;
1312 cvmx_write64_uint32(csr_address, *ptr++);
1313 if (--words) {
1314 cvmx_write64_uint32(csr_address, *ptr++);
1315 if (--words)
1316 cvmx_write64_uint32(csr_address, *ptr++);
1318 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1320 return fifo->head != fifo->tail;
1325 * Check the hardware FIFOs and fill them as needed
1327 * @usb: USB device state populated by cvmx_usb_initialize().
1329 static void cvmx_usb_poll_tx_fifo(struct cvmx_usb_state *usb)
1331 if (usb->periodic.head != usb->periodic.tail) {
1332 union cvmx_usbcx_hptxsts tx_status;
1334 tx_status.u32 = cvmx_usb_read_csr32(usb,
1335 CVMX_USBCX_HPTXSTS(usb->index));
1336 if (cvmx_usb_fill_tx_hw(usb, &usb->periodic,
1337 tx_status.s.ptxfspcavail))
1338 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1339 union cvmx_usbcx_gintmsk,
1340 ptxfempmsk, 1);
1341 else
1342 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1343 union cvmx_usbcx_gintmsk,
1344 ptxfempmsk, 0);
1347 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1348 union cvmx_usbcx_gnptxsts tx_status;
1350 tx_status.u32 = cvmx_usb_read_csr32(usb,
1351 CVMX_USBCX_GNPTXSTS(usb->index));
1352 if (cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic,
1353 tx_status.s.nptxfspcavail))
1354 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1355 union cvmx_usbcx_gintmsk,
1356 nptxfempmsk, 1);
1357 else
1358 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1359 union cvmx_usbcx_gintmsk,
1360 nptxfempmsk, 0);
1366 * Fill the TX FIFO with an outgoing packet
1368 * @usb: USB device state populated by cvmx_usb_initialize().
1369 * @channel: Channel number to get packet from
1371 static void cvmx_usb_fill_tx_fifo(struct cvmx_usb_state *usb, int channel)
1373 union cvmx_usbcx_hccharx hcchar;
1374 union cvmx_usbcx_hcspltx usbc_hcsplt;
1375 union cvmx_usbcx_hctsizx usbc_hctsiz;
1376 struct cvmx_usb_tx_fifo *fifo;
1378 /* We only need to fill data on outbound channels */
1379 hcchar.u32 = cvmx_usb_read_csr32(usb,
1380 CVMX_USBCX_HCCHARX(channel, usb->index));
1381 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1382 return;
1384 /* OUT Splits only have data on the start and not the complete */
1385 usbc_hcsplt.u32 = cvmx_usb_read_csr32(usb,
1386 CVMX_USBCX_HCSPLTX(channel, usb->index));
1387 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1388 return;
1391 * Find out how many bytes we need to fill and convert it into 32bit
1392 * words.
1394 usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb,
1395 CVMX_USBCX_HCTSIZX(channel, usb->index));
1396 if (!usbc_hctsiz.s.xfersize)
1397 return;
1399 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1400 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1401 fifo = &usb->periodic;
1402 else
1403 fifo = &usb->nonperiodic;
1405 fifo->entry[fifo->head].channel = channel;
1406 fifo->entry[fifo->head].address =
1407 cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) +
1408 channel * 8);
1409 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1410 fifo->head++;
1411 if (fifo->head > MAX_CHANNELS)
1412 fifo->head = 0;
1414 cvmx_usb_poll_tx_fifo(usb);
1418 * Perform channel specific setup for Control transactions. All
1419 * the generic stuff will already have been done in cvmx_usb_start_channel().
1421 * @usb: USB device state populated by cvmx_usb_initialize().
1422 * @channel: Channel to setup
1423 * @pipe: Pipe for control transaction
1425 static void cvmx_usb_start_channel_control(struct cvmx_usb_state *usb,
1426 int channel,
1427 struct cvmx_usb_pipe *pipe)
1429 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
1430 struct usb_hcd *hcd = octeon_to_hcd(priv);
1431 struct device *dev = hcd->self.controller;
1432 struct cvmx_usb_transaction *transaction =
1433 list_first_entry(&pipe->transactions, typeof(*transaction),
1434 node);
1435 struct usb_ctrlrequest *header =
1436 cvmx_phys_to_ptr(transaction->control_header);
1437 int bytes_to_transfer = transaction->buffer_length -
1438 transaction->actual_bytes;
1439 int packets_to_transfer;
1440 union cvmx_usbcx_hctsizx usbc_hctsiz;
1442 usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb,
1443 CVMX_USBCX_HCTSIZX(channel, usb->index));
1445 switch (transaction->stage) {
1446 case CVMX_USB_STAGE_NON_CONTROL:
1447 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1448 dev_err(dev, "%s: ERROR - Non control stage\n", __func__);
1449 break;
1450 case CVMX_USB_STAGE_SETUP:
1451 usbc_hctsiz.s.pid = 3; /* Setup */
1452 bytes_to_transfer = sizeof(*header);
1453 /* All Control operations start with a setup going OUT */
1454 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1455 union cvmx_usbcx_hccharx, epdir,
1456 CVMX_USB_DIRECTION_OUT);
1458 * Setup send the control header instead of the buffer data. The
1459 * buffer data will be used in the next stage
1461 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) +
1462 channel * 8,
1463 transaction->control_header);
1464 break;
1465 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1466 usbc_hctsiz.s.pid = 3; /* Setup */
1467 bytes_to_transfer = 0;
1468 /* All Control operations start with a setup going OUT */
1469 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1470 union cvmx_usbcx_hccharx, epdir,
1471 CVMX_USB_DIRECTION_OUT);
1473 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1474 union cvmx_usbcx_hcspltx, compsplt, 1);
1475 break;
1476 case CVMX_USB_STAGE_DATA:
1477 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe);
1478 if (cvmx_usb_pipe_needs_split(usb, pipe)) {
1479 if (header->bRequestType & USB_DIR_IN)
1480 bytes_to_transfer = 0;
1481 else if (bytes_to_transfer > pipe->max_packet)
1482 bytes_to_transfer = pipe->max_packet;
1484 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1485 union cvmx_usbcx_hccharx, epdir,
1486 ((header->bRequestType & USB_DIR_IN) ?
1487 CVMX_USB_DIRECTION_IN :
1488 CVMX_USB_DIRECTION_OUT));
1489 break;
1490 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1491 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe);
1492 if (!(header->bRequestType & USB_DIR_IN))
1493 bytes_to_transfer = 0;
1494 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1495 union cvmx_usbcx_hccharx, epdir,
1496 ((header->bRequestType & USB_DIR_IN) ?
1497 CVMX_USB_DIRECTION_IN :
1498 CVMX_USB_DIRECTION_OUT));
1499 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1500 union cvmx_usbcx_hcspltx, compsplt, 1);
1501 break;
1502 case CVMX_USB_STAGE_STATUS:
1503 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe);
1504 bytes_to_transfer = 0;
1505 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1506 union cvmx_usbcx_hccharx, epdir,
1507 ((header->bRequestType & USB_DIR_IN) ?
1508 CVMX_USB_DIRECTION_OUT :
1509 CVMX_USB_DIRECTION_IN));
1510 break;
1511 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1512 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe);
1513 bytes_to_transfer = 0;
1514 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1515 union cvmx_usbcx_hccharx, epdir,
1516 ((header->bRequestType & USB_DIR_IN) ?
1517 CVMX_USB_DIRECTION_OUT :
1518 CVMX_USB_DIRECTION_IN));
1519 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1520 union cvmx_usbcx_hcspltx, compsplt, 1);
1521 break;
1525 * Make sure the transfer never exceeds the byte limit of the hardware.
1526 * Further bytes will be sent as continued transactions
1528 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1529 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1530 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1531 bytes_to_transfer *= pipe->max_packet;
1535 * Calculate the number of packets to transfer. If the length is zero
1536 * we still need to transfer one packet
1538 packets_to_transfer = DIV_ROUND_UP(bytes_to_transfer,
1539 pipe->max_packet);
1540 if (packets_to_transfer == 0)
1541 packets_to_transfer = 1;
1542 else if ((packets_to_transfer > 1) &&
1543 (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1545 * Limit to one packet when not using DMA. Channels must be
1546 * restarted between every packet for IN transactions, so there
1547 * is no reason to do multiple packets in a row
1549 packets_to_transfer = 1;
1550 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1551 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1553 * Limit the number of packet and data transferred to what the
1554 * hardware can handle
1556 packets_to_transfer = MAX_TRANSFER_PACKETS;
1557 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1560 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1561 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1563 cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index),
1564 usbc_hctsiz.u32);
1569 * Start a channel to perform the pipe's head transaction
1571 * @usb: USB device state populated by cvmx_usb_initialize().
1572 * @channel: Channel to setup
1573 * @pipe: Pipe to start
1575 static void cvmx_usb_start_channel(struct cvmx_usb_state *usb, int channel,
1576 struct cvmx_usb_pipe *pipe)
1578 struct cvmx_usb_transaction *transaction =
1579 list_first_entry(&pipe->transactions, typeof(*transaction),
1580 node);
1582 /* Make sure all writes to the DMA region get flushed */
1583 CVMX_SYNCW;
1585 /* Attach the channel to the pipe */
1586 usb->pipe_for_channel[channel] = pipe;
1587 pipe->channel = channel;
1588 pipe->flags |= CVMX_USB_PIPE_FLAGS_SCHEDULED;
1590 /* Mark this channel as in use */
1591 usb->idle_hardware_channels &= ~(1<<channel);
1593 /* Enable the channel interrupt bits */
1595 union cvmx_usbcx_hcintx usbc_hcint;
1596 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1597 union cvmx_usbcx_haintmsk usbc_haintmsk;
1599 /* Clear all channel status bits */
1600 usbc_hcint.u32 = cvmx_usb_read_csr32(usb,
1601 CVMX_USBCX_HCINTX(channel, usb->index));
1603 cvmx_usb_write_csr32(usb,
1604 CVMX_USBCX_HCINTX(channel, usb->index),
1605 usbc_hcint.u32);
1607 usbc_hcintmsk.u32 = 0;
1608 usbc_hcintmsk.s.chhltdmsk = 1;
1609 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1611 * Channels need these extra interrupts when we aren't
1612 * in DMA mode.
1614 usbc_hcintmsk.s.datatglerrmsk = 1;
1615 usbc_hcintmsk.s.frmovrunmsk = 1;
1616 usbc_hcintmsk.s.bblerrmsk = 1;
1617 usbc_hcintmsk.s.xacterrmsk = 1;
1618 if (cvmx_usb_pipe_needs_split(usb, pipe)) {
1620 * Splits don't generate xfercompl, so we need
1621 * ACK and NYET.
1623 usbc_hcintmsk.s.nyetmsk = 1;
1624 usbc_hcintmsk.s.ackmsk = 1;
1626 usbc_hcintmsk.s.nakmsk = 1;
1627 usbc_hcintmsk.s.stallmsk = 1;
1628 usbc_hcintmsk.s.xfercomplmsk = 1;
1630 cvmx_usb_write_csr32(usb,
1631 CVMX_USBCX_HCINTMSKX(channel, usb->index),
1632 usbc_hcintmsk.u32);
1634 /* Enable the channel interrupt to propagate */
1635 usbc_haintmsk.u32 = cvmx_usb_read_csr32(usb,
1636 CVMX_USBCX_HAINTMSK(usb->index));
1637 usbc_haintmsk.s.haintmsk |= 1<<channel;
1638 cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index),
1639 usbc_haintmsk.u32);
1642 /* Setup the locations the DMA engines use */
1644 uint64_t dma_address = transaction->buffer +
1645 transaction->actual_bytes;
1647 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1648 dma_address = transaction->buffer +
1649 transaction->iso_packets[0].offset +
1650 transaction->actual_bytes;
1652 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) +
1653 channel * 8,
1654 dma_address);
1655 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) +
1656 channel * 8,
1657 dma_address);
1660 /* Setup both the size of the transfer and the SPLIT characteristics */
1662 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1663 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1664 int packets_to_transfer;
1665 int bytes_to_transfer = transaction->buffer_length -
1666 transaction->actual_bytes;
1669 * ISOCHRONOUS transactions store each individual transfer size
1670 * in the packet structure, not the global buffer_length
1672 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1673 bytes_to_transfer =
1674 transaction->iso_packets[0].length -
1675 transaction->actual_bytes;
1678 * We need to do split transactions when we are talking to non
1679 * high speed devices that are behind a high speed hub
1681 if (cvmx_usb_pipe_needs_split(usb, pipe)) {
1683 * On the start split phase (stage is even) record the
1684 * frame number we will need to send the split complete.
1685 * We only store the lower two bits since the time ahead
1686 * can only be two frames
1688 if ((transaction->stage&1) == 0) {
1689 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1690 pipe->split_sc_frame =
1691 (usb->frame_number + 1) & 0x7f;
1692 else
1693 pipe->split_sc_frame =
1694 (usb->frame_number + 2) & 0x7f;
1695 } else
1696 pipe->split_sc_frame = -1;
1698 usbc_hcsplt.s.spltena = 1;
1699 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1700 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1701 usbc_hcsplt.s.compsplt = (transaction->stage ==
1702 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1705 * SPLIT transactions can only ever transmit one data
1706 * packet so limit the transfer size to the max packet
1707 * size
1709 if (bytes_to_transfer > pipe->max_packet)
1710 bytes_to_transfer = pipe->max_packet;
1713 * ISOCHRONOUS OUT splits are unique in that they limit
1714 * data transfers to 188 byte chunks representing the
1715 * begin/middle/end of the data or all
1717 if (!usbc_hcsplt.s.compsplt &&
1718 (pipe->transfer_dir ==
1719 CVMX_USB_DIRECTION_OUT) &&
1720 (pipe->transfer_type ==
1721 CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1723 * Clear the split complete frame number as
1724 * there isn't going to be a split complete
1726 pipe->split_sc_frame = -1;
1728 * See if we've started this transfer and sent
1729 * data
1731 if (transaction->actual_bytes == 0) {
1733 * Nothing sent yet, this is either a
1734 * begin or the entire payload
1736 if (bytes_to_transfer <= 188)
1737 /* Entire payload in one go */
1738 usbc_hcsplt.s.xactpos = 3;
1739 else
1740 /* First part of payload */
1741 usbc_hcsplt.s.xactpos = 2;
1742 } else {
1744 * Continuing the previous data, we must
1745 * either be in the middle or at the end
1747 if (bytes_to_transfer <= 188)
1748 /* End of payload */
1749 usbc_hcsplt.s.xactpos = 1;
1750 else
1751 /* Middle of payload */
1752 usbc_hcsplt.s.xactpos = 0;
1755 * Again, the transfer size is limited to 188
1756 * bytes
1758 if (bytes_to_transfer > 188)
1759 bytes_to_transfer = 188;
1764 * Make sure the transfer never exceeds the byte limit of the
1765 * hardware. Further bytes will be sent as continued
1766 * transactions
1768 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1770 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1771 * size
1773 bytes_to_transfer = MAX_TRANSFER_BYTES /
1774 pipe->max_packet;
1775 bytes_to_transfer *= pipe->max_packet;
1779 * Calculate the number of packets to transfer. If the length is
1780 * zero we still need to transfer one packet
1782 packets_to_transfer =
1783 DIV_ROUND_UP(bytes_to_transfer, pipe->max_packet);
1784 if (packets_to_transfer == 0)
1785 packets_to_transfer = 1;
1786 else if ((packets_to_transfer > 1) &&
1787 (usb->init_flags &
1788 CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1790 * Limit to one packet when not using DMA. Channels must
1791 * be restarted between every packet for IN
1792 * transactions, so there is no reason to do multiple
1793 * packets in a row
1795 packets_to_transfer = 1;
1796 bytes_to_transfer = packets_to_transfer *
1797 pipe->max_packet;
1798 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1800 * Limit the number of packet and data transferred to
1801 * what the hardware can handle
1803 packets_to_transfer = MAX_TRANSFER_PACKETS;
1804 bytes_to_transfer = packets_to_transfer *
1805 pipe->max_packet;
1808 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1809 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1811 /* Update the DATA0/DATA1 toggle */
1812 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe);
1814 * High speed pipes may need a hardware ping before they start
1816 if (pipe->flags & CVMX_USB_PIPE_FLAGS_NEED_PING)
1817 usbc_hctsiz.s.dopng = 1;
1819 cvmx_usb_write_csr32(usb,
1820 CVMX_USBCX_HCSPLTX(channel, usb->index),
1821 usbc_hcsplt.u32);
1822 cvmx_usb_write_csr32(usb,
1823 CVMX_USBCX_HCTSIZX(channel, usb->index),
1824 usbc_hctsiz.u32);
1827 /* Setup the Host Channel Characteristics Register */
1829 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1832 * Set the startframe odd/even properly. This is only used for
1833 * periodic
1835 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1838 * Set the number of back to back packets allowed by this
1839 * endpoint. Split transactions interpret "ec" as the number of
1840 * immediate retries of failure. These retries happen too
1841 * quickly, so we disable these entirely for splits
1843 if (cvmx_usb_pipe_needs_split(usb, pipe))
1844 usbc_hcchar.s.ec = 1;
1845 else if (pipe->multi_count < 1)
1846 usbc_hcchar.s.ec = 1;
1847 else if (pipe->multi_count > 3)
1848 usbc_hcchar.s.ec = 3;
1849 else
1850 usbc_hcchar.s.ec = pipe->multi_count;
1852 /* Set the rest of the endpoint specific settings */
1853 usbc_hcchar.s.devaddr = pipe->device_addr;
1854 usbc_hcchar.s.eptype = transaction->type;
1855 usbc_hcchar.s.lspddev =
1856 (pipe->device_speed == CVMX_USB_SPEED_LOW);
1857 usbc_hcchar.s.epdir = pipe->transfer_dir;
1858 usbc_hcchar.s.epnum = pipe->endpoint_num;
1859 usbc_hcchar.s.mps = pipe->max_packet;
1860 cvmx_usb_write_csr32(usb,
1861 CVMX_USBCX_HCCHARX(channel, usb->index),
1862 usbc_hcchar.u32);
1865 /* Do transaction type specific fixups as needed */
1866 switch (transaction->type) {
1867 case CVMX_USB_TRANSFER_CONTROL:
1868 cvmx_usb_start_channel_control(usb, channel, pipe);
1869 break;
1870 case CVMX_USB_TRANSFER_BULK:
1871 case CVMX_USB_TRANSFER_INTERRUPT:
1872 break;
1873 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1874 if (!cvmx_usb_pipe_needs_split(usb, pipe)) {
1876 * ISO transactions require different PIDs depending on
1877 * direction and how many packets are needed
1879 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1880 if (pipe->multi_count < 2) /* Need DATA0 */
1881 USB_SET_FIELD32(
1882 CVMX_USBCX_HCTSIZX(channel,
1883 usb->index),
1884 union cvmx_usbcx_hctsizx,
1885 pid, 0);
1886 else /* Need MDATA */
1887 USB_SET_FIELD32(
1888 CVMX_USBCX_HCTSIZX(channel,
1889 usb->index),
1890 union cvmx_usbcx_hctsizx,
1891 pid, 3);
1894 break;
1897 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 =
1898 cvmx_usb_read_csr32(usb,
1899 CVMX_USBCX_HCTSIZX(channel, usb->index))};
1900 transaction->xfersize = usbc_hctsiz.s.xfersize;
1901 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1903 /* Remeber when we start a split transaction */
1904 if (cvmx_usb_pipe_needs_split(usb, pipe))
1905 usb->active_split = transaction;
1906 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1907 union cvmx_usbcx_hccharx, chena, 1);
1908 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1909 cvmx_usb_fill_tx_fifo(usb, channel);
1914 * Find a pipe that is ready to be scheduled to hardware.
1915 * @usb: USB device state populated by cvmx_usb_initialize().
1916 * @list: Pipe list to search
1917 * @current_frame:
1918 * Frame counter to use as a time reference.
1920 * Returns: Pipe or NULL if none are ready
1922 static struct cvmx_usb_pipe *cvmx_usb_find_ready_pipe(
1923 struct cvmx_usb_state *usb,
1924 struct list_head *list,
1925 uint64_t current_frame)
1927 struct cvmx_usb_pipe *pipe;
1929 list_for_each_entry(pipe, list, node) {
1930 struct cvmx_usb_transaction *t =
1931 list_first_entry(&pipe->transactions, typeof(*t),
1932 node);
1933 if (!(pipe->flags & CVMX_USB_PIPE_FLAGS_SCHEDULED) && t &&
1934 (pipe->next_tx_frame <= current_frame) &&
1935 ((pipe->split_sc_frame == -1) ||
1936 ((((int)current_frame - (int)pipe->split_sc_frame)
1937 & 0x7f) < 0x40)) &&
1938 (!usb->active_split || (usb->active_split == t))) {
1939 prefetch(t);
1940 return pipe;
1943 return NULL;
1948 * Called whenever a pipe might need to be scheduled to the
1949 * hardware.
1951 * @usb: USB device state populated by cvmx_usb_initialize().
1952 * @is_sof: True if this schedule was called on a SOF interrupt.
1954 static void cvmx_usb_schedule(struct cvmx_usb_state *usb, int is_sof)
1956 int channel;
1957 struct cvmx_usb_pipe *pipe;
1958 int need_sof;
1959 enum cvmx_usb_transfer ttype;
1961 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1963 * Without DMA we need to be careful to not schedule something
1964 * at the end of a frame and cause an overrun.
1966 union cvmx_usbcx_hfnum hfnum = {
1967 .u32 = cvmx_usb_read_csr32(usb,
1968 CVMX_USBCX_HFNUM(usb->index))
1971 union cvmx_usbcx_hfir hfir = {
1972 .u32 = cvmx_usb_read_csr32(usb,
1973 CVMX_USBCX_HFIR(usb->index))
1976 if (hfnum.s.frrem < hfir.s.frint/4)
1977 goto done;
1980 while (usb->idle_hardware_channels) {
1981 /* Find an idle channel */
1982 channel = __fls(usb->idle_hardware_channels);
1983 if (unlikely(channel > 7))
1984 break;
1986 /* Find a pipe needing service */
1987 pipe = NULL;
1988 if (is_sof) {
1990 * Only process periodic pipes on SOF interrupts. This
1991 * way we are sure that the periodic data is sent in the
1992 * beginning of the frame
1994 pipe = cvmx_usb_find_ready_pipe(usb,
1995 usb->active_pipes +
1996 CVMX_USB_TRANSFER_ISOCHRONOUS,
1997 usb->frame_number);
1998 if (likely(!pipe))
1999 pipe = cvmx_usb_find_ready_pipe(usb,
2000 usb->active_pipes +
2001 CVMX_USB_TRANSFER_INTERRUPT,
2002 usb->frame_number);
2004 if (likely(!pipe)) {
2005 pipe = cvmx_usb_find_ready_pipe(usb,
2006 usb->active_pipes +
2007 CVMX_USB_TRANSFER_CONTROL,
2008 usb->frame_number);
2009 if (likely(!pipe))
2010 pipe = cvmx_usb_find_ready_pipe(usb,
2011 usb->active_pipes +
2012 CVMX_USB_TRANSFER_BULK,
2013 usb->frame_number);
2015 if (!pipe)
2016 break;
2018 cvmx_usb_start_channel(usb, channel, pipe);
2021 done:
2023 * Only enable SOF interrupts when we have transactions pending in the
2024 * future that might need to be scheduled
2026 need_sof = 0;
2027 for (ttype = CVMX_USB_TRANSFER_CONTROL;
2028 ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
2029 list_for_each_entry(pipe, &usb->active_pipes[ttype], node) {
2030 if (pipe->next_tx_frame > usb->frame_number) {
2031 need_sof = 1;
2032 break;
2036 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
2037 union cvmx_usbcx_gintmsk, sofmsk, need_sof);
2040 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state *usb,
2041 enum cvmx_usb_complete status,
2042 struct cvmx_usb_pipe *pipe,
2043 struct cvmx_usb_transaction
2044 *transaction,
2045 int bytes_transferred,
2046 struct urb *urb)
2048 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2049 struct usb_hcd *hcd = octeon_to_hcd(priv);
2050 struct device *dev = hcd->self.controller;
2052 if (likely(status == CVMX_USB_COMPLETE_SUCCESS))
2053 urb->actual_length = bytes_transferred;
2054 else
2055 urb->actual_length = 0;
2057 urb->hcpriv = NULL;
2059 /* For Isochronous transactions we need to update the URB packet status
2060 list from data in our private copy */
2061 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2062 int i;
2064 * The pointer to the private list is stored in the setup_packet
2065 * field.
2067 struct cvmx_usb_iso_packet *iso_packet =
2068 (struct cvmx_usb_iso_packet *) urb->setup_packet;
2069 /* Recalculate the transfer size by adding up each packet */
2070 urb->actual_length = 0;
2071 for (i = 0; i < urb->number_of_packets; i++) {
2072 if (iso_packet[i].status ==
2073 CVMX_USB_COMPLETE_SUCCESS) {
2074 urb->iso_frame_desc[i].status = 0;
2075 urb->iso_frame_desc[i].actual_length =
2076 iso_packet[i].length;
2077 urb->actual_length +=
2078 urb->iso_frame_desc[i].actual_length;
2079 } else {
2080 dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2081 i, urb->number_of_packets,
2082 iso_packet[i].status, pipe,
2083 transaction, iso_packet[i].length);
2084 urb->iso_frame_desc[i].status = -EREMOTEIO;
2087 /* Free the private list now that we don't need it anymore */
2088 kfree(iso_packet);
2089 urb->setup_packet = NULL;
2092 switch (status) {
2093 case CVMX_USB_COMPLETE_SUCCESS:
2094 urb->status = 0;
2095 break;
2096 case CVMX_USB_COMPLETE_CANCEL:
2097 if (urb->status == 0)
2098 urb->status = -ENOENT;
2099 break;
2100 case CVMX_USB_COMPLETE_STALL:
2101 dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n",
2102 pipe, transaction, bytes_transferred);
2103 urb->status = -EPIPE;
2104 break;
2105 case CVMX_USB_COMPLETE_BABBLEERR:
2106 dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n",
2107 pipe, transaction, bytes_transferred);
2108 urb->status = -EPIPE;
2109 break;
2110 case CVMX_USB_COMPLETE_SHORT:
2111 dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n",
2112 pipe, transaction, bytes_transferred);
2113 urb->status = -EREMOTEIO;
2114 break;
2115 case CVMX_USB_COMPLETE_ERROR:
2116 case CVMX_USB_COMPLETE_XACTERR:
2117 case CVMX_USB_COMPLETE_DATATGLERR:
2118 case CVMX_USB_COMPLETE_FRAMEERR:
2119 dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n",
2120 status, pipe, transaction, bytes_transferred);
2121 urb->status = -EPROTO;
2122 break;
2124 usb_hcd_unlink_urb_from_ep(octeon_to_hcd(priv), urb);
2125 spin_unlock(&priv->lock);
2126 usb_hcd_giveback_urb(octeon_to_hcd(priv), urb, urb->status);
2127 spin_lock(&priv->lock);
2131 * Signal the completion of a transaction and free it. The
2132 * transaction will be removed from the pipe transaction list.
2134 * @usb: USB device state populated by cvmx_usb_initialize().
2135 * @pipe: Pipe the transaction is on
2136 * @transaction:
2137 * Transaction that completed
2138 * @complete_code:
2139 * Completion code
2141 static void cvmx_usb_perform_complete(struct cvmx_usb_state *usb,
2142 struct cvmx_usb_pipe *pipe,
2143 struct cvmx_usb_transaction *transaction,
2144 enum cvmx_usb_complete complete_code)
2146 /* If this was a split then clear our split in progress marker */
2147 if (usb->active_split == transaction)
2148 usb->active_split = NULL;
2151 * Isochronous transactions need extra processing as they might not be
2152 * done after a single data transfer
2154 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2155 /* Update the number of bytes transferred in this ISO packet */
2156 transaction->iso_packets[0].length = transaction->actual_bytes;
2157 transaction->iso_packets[0].status = complete_code;
2160 * If there are more ISOs pending and we succeeded, schedule the
2161 * next one
2163 if ((transaction->iso_number_packets > 1) &&
2164 (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2165 /* No bytes transferred for this packet as of yet */
2166 transaction->actual_bytes = 0;
2167 /* One less ISO waiting to transfer */
2168 transaction->iso_number_packets--;
2169 /* Increment to the next location in our packet array */
2170 transaction->iso_packets++;
2171 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2172 return;
2176 /* Remove the transaction from the pipe list */
2177 list_del(&transaction->node);
2178 if (list_empty(&pipe->transactions))
2179 list_move_tail(&pipe->node, &usb->idle_pipes);
2180 octeon_usb_urb_complete_callback(usb, complete_code, pipe,
2181 transaction,
2182 transaction->actual_bytes,
2183 transaction->urb);
2184 kfree(transaction);
2189 * Submit a usb transaction to a pipe. Called for all types
2190 * of transactions.
2192 * @usb:
2193 * @pipe: Which pipe to submit to.
2194 * @type: Transaction type
2195 * @buffer: User buffer for the transaction
2196 * @buffer_length:
2197 * User buffer's length in bytes
2198 * @control_header:
2199 * For control transactions, the 8 byte standard header
2200 * @iso_start_frame:
2201 * For ISO transactions, the start frame
2202 * @iso_number_packets:
2203 * For ISO, the number of packet in the transaction.
2204 * @iso_packets:
2205 * A description of each ISO packet
2206 * @urb: URB for the callback
2208 * Returns: Transaction or NULL on failure.
2210 static struct cvmx_usb_transaction *cvmx_usb_submit_transaction(
2211 struct cvmx_usb_state *usb,
2212 struct cvmx_usb_pipe *pipe,
2213 enum cvmx_usb_transfer type,
2214 uint64_t buffer,
2215 int buffer_length,
2216 uint64_t control_header,
2217 int iso_start_frame,
2218 int iso_number_packets,
2219 struct cvmx_usb_iso_packet *iso_packets,
2220 struct urb *urb)
2222 struct cvmx_usb_transaction *transaction;
2224 if (unlikely(pipe->transfer_type != type))
2225 return NULL;
2227 transaction = kzalloc(sizeof(*transaction), GFP_ATOMIC);
2228 if (unlikely(!transaction))
2229 return NULL;
2231 transaction->type = type;
2232 transaction->buffer = buffer;
2233 transaction->buffer_length = buffer_length;
2234 transaction->control_header = control_header;
2235 /* FIXME: This is not used, implement it. */
2236 transaction->iso_start_frame = iso_start_frame;
2237 transaction->iso_number_packets = iso_number_packets;
2238 transaction->iso_packets = iso_packets;
2239 transaction->urb = urb;
2240 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2241 transaction->stage = CVMX_USB_STAGE_SETUP;
2242 else
2243 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2245 if (!list_empty(&pipe->transactions)) {
2246 list_add_tail(&transaction->node, &pipe->transactions);
2247 } else {
2248 list_add_tail(&transaction->node, &pipe->transactions);
2249 list_move_tail(&pipe->node,
2250 &usb->active_pipes[pipe->transfer_type]);
2253 * We may need to schedule the pipe if this was the head of the
2254 * pipe.
2256 cvmx_usb_schedule(usb, 0);
2259 return transaction;
2264 * Call to submit a USB Bulk transfer to a pipe.
2266 * @usb: USB device state populated by cvmx_usb_initialize().
2267 * @pipe: Handle to the pipe for the transfer.
2268 * @urb: URB.
2270 * Returns: A submitted transaction or NULL on failure.
2272 static struct cvmx_usb_transaction *cvmx_usb_submit_bulk(
2273 struct cvmx_usb_state *usb,
2274 struct cvmx_usb_pipe *pipe,
2275 struct urb *urb)
2277 return cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK,
2278 urb->transfer_dma,
2279 urb->transfer_buffer_length,
2280 0, /* control_header */
2281 0, /* iso_start_frame */
2282 0, /* iso_number_packets */
2283 NULL, /* iso_packets */
2284 urb);
2289 * Call to submit a USB Interrupt transfer to a pipe.
2291 * @usb: USB device state populated by cvmx_usb_initialize().
2292 * @pipe: Handle to the pipe for the transfer.
2293 * @urb: URB returned when the callback is called.
2295 * Returns: A submitted transaction or NULL on failure.
2297 static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt(
2298 struct cvmx_usb_state *usb,
2299 struct cvmx_usb_pipe *pipe,
2300 struct urb *urb)
2302 return cvmx_usb_submit_transaction(usb, pipe,
2303 CVMX_USB_TRANSFER_INTERRUPT,
2304 urb->transfer_dma,
2305 urb->transfer_buffer_length,
2306 0, /* control_header */
2307 0, /* iso_start_frame */
2308 0, /* iso_number_packets */
2309 NULL, /* iso_packets */
2310 urb);
2315 * Call to submit a USB Control transfer to a pipe.
2317 * @usb: USB device state populated by cvmx_usb_initialize().
2318 * @pipe: Handle to the pipe for the transfer.
2319 * @urb: URB.
2321 * Returns: A submitted transaction or NULL on failure.
2323 static struct cvmx_usb_transaction *cvmx_usb_submit_control(
2324 struct cvmx_usb_state *usb,
2325 struct cvmx_usb_pipe *pipe,
2326 struct urb *urb)
2328 int buffer_length = urb->transfer_buffer_length;
2329 uint64_t control_header = urb->setup_dma;
2330 struct usb_ctrlrequest *header = cvmx_phys_to_ptr(control_header);
2332 if ((header->bRequestType & USB_DIR_IN) == 0)
2333 buffer_length = le16_to_cpu(header->wLength);
2335 return cvmx_usb_submit_transaction(usb, pipe,
2336 CVMX_USB_TRANSFER_CONTROL,
2337 urb->transfer_dma, buffer_length,
2338 control_header,
2339 0, /* iso_start_frame */
2340 0, /* iso_number_packets */
2341 NULL, /* iso_packets */
2342 urb);
2347 * Call to submit a USB Isochronous transfer to a pipe.
2349 * @usb: USB device state populated by cvmx_usb_initialize().
2350 * @pipe: Handle to the pipe for the transfer.
2351 * @urb: URB returned when the callback is called.
2353 * Returns: A submitted transaction or NULL on failure.
2355 static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous(
2356 struct cvmx_usb_state *usb,
2357 struct cvmx_usb_pipe *pipe,
2358 struct urb *urb)
2360 struct cvmx_usb_iso_packet *packets;
2362 packets = (struct cvmx_usb_iso_packet *) urb->setup_packet;
2363 return cvmx_usb_submit_transaction(usb, pipe,
2364 CVMX_USB_TRANSFER_ISOCHRONOUS,
2365 urb->transfer_dma,
2366 urb->transfer_buffer_length,
2367 0, /* control_header */
2368 urb->start_frame,
2369 urb->number_of_packets,
2370 packets, urb);
2375 * Cancel one outstanding request in a pipe. Canceling a request
2376 * can fail if the transaction has already completed before cancel
2377 * is called. Even after a successful cancel call, it may take
2378 * a frame or two for the cvmx_usb_poll() function to call the
2379 * associated callback.
2381 * @usb: USB device state populated by cvmx_usb_initialize().
2382 * @pipe: Pipe to cancel requests in.
2383 * @transaction: Transaction to cancel, returned by the submit function.
2385 * Returns: 0 or a negative error code.
2387 static int cvmx_usb_cancel(struct cvmx_usb_state *usb,
2388 struct cvmx_usb_pipe *pipe,
2389 struct cvmx_usb_transaction *transaction)
2392 * If the transaction is the HEAD of the queue and scheduled. We need to
2393 * treat it special
2395 if (list_first_entry(&pipe->transactions, typeof(*transaction), node) ==
2396 transaction && (pipe->flags & CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2397 union cvmx_usbcx_hccharx usbc_hcchar;
2399 usb->pipe_for_channel[pipe->channel] = NULL;
2400 pipe->flags &= ~CVMX_USB_PIPE_FLAGS_SCHEDULED;
2402 CVMX_SYNCW;
2404 usbc_hcchar.u32 = cvmx_usb_read_csr32(usb,
2405 CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2407 * If the channel isn't enabled then the transaction already
2408 * completed.
2410 if (usbc_hcchar.s.chena) {
2411 usbc_hcchar.s.chdis = 1;
2412 cvmx_usb_write_csr32(usb,
2413 CVMX_USBCX_HCCHARX(pipe->channel,
2414 usb->index),
2415 usbc_hcchar.u32);
2418 cvmx_usb_perform_complete(usb, pipe, transaction,
2419 CVMX_USB_COMPLETE_CANCEL);
2420 return 0;
2425 * Cancel all outstanding requests in a pipe. Logically all this
2426 * does is call cvmx_usb_cancel() in a loop.
2428 * @usb: USB device state populated by cvmx_usb_initialize().
2429 * @pipe: Pipe to cancel requests in.
2431 * Returns: 0 or a negative error code.
2433 static int cvmx_usb_cancel_all(struct cvmx_usb_state *usb,
2434 struct cvmx_usb_pipe *pipe)
2436 struct cvmx_usb_transaction *transaction, *next;
2438 /* Simply loop through and attempt to cancel each transaction */
2439 list_for_each_entry_safe(transaction, next, &pipe->transactions, node) {
2440 int result = cvmx_usb_cancel(usb, pipe, transaction);
2442 if (unlikely(result != 0))
2443 return result;
2445 return 0;
2450 * Close a pipe created with cvmx_usb_open_pipe().
2452 * @usb: USB device state populated by cvmx_usb_initialize().
2453 * @pipe: Pipe to close.
2455 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2456 * outstanding transfers.
2458 static int cvmx_usb_close_pipe(struct cvmx_usb_state *usb,
2459 struct cvmx_usb_pipe *pipe)
2461 /* Fail if the pipe has pending transactions */
2462 if (!list_empty(&pipe->transactions))
2463 return -EBUSY;
2465 list_del(&pipe->node);
2466 kfree(pipe);
2468 return 0;
2472 * Get the current USB protocol level frame number. The frame
2473 * number is always in the range of 0-0x7ff.
2475 * @usb: USB device state populated by cvmx_usb_initialize().
2477 * Returns: USB frame number
2479 static int cvmx_usb_get_frame_number(struct cvmx_usb_state *usb)
2481 int frame_number;
2482 union cvmx_usbcx_hfnum usbc_hfnum;
2484 usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2485 frame_number = usbc_hfnum.s.frnum;
2487 return frame_number;
2492 * Poll a channel for status
2494 * @usb: USB device
2495 * @channel: Channel to poll
2497 * Returns: Zero on success
2499 static int cvmx_usb_poll_channel(struct cvmx_usb_state *usb, int channel)
2501 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2502 struct usb_hcd *hcd = octeon_to_hcd(priv);
2503 struct device *dev = hcd->self.controller;
2504 union cvmx_usbcx_hcintx usbc_hcint;
2505 union cvmx_usbcx_hctsizx usbc_hctsiz;
2506 union cvmx_usbcx_hccharx usbc_hcchar;
2507 struct cvmx_usb_pipe *pipe;
2508 struct cvmx_usb_transaction *transaction;
2509 int bytes_this_transfer;
2510 int bytes_in_last_packet;
2511 int packets_processed;
2512 int buffer_space_left;
2514 /* Read the interrupt status bits for the channel */
2515 usbc_hcint.u32 = cvmx_usb_read_csr32(usb,
2516 CVMX_USBCX_HCINTX(channel, usb->index));
2518 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2519 usbc_hcchar.u32 = cvmx_usb_read_csr32(usb,
2520 CVMX_USBCX_HCCHARX(channel, usb->index));
2522 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2524 * There seems to be a bug in CN31XX which can cause
2525 * interrupt IN transfers to get stuck until we do a
2526 * write of HCCHARX without changing things
2528 cvmx_usb_write_csr32(usb,
2529 CVMX_USBCX_HCCHARX(channel,
2530 usb->index),
2531 usbc_hcchar.u32);
2532 return 0;
2536 * In non DMA mode the channels don't halt themselves. We need
2537 * to manually disable channels that are left running
2539 if (!usbc_hcint.s.chhltd) {
2540 if (usbc_hcchar.s.chena) {
2541 union cvmx_usbcx_hcintmskx hcintmsk;
2542 /* Disable all interrupts except CHHLTD */
2543 hcintmsk.u32 = 0;
2544 hcintmsk.s.chhltdmsk = 1;
2545 cvmx_usb_write_csr32(usb,
2546 CVMX_USBCX_HCINTMSKX(channel,
2547 usb->index),
2548 hcintmsk.u32);
2549 usbc_hcchar.s.chdis = 1;
2550 cvmx_usb_write_csr32(usb,
2551 CVMX_USBCX_HCCHARX(channel,
2552 usb->index),
2553 usbc_hcchar.u32);
2554 return 0;
2555 } else if (usbc_hcint.s.xfercompl) {
2557 * Successful IN/OUT with transfer complete.
2558 * Channel halt isn't needed.
2560 } else {
2561 dev_err(dev, "USB%d: Channel %d interrupt without halt\n",
2562 usb->index, channel);
2563 return 0;
2566 } else {
2568 * There is are no interrupts that we need to process when the
2569 * channel is still running
2571 if (!usbc_hcint.s.chhltd)
2572 return 0;
2575 /* Disable the channel interrupts now that it is done */
2576 cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2577 usb->idle_hardware_channels |= (1<<channel);
2579 /* Make sure this channel is tied to a valid pipe */
2580 pipe = usb->pipe_for_channel[channel];
2581 prefetch(pipe);
2582 if (!pipe)
2583 return 0;
2584 transaction = list_first_entry(&pipe->transactions,
2585 typeof(*transaction),
2586 node);
2587 prefetch(transaction);
2590 * Disconnect this pipe from the HW channel. Later the schedule
2591 * function will figure out which pipe needs to go
2593 usb->pipe_for_channel[channel] = NULL;
2594 pipe->flags &= ~CVMX_USB_PIPE_FLAGS_SCHEDULED;
2597 * Read the channel config info so we can figure out how much data
2598 * transferred
2600 usbc_hcchar.u32 = cvmx_usb_read_csr32(usb,
2601 CVMX_USBCX_HCCHARX(channel, usb->index));
2602 usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb,
2603 CVMX_USBCX_HCTSIZX(channel, usb->index));
2606 * Calculating the number of bytes successfully transferred is dependent
2607 * on the transfer direction
2609 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2610 if (usbc_hcchar.s.epdir) {
2612 * IN transactions are easy. For every byte received the
2613 * hardware decrements xfersize. All we need to do is subtract
2614 * the current value of xfersize from its starting value and we
2615 * know how many bytes were written to the buffer
2617 bytes_this_transfer = transaction->xfersize -
2618 usbc_hctsiz.s.xfersize;
2619 } else {
2621 * OUT transaction don't decrement xfersize. Instead pktcnt is
2622 * decremented on every successful packet send. The hardware
2623 * does this when it receives an ACK, or NYET. If it doesn't
2624 * receive one of these responses pktcnt doesn't change
2626 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2628 * The last packet may not be a full transfer if we didn't have
2629 * enough data
2631 if (bytes_this_transfer > transaction->xfersize)
2632 bytes_this_transfer = transaction->xfersize;
2634 /* Figure out how many bytes were in the last packet of the transfer */
2635 if (packets_processed)
2636 bytes_in_last_packet = bytes_this_transfer -
2637 (packets_processed - 1) * usbc_hcchar.s.mps;
2638 else
2639 bytes_in_last_packet = bytes_this_transfer;
2642 * As a special case, setup transactions output the setup header, not
2643 * the user's data. For this reason we don't count setup data as bytes
2644 * transferred
2646 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2647 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2648 bytes_this_transfer = 0;
2651 * Add the bytes transferred to the running total. It is important that
2652 * bytes_this_transfer doesn't count any data that needs to be
2653 * retransmitted
2655 transaction->actual_bytes += bytes_this_transfer;
2656 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2657 buffer_space_left = transaction->iso_packets[0].length -
2658 transaction->actual_bytes;
2659 else
2660 buffer_space_left = transaction->buffer_length -
2661 transaction->actual_bytes;
2664 * We need to remember the PID toggle state for the next transaction.
2665 * The hardware already updated it for the next transaction
2667 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2670 * For high speed bulk out, assume the next transaction will need to do
2671 * a ping before proceeding. If this isn't true the ACK processing below
2672 * will clear this flag
2674 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2675 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2676 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2677 pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING;
2679 if (usbc_hcint.s.stall) {
2681 * STALL as a response means this transaction cannot be
2682 * completed because the device can't process transactions. Tell
2683 * the user. Any data that was transferred will be counted on
2684 * the actual bytes transferred
2686 pipe->pid_toggle = 0;
2687 cvmx_usb_perform_complete(usb, pipe, transaction,
2688 CVMX_USB_COMPLETE_STALL);
2689 } else if (usbc_hcint.s.xacterr) {
2691 * We know at least one packet worked if we get a ACK or NAK.
2692 * Reset the retry counter
2694 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2695 transaction->retries = 0;
2696 transaction->retries++;
2697 if (transaction->retries > MAX_RETRIES) {
2699 * XactErr as a response means the device signaled
2700 * something wrong with the transfer. For example, PID
2701 * toggle errors cause these
2703 cvmx_usb_perform_complete(usb, pipe, transaction,
2704 CVMX_USB_COMPLETE_XACTERR);
2705 } else {
2707 * If this was a split then clear our split in progress
2708 * marker
2710 if (usb->active_split == transaction)
2711 usb->active_split = NULL;
2713 * Rewind to the beginning of the transaction by anding
2714 * off the split complete bit
2716 transaction->stage &= ~1;
2717 pipe->split_sc_frame = -1;
2718 pipe->next_tx_frame += pipe->interval;
2719 if (pipe->next_tx_frame < usb->frame_number)
2720 pipe->next_tx_frame =
2721 usb->frame_number + pipe->interval -
2722 (usb->frame_number -
2723 pipe->next_tx_frame) % pipe->interval;
2725 } else if (usbc_hcint.s.bblerr) {
2726 /* Babble Error (BblErr) */
2727 cvmx_usb_perform_complete(usb, pipe, transaction,
2728 CVMX_USB_COMPLETE_BABBLEERR);
2729 } else if (usbc_hcint.s.datatglerr) {
2730 /* Data toggle error */
2731 cvmx_usb_perform_complete(usb, pipe, transaction,
2732 CVMX_USB_COMPLETE_DATATGLERR);
2733 } else if (usbc_hcint.s.nyet) {
2735 * NYET as a response is only allowed in three cases: as a
2736 * response to a ping, as a response to a split transaction, and
2737 * as a response to a bulk out. The ping case is handled by
2738 * hardware, so we only have splits and bulk out
2740 if (!cvmx_usb_pipe_needs_split(usb, pipe)) {
2741 transaction->retries = 0;
2743 * If there is more data to go then we need to try
2744 * again. Otherwise this transaction is complete
2746 if ((buffer_space_left == 0) ||
2747 (bytes_in_last_packet < pipe->max_packet))
2748 cvmx_usb_perform_complete(usb, pipe,
2749 transaction,
2750 CVMX_USB_COMPLETE_SUCCESS);
2751 } else {
2753 * Split transactions retry the split complete 4 times
2754 * then rewind to the start split and do the entire
2755 * transactions again
2757 transaction->retries++;
2758 if ((transaction->retries & 0x3) == 0) {
2760 * Rewind to the beginning of the transaction by
2761 * anding off the split complete bit
2763 transaction->stage &= ~1;
2764 pipe->split_sc_frame = -1;
2767 } else if (usbc_hcint.s.ack) {
2768 transaction->retries = 0;
2770 * The ACK bit can only be checked after the other error bits.
2771 * This is because a multi packet transfer may succeed in a
2772 * number of packets and then get a different response on the
2773 * last packet. In this case both ACK and the last response bit
2774 * will be set. If none of the other response bits is set, then
2775 * the last packet must have been an ACK
2777 * Since we got an ACK, we know we don't need to do a ping on
2778 * this pipe
2780 pipe->flags &= ~CVMX_USB_PIPE_FLAGS_NEED_PING;
2782 switch (transaction->type) {
2783 case CVMX_USB_TRANSFER_CONTROL:
2784 switch (transaction->stage) {
2785 case CVMX_USB_STAGE_NON_CONTROL:
2786 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2787 /* This should be impossible */
2788 cvmx_usb_perform_complete(usb, pipe,
2789 transaction, CVMX_USB_COMPLETE_ERROR);
2790 break;
2791 case CVMX_USB_STAGE_SETUP:
2792 pipe->pid_toggle = 1;
2793 if (cvmx_usb_pipe_needs_split(usb, pipe))
2794 transaction->stage =
2795 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2796 else {
2797 struct usb_ctrlrequest *header =
2798 cvmx_phys_to_ptr(transaction->control_header);
2799 if (header->wLength)
2800 transaction->stage =
2801 CVMX_USB_STAGE_DATA;
2802 else
2803 transaction->stage =
2804 CVMX_USB_STAGE_STATUS;
2806 break;
2807 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2809 struct usb_ctrlrequest *header =
2810 cvmx_phys_to_ptr(transaction->control_header);
2811 if (header->wLength)
2812 transaction->stage =
2813 CVMX_USB_STAGE_DATA;
2814 else
2815 transaction->stage =
2816 CVMX_USB_STAGE_STATUS;
2818 break;
2819 case CVMX_USB_STAGE_DATA:
2820 if (cvmx_usb_pipe_needs_split(usb, pipe)) {
2821 transaction->stage =
2822 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2824 * For setup OUT data that are splits,
2825 * the hardware doesn't appear to count
2826 * transferred data. Here we manually
2827 * update the data transferred
2829 if (!usbc_hcchar.s.epdir) {
2830 if (buffer_space_left < pipe->max_packet)
2831 transaction->actual_bytes +=
2832 buffer_space_left;
2833 else
2834 transaction->actual_bytes +=
2835 pipe->max_packet;
2837 } else if ((buffer_space_left == 0) ||
2838 (bytes_in_last_packet <
2839 pipe->max_packet)) {
2840 pipe->pid_toggle = 1;
2841 transaction->stage =
2842 CVMX_USB_STAGE_STATUS;
2844 break;
2845 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2846 if ((buffer_space_left == 0) ||
2847 (bytes_in_last_packet <
2848 pipe->max_packet)) {
2849 pipe->pid_toggle = 1;
2850 transaction->stage =
2851 CVMX_USB_STAGE_STATUS;
2852 } else {
2853 transaction->stage =
2854 CVMX_USB_STAGE_DATA;
2856 break;
2857 case CVMX_USB_STAGE_STATUS:
2858 if (cvmx_usb_pipe_needs_split(usb, pipe))
2859 transaction->stage =
2860 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2861 else
2862 cvmx_usb_perform_complete(usb, pipe,
2863 transaction,
2864 CVMX_USB_COMPLETE_SUCCESS);
2865 break;
2866 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2867 cvmx_usb_perform_complete(usb, pipe,
2868 transaction,
2869 CVMX_USB_COMPLETE_SUCCESS);
2870 break;
2872 break;
2873 case CVMX_USB_TRANSFER_BULK:
2874 case CVMX_USB_TRANSFER_INTERRUPT:
2876 * The only time a bulk transfer isn't complete when it
2877 * finishes with an ACK is during a split transaction.
2878 * For splits we need to continue the transfer if more
2879 * data is needed
2881 if (cvmx_usb_pipe_needs_split(usb, pipe)) {
2882 if (transaction->stage ==
2883 CVMX_USB_STAGE_NON_CONTROL)
2884 transaction->stage =
2885 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2886 else {
2887 if (buffer_space_left &&
2888 (bytes_in_last_packet ==
2889 pipe->max_packet))
2890 transaction->stage =
2891 CVMX_USB_STAGE_NON_CONTROL;
2892 else {
2893 if (transaction->type ==
2894 CVMX_USB_TRANSFER_INTERRUPT)
2895 pipe->next_tx_frame +=
2896 pipe->interval;
2897 cvmx_usb_perform_complete(
2898 usb,
2899 pipe,
2900 transaction,
2901 CVMX_USB_COMPLETE_SUCCESS);
2904 } else {
2905 if ((pipe->device_speed ==
2906 CVMX_USB_SPEED_HIGH) &&
2907 (pipe->transfer_type ==
2908 CVMX_USB_TRANSFER_BULK) &&
2909 (pipe->transfer_dir ==
2910 CVMX_USB_DIRECTION_OUT) &&
2911 (usbc_hcint.s.nak))
2912 pipe->flags |=
2913 CVMX_USB_PIPE_FLAGS_NEED_PING;
2914 if (!buffer_space_left ||
2915 (bytes_in_last_packet <
2916 pipe->max_packet)) {
2917 if (transaction->type ==
2918 CVMX_USB_TRANSFER_INTERRUPT)
2919 pipe->next_tx_frame +=
2920 pipe->interval;
2921 cvmx_usb_perform_complete(usb, pipe,
2922 transaction,
2923 CVMX_USB_COMPLETE_SUCCESS);
2926 break;
2927 case CVMX_USB_TRANSFER_ISOCHRONOUS:
2928 if (cvmx_usb_pipe_needs_split(usb, pipe)) {
2930 * ISOCHRONOUS OUT splits don't require a
2931 * complete split stage. Instead they use a
2932 * sequence of begin OUT splits to transfer the
2933 * data 188 bytes at a time. Once the transfer
2934 * is complete, the pipe sleeps until the next
2935 * schedule interval
2937 if (pipe->transfer_dir ==
2938 CVMX_USB_DIRECTION_OUT) {
2940 * If no space left or this wasn't a max
2941 * size packet then this transfer is
2942 * complete. Otherwise start it again to
2943 * send the next 188 bytes
2945 if (!buffer_space_left ||
2946 (bytes_this_transfer < 188)) {
2947 pipe->next_tx_frame +=
2948 pipe->interval;
2949 cvmx_usb_perform_complete(usb,
2950 pipe, transaction,
2951 CVMX_USB_COMPLETE_SUCCESS);
2953 } else {
2954 if (transaction->stage ==
2955 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
2957 * We are in the incoming data
2958 * phase. Keep getting data
2959 * until we run out of space or
2960 * get a small packet
2962 if ((buffer_space_left == 0) ||
2963 (bytes_in_last_packet <
2964 pipe->max_packet)) {
2965 pipe->next_tx_frame +=
2966 pipe->interval;
2967 cvmx_usb_perform_complete(
2968 usb,
2969 pipe,
2970 transaction,
2971 CVMX_USB_COMPLETE_SUCCESS);
2973 } else
2974 transaction->stage =
2975 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2977 } else {
2978 pipe->next_tx_frame += pipe->interval;
2979 cvmx_usb_perform_complete(usb, pipe,
2980 transaction,
2981 CVMX_USB_COMPLETE_SUCCESS);
2983 break;
2985 } else if (usbc_hcint.s.nak) {
2987 * If this was a split then clear our split in progress marker.
2989 if (usb->active_split == transaction)
2990 usb->active_split = NULL;
2992 * NAK as a response means the device couldn't accept the
2993 * transaction, but it should be retried in the future. Rewind
2994 * to the beginning of the transaction by anding off the split
2995 * complete bit. Retry in the next interval
2997 transaction->retries = 0;
2998 transaction->stage &= ~1;
2999 pipe->next_tx_frame += pipe->interval;
3000 if (pipe->next_tx_frame < usb->frame_number)
3001 pipe->next_tx_frame = usb->frame_number +
3002 pipe->interval -
3003 (usb->frame_number - pipe->next_tx_frame) %
3004 pipe->interval;
3005 } else {
3006 struct cvmx_usb_port_status port;
3008 port = cvmx_usb_get_status(usb);
3009 if (port.port_enabled) {
3010 /* We'll retry the exact same transaction again */
3011 transaction->retries++;
3012 } else {
3014 * We get channel halted interrupts with no result bits
3015 * sets when the cable is unplugged
3017 cvmx_usb_perform_complete(usb, pipe, transaction,
3018 CVMX_USB_COMPLETE_ERROR);
3021 return 0;
3024 static void octeon_usb_port_callback(struct cvmx_usb_state *usb)
3026 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
3028 spin_unlock(&priv->lock);
3029 usb_hcd_poll_rh_status(octeon_to_hcd(priv));
3030 spin_lock(&priv->lock);
3034 * Poll the USB block for status and call all needed callback
3035 * handlers. This function is meant to be called in the interrupt
3036 * handler for the USB controller. It can also be called
3037 * periodically in a loop for non-interrupt based operation.
3039 * @usb: USB device state populated by cvmx_usb_initialize().
3041 * Returns: 0 or a negative error code.
3043 static int cvmx_usb_poll(struct cvmx_usb_state *usb)
3045 union cvmx_usbcx_hfnum usbc_hfnum;
3046 union cvmx_usbcx_gintsts usbc_gintsts;
3048 prefetch_range(usb, sizeof(*usb));
3050 /* Update the frame counter */
3051 usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
3052 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
3053 usb->frame_number += 0x4000;
3054 usb->frame_number &= ~0x3fffull;
3055 usb->frame_number |= usbc_hfnum.s.frnum;
3057 /* Read the pending interrupts */
3058 usbc_gintsts.u32 = cvmx_usb_read_csr32(usb,
3059 CVMX_USBCX_GINTSTS(usb->index));
3061 /* Clear the interrupts now that we know about them */
3062 cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index),
3063 usbc_gintsts.u32);
3065 if (usbc_gintsts.s.rxflvl) {
3067 * RxFIFO Non-Empty (RxFLvl)
3068 * Indicates that there is at least one packet pending to be
3069 * read from the RxFIFO.
3071 * In DMA mode this is handled by hardware
3073 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3074 cvmx_usb_poll_rx_fifo(usb);
3076 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
3077 /* Fill the Tx FIFOs when not in DMA mode */
3078 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3079 cvmx_usb_poll_tx_fifo(usb);
3081 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
3082 union cvmx_usbcx_hprt usbc_hprt;
3084 * Disconnect Detected Interrupt (DisconnInt)
3085 * Asserted when a device disconnect is detected.
3087 * Host Port Interrupt (PrtInt)
3088 * The core sets this bit to indicate a change in port status of
3089 * one of the O2P USB core ports in Host mode. The application
3090 * must read the Host Port Control and Status (HPRT) register to
3091 * determine the exact event that caused this interrupt. The
3092 * application must clear the appropriate status bit in the Host
3093 * Port Control and Status register to clear this bit.
3095 * Call the user's port callback
3097 octeon_usb_port_callback(usb);
3098 /* Clear the port change bits */
3099 usbc_hprt.u32 = cvmx_usb_read_csr32(usb,
3100 CVMX_USBCX_HPRT(usb->index));
3101 usbc_hprt.s.prtena = 0;
3102 cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index),
3103 usbc_hprt.u32);
3105 if (usbc_gintsts.s.hchint) {
3107 * Host Channels Interrupt (HChInt)
3108 * The core sets this bit to indicate that an interrupt is
3109 * pending on one of the channels of the core (in Host mode).
3110 * The application must read the Host All Channels Interrupt
3111 * (HAINT) register to determine the exact number of the channel
3112 * on which the interrupt occurred, and then read the
3113 * corresponding Host Channel-n Interrupt (HCINTn) register to
3114 * determine the exact cause of the interrupt. The application
3115 * must clear the appropriate status bit in the HCINTn register
3116 * to clear this bit.
3118 union cvmx_usbcx_haint usbc_haint;
3120 usbc_haint.u32 = cvmx_usb_read_csr32(usb,
3121 CVMX_USBCX_HAINT(usb->index));
3122 while (usbc_haint.u32) {
3123 int channel;
3125 channel = __fls(usbc_haint.u32);
3126 cvmx_usb_poll_channel(usb, channel);
3127 usbc_haint.u32 ^= 1<<channel;
3131 cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3133 return 0;
3136 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3137 static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd)
3139 return (struct octeon_hcd *)(hcd->hcd_priv);
3142 static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd)
3144 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3145 unsigned long flags;
3147 spin_lock_irqsave(&priv->lock, flags);
3148 cvmx_usb_poll(&priv->usb);
3149 spin_unlock_irqrestore(&priv->lock, flags);
3150 return IRQ_HANDLED;
3153 static int octeon_usb_start(struct usb_hcd *hcd)
3155 hcd->state = HC_STATE_RUNNING;
3156 return 0;
3159 static void octeon_usb_stop(struct usb_hcd *hcd)
3161 hcd->state = HC_STATE_HALT;
3164 static int octeon_usb_get_frame_number(struct usb_hcd *hcd)
3166 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3168 return cvmx_usb_get_frame_number(&priv->usb);
3171 static int octeon_usb_urb_enqueue(struct usb_hcd *hcd,
3172 struct urb *urb,
3173 gfp_t mem_flags)
3175 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3176 struct device *dev = hcd->self.controller;
3177 struct cvmx_usb_transaction *transaction = NULL;
3178 struct cvmx_usb_pipe *pipe;
3179 unsigned long flags;
3180 struct cvmx_usb_iso_packet *iso_packet;
3181 struct usb_host_endpoint *ep = urb->ep;
3182 int rc;
3184 urb->status = 0;
3185 spin_lock_irqsave(&priv->lock, flags);
3187 rc = usb_hcd_link_urb_to_ep(hcd, urb);
3188 if (rc) {
3189 spin_unlock_irqrestore(&priv->lock, flags);
3190 return rc;
3193 if (!ep->hcpriv) {
3194 enum cvmx_usb_transfer transfer_type;
3195 enum cvmx_usb_speed speed;
3196 int split_device = 0;
3197 int split_port = 0;
3199 switch (usb_pipetype(urb->pipe)) {
3200 case PIPE_ISOCHRONOUS:
3201 transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS;
3202 break;
3203 case PIPE_INTERRUPT:
3204 transfer_type = CVMX_USB_TRANSFER_INTERRUPT;
3205 break;
3206 case PIPE_CONTROL:
3207 transfer_type = CVMX_USB_TRANSFER_CONTROL;
3208 break;
3209 default:
3210 transfer_type = CVMX_USB_TRANSFER_BULK;
3211 break;
3213 switch (urb->dev->speed) {
3214 case USB_SPEED_LOW:
3215 speed = CVMX_USB_SPEED_LOW;
3216 break;
3217 case USB_SPEED_FULL:
3218 speed = CVMX_USB_SPEED_FULL;
3219 break;
3220 default:
3221 speed = CVMX_USB_SPEED_HIGH;
3222 break;
3225 * For slow devices on high speed ports we need to find the hub
3226 * that does the speed translation so we know where to send the
3227 * split transactions.
3229 if (speed != CVMX_USB_SPEED_HIGH) {
3231 * Start at this device and work our way up the usb
3232 * tree.
3234 struct usb_device *dev = urb->dev;
3236 while (dev->parent) {
3238 * If our parent is high speed then he'll
3239 * receive the splits.
3241 if (dev->parent->speed == USB_SPEED_HIGH) {
3242 split_device = dev->parent->devnum;
3243 split_port = dev->portnum;
3244 break;
3247 * Move up the tree one level. If we make it all
3248 * the way up the tree, then the port must not
3249 * be in high speed mode and we don't need a
3250 * split.
3252 dev = dev->parent;
3255 pipe = cvmx_usb_open_pipe(&priv->usb, usb_pipedevice(urb->pipe),
3256 usb_pipeendpoint(urb->pipe), speed,
3257 le16_to_cpu(ep->desc.wMaxPacketSize)
3258 & 0x7ff,
3259 transfer_type,
3260 usb_pipein(urb->pipe) ?
3261 CVMX_USB_DIRECTION_IN :
3262 CVMX_USB_DIRECTION_OUT,
3263 urb->interval,
3264 (le16_to_cpu(ep->desc.wMaxPacketSize)
3265 >> 11) & 0x3,
3266 split_device, split_port);
3267 if (!pipe) {
3268 usb_hcd_unlink_urb_from_ep(hcd, urb);
3269 spin_unlock_irqrestore(&priv->lock, flags);
3270 dev_dbg(dev, "Failed to create pipe\n");
3271 return -ENOMEM;
3273 ep->hcpriv = pipe;
3274 } else {
3275 pipe = ep->hcpriv;
3278 switch (usb_pipetype(urb->pipe)) {
3279 case PIPE_ISOCHRONOUS:
3280 dev_dbg(dev, "Submit isochronous to %d.%d\n",
3281 usb_pipedevice(urb->pipe),
3282 usb_pipeendpoint(urb->pipe));
3284 * Allocate a structure to use for our private list of
3285 * isochronous packets.
3287 iso_packet = kmalloc(urb->number_of_packets *
3288 sizeof(struct cvmx_usb_iso_packet),
3289 GFP_ATOMIC);
3290 if (iso_packet) {
3291 int i;
3292 /* Fill the list with the data from the URB */
3293 for (i = 0; i < urb->number_of_packets; i++) {
3294 iso_packet[i].offset =
3295 urb->iso_frame_desc[i].offset;
3296 iso_packet[i].length =
3297 urb->iso_frame_desc[i].length;
3298 iso_packet[i].status =
3299 CVMX_USB_COMPLETE_ERROR;
3302 * Store a pointer to the list in the URB setup_packet
3303 * field. We know this currently isn't being used and
3304 * this saves us a bunch of logic.
3306 urb->setup_packet = (char *)iso_packet;
3307 transaction = cvmx_usb_submit_isochronous(&priv->usb,
3308 pipe, urb);
3310 * If submit failed we need to free our private packet
3311 * list.
3313 if (!transaction) {
3314 urb->setup_packet = NULL;
3315 kfree(iso_packet);
3318 break;
3319 case PIPE_INTERRUPT:
3320 dev_dbg(dev, "Submit interrupt to %d.%d\n",
3321 usb_pipedevice(urb->pipe),
3322 usb_pipeendpoint(urb->pipe));
3323 transaction = cvmx_usb_submit_interrupt(&priv->usb, pipe, urb);
3324 break;
3325 case PIPE_CONTROL:
3326 dev_dbg(dev, "Submit control to %d.%d\n",
3327 usb_pipedevice(urb->pipe),
3328 usb_pipeendpoint(urb->pipe));
3329 transaction = cvmx_usb_submit_control(&priv->usb, pipe, urb);
3330 break;
3331 case PIPE_BULK:
3332 dev_dbg(dev, "Submit bulk to %d.%d\n",
3333 usb_pipedevice(urb->pipe),
3334 usb_pipeendpoint(urb->pipe));
3335 transaction = cvmx_usb_submit_bulk(&priv->usb, pipe, urb);
3336 break;
3338 if (!transaction) {
3339 usb_hcd_unlink_urb_from_ep(hcd, urb);
3340 spin_unlock_irqrestore(&priv->lock, flags);
3341 dev_dbg(dev, "Failed to submit\n");
3342 return -ENOMEM;
3344 urb->hcpriv = transaction;
3345 spin_unlock_irqrestore(&priv->lock, flags);
3346 return 0;
3349 static int octeon_usb_urb_dequeue(struct usb_hcd *hcd,
3350 struct urb *urb,
3351 int status)
3353 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3354 unsigned long flags;
3355 int rc;
3357 if (!urb->dev)
3358 return -EINVAL;
3360 spin_lock_irqsave(&priv->lock, flags);
3362 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
3363 if (rc)
3364 goto out;
3366 urb->status = status;
3367 cvmx_usb_cancel(&priv->usb, urb->ep->hcpriv, urb->hcpriv);
3369 out:
3370 spin_unlock_irqrestore(&priv->lock, flags);
3372 return rc;
3375 static void octeon_usb_endpoint_disable(struct usb_hcd *hcd,
3376 struct usb_host_endpoint *ep)
3378 struct device *dev = hcd->self.controller;
3380 if (ep->hcpriv) {
3381 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3382 struct cvmx_usb_pipe *pipe = ep->hcpriv;
3383 unsigned long flags;
3385 spin_lock_irqsave(&priv->lock, flags);
3386 cvmx_usb_cancel_all(&priv->usb, pipe);
3387 if (cvmx_usb_close_pipe(&priv->usb, pipe))
3388 dev_dbg(dev, "Closing pipe %p failed\n", pipe);
3389 spin_unlock_irqrestore(&priv->lock, flags);
3390 ep->hcpriv = NULL;
3394 static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf)
3396 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3397 struct cvmx_usb_port_status port_status;
3398 unsigned long flags;
3400 spin_lock_irqsave(&priv->lock, flags);
3401 port_status = cvmx_usb_get_status(&priv->usb);
3402 spin_unlock_irqrestore(&priv->lock, flags);
3403 buf[0] = 0;
3404 buf[0] = port_status.connect_change << 1;
3406 return buf[0] != 0;
3409 static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
3410 u16 wIndex, char *buf, u16 wLength)
3412 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3413 struct device *dev = hcd->self.controller;
3414 struct cvmx_usb_port_status usb_port_status;
3415 int port_status;
3416 struct usb_hub_descriptor *desc;
3417 unsigned long flags;
3419 switch (typeReq) {
3420 case ClearHubFeature:
3421 dev_dbg(dev, "ClearHubFeature\n");
3422 switch (wValue) {
3423 case C_HUB_LOCAL_POWER:
3424 case C_HUB_OVER_CURRENT:
3425 /* Nothing required here */
3426 break;
3427 default:
3428 return -EINVAL;
3430 break;
3431 case ClearPortFeature:
3432 dev_dbg(dev, "ClearPortFeature\n");
3433 if (wIndex != 1) {
3434 dev_dbg(dev, " INVALID\n");
3435 return -EINVAL;
3438 switch (wValue) {
3439 case USB_PORT_FEAT_ENABLE:
3440 dev_dbg(dev, " ENABLE\n");
3441 spin_lock_irqsave(&priv->lock, flags);
3442 cvmx_usb_disable(&priv->usb);
3443 spin_unlock_irqrestore(&priv->lock, flags);
3444 break;
3445 case USB_PORT_FEAT_SUSPEND:
3446 dev_dbg(dev, " SUSPEND\n");
3447 /* Not supported on Octeon */
3448 break;
3449 case USB_PORT_FEAT_POWER:
3450 dev_dbg(dev, " POWER\n");
3451 /* Not supported on Octeon */
3452 break;
3453 case USB_PORT_FEAT_INDICATOR:
3454 dev_dbg(dev, " INDICATOR\n");
3455 /* Port inidicator not supported */
3456 break;
3457 case USB_PORT_FEAT_C_CONNECTION:
3458 dev_dbg(dev, " C_CONNECTION\n");
3459 /* Clears drivers internal connect status change flag */
3460 spin_lock_irqsave(&priv->lock, flags);
3461 priv->usb.port_status =
3462 cvmx_usb_get_status(&priv->usb);
3463 spin_unlock_irqrestore(&priv->lock, flags);
3464 break;
3465 case USB_PORT_FEAT_C_RESET:
3466 dev_dbg(dev, " C_RESET\n");
3468 * Clears the driver's internal Port Reset Change flag.
3470 spin_lock_irqsave(&priv->lock, flags);
3471 priv->usb.port_status =
3472 cvmx_usb_get_status(&priv->usb);
3473 spin_unlock_irqrestore(&priv->lock, flags);
3474 break;
3475 case USB_PORT_FEAT_C_ENABLE:
3476 dev_dbg(dev, " C_ENABLE\n");
3478 * Clears the driver's internal Port Enable/Disable
3479 * Change flag.
3481 spin_lock_irqsave(&priv->lock, flags);
3482 priv->usb.port_status =
3483 cvmx_usb_get_status(&priv->usb);
3484 spin_unlock_irqrestore(&priv->lock, flags);
3485 break;
3486 case USB_PORT_FEAT_C_SUSPEND:
3487 dev_dbg(dev, " C_SUSPEND\n");
3489 * Clears the driver's internal Port Suspend Change
3490 * flag, which is set when resume signaling on the host
3491 * port is complete.
3493 break;
3494 case USB_PORT_FEAT_C_OVER_CURRENT:
3495 dev_dbg(dev, " C_OVER_CURRENT\n");
3496 /* Clears the driver's overcurrent Change flag */
3497 spin_lock_irqsave(&priv->lock, flags);
3498 priv->usb.port_status =
3499 cvmx_usb_get_status(&priv->usb);
3500 spin_unlock_irqrestore(&priv->lock, flags);
3501 break;
3502 default:
3503 dev_dbg(dev, " UNKNOWN\n");
3504 return -EINVAL;
3506 break;
3507 case GetHubDescriptor:
3508 dev_dbg(dev, "GetHubDescriptor\n");
3509 desc = (struct usb_hub_descriptor *)buf;
3510 desc->bDescLength = 9;
3511 desc->bDescriptorType = 0x29;
3512 desc->bNbrPorts = 1;
3513 desc->wHubCharacteristics = cpu_to_le16(0x08);
3514 desc->bPwrOn2PwrGood = 1;
3515 desc->bHubContrCurrent = 0;
3516 desc->u.hs.DeviceRemovable[0] = 0;
3517 desc->u.hs.DeviceRemovable[1] = 0xff;
3518 break;
3519 case GetHubStatus:
3520 dev_dbg(dev, "GetHubStatus\n");
3521 *(__le32 *) buf = 0;
3522 break;
3523 case GetPortStatus:
3524 dev_dbg(dev, "GetPortStatus\n");
3525 if (wIndex != 1) {
3526 dev_dbg(dev, " INVALID\n");
3527 return -EINVAL;
3530 spin_lock_irqsave(&priv->lock, flags);
3531 usb_port_status = cvmx_usb_get_status(&priv->usb);
3532 spin_unlock_irqrestore(&priv->lock, flags);
3533 port_status = 0;
3535 if (usb_port_status.connect_change) {
3536 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
3537 dev_dbg(dev, " C_CONNECTION\n");
3540 if (usb_port_status.port_enabled) {
3541 port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
3542 dev_dbg(dev, " C_ENABLE\n");
3545 if (usb_port_status.connected) {
3546 port_status |= (1 << USB_PORT_FEAT_CONNECTION);
3547 dev_dbg(dev, " CONNECTION\n");
3550 if (usb_port_status.port_enabled) {
3551 port_status |= (1 << USB_PORT_FEAT_ENABLE);
3552 dev_dbg(dev, " ENABLE\n");
3555 if (usb_port_status.port_over_current) {
3556 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
3557 dev_dbg(dev, " OVER_CURRENT\n");
3560 if (usb_port_status.port_powered) {
3561 port_status |= (1 << USB_PORT_FEAT_POWER);
3562 dev_dbg(dev, " POWER\n");
3565 if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) {
3566 port_status |= USB_PORT_STAT_HIGH_SPEED;
3567 dev_dbg(dev, " HIGHSPEED\n");
3568 } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) {
3569 port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
3570 dev_dbg(dev, " LOWSPEED\n");
3573 *((__le32 *) buf) = cpu_to_le32(port_status);
3574 break;
3575 case SetHubFeature:
3576 dev_dbg(dev, "SetHubFeature\n");
3577 /* No HUB features supported */
3578 break;
3579 case SetPortFeature:
3580 dev_dbg(dev, "SetPortFeature\n");
3581 if (wIndex != 1) {
3582 dev_dbg(dev, " INVALID\n");
3583 return -EINVAL;
3586 switch (wValue) {
3587 case USB_PORT_FEAT_SUSPEND:
3588 dev_dbg(dev, " SUSPEND\n");
3589 return -EINVAL;
3590 case USB_PORT_FEAT_POWER:
3591 dev_dbg(dev, " POWER\n");
3592 return -EINVAL;
3593 case USB_PORT_FEAT_RESET:
3594 dev_dbg(dev, " RESET\n");
3595 spin_lock_irqsave(&priv->lock, flags);
3596 cvmx_usb_disable(&priv->usb);
3597 if (cvmx_usb_enable(&priv->usb))
3598 dev_dbg(dev, "Failed to enable the port\n");
3599 spin_unlock_irqrestore(&priv->lock, flags);
3600 return 0;
3601 case USB_PORT_FEAT_INDICATOR:
3602 dev_dbg(dev, " INDICATOR\n");
3603 /* Not supported */
3604 break;
3605 default:
3606 dev_dbg(dev, " UNKNOWN\n");
3607 return -EINVAL;
3609 break;
3610 default:
3611 dev_dbg(dev, "Unknown root hub request\n");
3612 return -EINVAL;
3614 return 0;
3617 static const struct hc_driver octeon_hc_driver = {
3618 .description = "Octeon USB",
3619 .product_desc = "Octeon Host Controller",
3620 .hcd_priv_size = sizeof(struct octeon_hcd),
3621 .irq = octeon_usb_irq,
3622 .flags = HCD_MEMORY | HCD_USB2,
3623 .start = octeon_usb_start,
3624 .stop = octeon_usb_stop,
3625 .urb_enqueue = octeon_usb_urb_enqueue,
3626 .urb_dequeue = octeon_usb_urb_dequeue,
3627 .endpoint_disable = octeon_usb_endpoint_disable,
3628 .get_frame_number = octeon_usb_get_frame_number,
3629 .hub_status_data = octeon_usb_hub_status_data,
3630 .hub_control = octeon_usb_hub_control,
3631 .map_urb_for_dma = octeon_map_urb_for_dma,
3632 .unmap_urb_for_dma = octeon_unmap_urb_for_dma,
3635 static int octeon_usb_probe(struct platform_device *pdev)
3637 int status;
3638 int initialize_flags;
3639 int usb_num;
3640 struct resource *res_mem;
3641 struct device_node *usbn_node;
3642 int irq = platform_get_irq(pdev, 0);
3643 struct device *dev = &pdev->dev;
3644 struct octeon_hcd *priv;
3645 struct usb_hcd *hcd;
3646 unsigned long flags;
3647 u32 clock_rate = 48000000;
3648 bool is_crystal_clock = false;
3649 const char *clock_type;
3650 int i;
3652 if (dev->of_node == NULL) {
3653 dev_err(dev, "Error: empty of_node\n");
3654 return -ENXIO;
3656 usbn_node = dev->of_node->parent;
3658 i = of_property_read_u32(usbn_node,
3659 "refclk-frequency", &clock_rate);
3660 if (i) {
3661 dev_err(dev, "No USBN \"refclk-frequency\"\n");
3662 return -ENXIO;
3664 switch (clock_rate) {
3665 case 12000000:
3666 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
3667 break;
3668 case 24000000:
3669 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
3670 break;
3671 case 48000000:
3672 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
3673 break;
3674 default:
3675 dev_err(dev, "Illebal USBN \"refclk-frequency\" %u\n",
3676 clock_rate);
3677 return -ENXIO;
3681 i = of_property_read_string(usbn_node,
3682 "refclk-type", &clock_type);
3684 if (!i && strcmp("crystal", clock_type) == 0)
3685 is_crystal_clock = true;
3687 if (is_crystal_clock)
3688 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;
3689 else
3690 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
3692 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3693 if (res_mem == NULL) {
3694 dev_err(dev, "found no memory resource\n");
3695 return -ENXIO;
3697 usb_num = (res_mem->start >> 44) & 1;
3699 if (irq < 0) {
3700 /* Defective device tree, but we know how to fix it. */
3701 irq_hw_number_t hwirq = usb_num ? (1 << 6) + 17 : 56;
3703 irq = irq_create_mapping(NULL, hwirq);
3707 * Set the DMA mask to 64bits so we get buffers already translated for
3708 * DMA.
3710 dev->coherent_dma_mask = ~0;
3711 dev->dma_mask = &dev->coherent_dma_mask;
3714 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3715 * IOB priority registers. Under heavy network load USB
3716 * hardware can be starved by the IOB causing a crash. Give
3717 * it a priority boost if it has been waiting more than 400
3718 * cycles to avoid this situation.
3720 * Testing indicates that a cnt_val of 8192 is not sufficient,
3721 * but no failures are seen with 4096. We choose a value of
3722 * 400 to give a safety factor of 10.
3724 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
3725 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt;
3727 pri_cnt.u64 = 0;
3728 pri_cnt.s.cnt_enb = 1;
3729 pri_cnt.s.cnt_val = 400;
3730 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64);
3733 hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev));
3734 if (!hcd) {
3735 dev_dbg(dev, "Failed to allocate memory for HCD\n");
3736 return -1;
3738 hcd->uses_new_polling = 1;
3739 priv = (struct octeon_hcd *)hcd->hcd_priv;
3741 spin_lock_init(&priv->lock);
3743 status = cvmx_usb_initialize(&priv->usb, usb_num, initialize_flags);
3744 if (status) {
3745 dev_dbg(dev, "USB initialization failed with %d\n", status);
3746 kfree(hcd);
3747 return -1;
3750 /* This delay is needed for CN3010, but I don't know why... */
3751 mdelay(10);
3753 spin_lock_irqsave(&priv->lock, flags);
3754 cvmx_usb_poll(&priv->usb);
3755 spin_unlock_irqrestore(&priv->lock, flags);
3757 status = usb_add_hcd(hcd, irq, 0);
3758 if (status) {
3759 dev_dbg(dev, "USB add HCD failed with %d\n", status);
3760 kfree(hcd);
3761 return -1;
3763 device_wakeup_enable(hcd->self.controller);
3765 dev_info(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq);
3767 return 0;
3770 static int octeon_usb_remove(struct platform_device *pdev)
3772 int status;
3773 struct device *dev = &pdev->dev;
3774 struct usb_hcd *hcd = dev_get_drvdata(dev);
3775 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3776 unsigned long flags;
3778 usb_remove_hcd(hcd);
3779 spin_lock_irqsave(&priv->lock, flags);
3780 status = cvmx_usb_shutdown(&priv->usb);
3781 spin_unlock_irqrestore(&priv->lock, flags);
3782 if (status)
3783 dev_dbg(dev, "USB shutdown failed with %d\n", status);
3785 kfree(hcd);
3787 return 0;
3790 static const struct of_device_id octeon_usb_match[] = {
3792 .compatible = "cavium,octeon-5750-usbc",
3797 static struct platform_driver octeon_usb_driver = {
3798 .driver = {
3799 .name = "OcteonUSB",
3800 .of_match_table = octeon_usb_match,
3802 .probe = octeon_usb_probe,
3803 .remove = octeon_usb_remove,
3806 static int __init octeon_usb_driver_init(void)
3808 if (usb_disabled())
3809 return 0;
3811 return platform_driver_register(&octeon_usb_driver);
3813 module_init(octeon_usb_driver_init);
3815 static void __exit octeon_usb_driver_exit(void)
3817 if (usb_disabled())
3818 return;
3820 platform_driver_unregister(&octeon_usb_driver);
3822 module_exit(octeon_usb_driver_exit);
3824 MODULE_LICENSE("GPL");
3825 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
3826 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver.");