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parisc iommu: fix panic due to trying to allocate too large region
[linux/fpc-iii.git] / drivers / scsi / csiostor / csio_hw.h
blob489fc095cb034232eacf4a7a4747fa9999d00816
1 /*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __CSIO_HW_H__
36 #define __CSIO_HW_H__
37
38 #include <linux/kernel.h>
39 #include <linux/pci.h>
40 #include <linux/device.h>
41 #include <linux/workqueue.h>
42 #include <linux/compiler.h>
43 #include <linux/cdev.h>
44 #include <linux/list.h>
45 #include <linux/mempool.h>
46 #include <linux/io.h>
47 #include <linux/spinlock_types.h>
48 #include <scsi/scsi_device.h>
49 #include <scsi/scsi_transport_fc.h>
50
51 #include "csio_hw_chip.h"
52 #include "csio_wr.h"
53 #include "csio_mb.h"
54 #include "csio_scsi.h"
55 #include "csio_defs.h"
56 #include "t4_regs.h"
57 #include "t4_msg.h"
58
59 /*
60 * An error value used by host. Should not clash with FW defined return values.
61 */
62 #define FW_HOSTERROR 255
63
64 #define CSIO_HW_NAME "Chelsio FCoE Adapter"
65 #define CSIO_MAX_PFN 8
66 #define CSIO_MAX_PPORTS 4
67
68 #define CSIO_MAX_LUN 0xFFFF
69 #define CSIO_MAX_QUEUE 2048
70 #define CSIO_MAX_CMD_PER_LUN 32
71 #define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
72 #define CSIO_MAX_SECTOR_SIZE 128
73
74 /* Interrupts */
75 #define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode
76 * (Forward intr iq + fw iq) */
77 #define CSIO_EXTRA_VECS 2 /* non-data + FW evt */
78 #define CSIO_MAX_SCSI_CPU 128
79 #define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
80 #define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
81
82 /* Queues */
83 enum {
84 CSIO_INTR_WRSIZE = 128,
85 CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
86 CSIO_FWEVT_WRSIZE = 128,
87 CSIO_FWEVT_IQLEN = 128,
88 CSIO_FWEVT_FLBUFS = 64,
89 CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
90 CSIO_HW_NIQ = 1,
91 CSIO_HW_NFLQ = 1,
92 CSIO_HW_NEQ = 1,
93 CSIO_HW_NINTXQ = 1,
94 };
95
96 struct csio_msix_entries {
97 unsigned short vector; /* Vector assigned by pci_enable_msix */
98 void *dev_id; /* Priv object associated w/ this msix*/
99 char desc[24]; /* Description of this vector */
100 };
101
102 struct csio_scsi_qset {
103 int iq_idx; /* Ingress index */
104 int eq_idx; /* Egress index */
105 uint32_t intr_idx; /* MSIX Vector index */
106 };
107
108 struct csio_scsi_cpu_info {
109 int16_t max_cpus;
110 };
111
112 extern int csio_dbg_level;
113 extern int csio_force_master;
114 extern unsigned int csio_port_mask;
115 extern int csio_msi;
116
117 #define CSIO_VENDOR_ID 0x1425
118 #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
119 #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
120
121 #define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
122 EDC1 | LE | TP | MA | PM_TX | PM_RX | \
123 ULP_RX | CPL_SWITCH | SGE | \
124 ULP_TX | SF)
125
126 /*
127 * Hard parameters used to initialize the card in the absence of a
128 * configuration file.
129 */
130 enum {
131 /* General */
132 CSIO_SGE_DBFIFO_INT_THRESH = 10,
133
134 CSIO_SGE_RX_DMA_OFFSET = 2,
135
136 CSIO_SGE_FLBUF_SIZE1 = 65536,
137 CSIO_SGE_FLBUF_SIZE2 = 1536,
138 CSIO_SGE_FLBUF_SIZE3 = 9024,
139 CSIO_SGE_FLBUF_SIZE4 = 9216,
140 CSIO_SGE_FLBUF_SIZE5 = 2048,
141 CSIO_SGE_FLBUF_SIZE6 = 128,
142 CSIO_SGE_FLBUF_SIZE7 = 8192,
143 CSIO_SGE_FLBUF_SIZE8 = 16384,
144
145 CSIO_SGE_TIMER_VAL_0 = 5,
146 CSIO_SGE_TIMER_VAL_1 = 10,
147 CSIO_SGE_TIMER_VAL_2 = 20,
148 CSIO_SGE_TIMER_VAL_3 = 50,
149 CSIO_SGE_TIMER_VAL_4 = 100,
150 CSIO_SGE_TIMER_VAL_5 = 200,
151
152 CSIO_SGE_INT_CNT_VAL_0 = 1,
153 CSIO_SGE_INT_CNT_VAL_1 = 4,
154 CSIO_SGE_INT_CNT_VAL_2 = 8,
155 CSIO_SGE_INT_CNT_VAL_3 = 16,
156
157 /* Storage specific - used by FW_PFVF_CMD */
158 CSIO_WX_CAPS = FW_CMD_CAP_PF, /* w/x all */
159 CSIO_R_CAPS = FW_CMD_CAP_PF, /* r all */
160 CSIO_NVI = 4,
161 CSIO_NIQ_FLINT = 34,
162 CSIO_NETH_CTRL = 32,
163 CSIO_NEQ = 66,
164 CSIO_NEXACTF = 32,
165 CSIO_CMASK = FW_PFVF_CMD_CMASK_MASK,
166 CSIO_PMASK = FW_PFVF_CMD_PMASK_MASK,
167 };
168
169 /* Slowpath events */
170 enum csio_evt {
171 CSIO_EVT_FW = 0, /* FW event */
172 CSIO_EVT_MBX, /* MBX event */
173 CSIO_EVT_SCN, /* State change notification */
174 CSIO_EVT_DEV_LOSS, /* Device loss event */
175 CSIO_EVT_MAX, /* Max supported event */
176 };
177
178 #define CSIO_EVT_MSG_SIZE 512
179 #define CSIO_EVTQ_SIZE 512
180
181 /* Event msg */
182 struct csio_evt_msg {
183 struct list_head list; /* evt queue*/
184 enum csio_evt type;
185 uint8_t data[CSIO_EVT_MSG_SIZE];
186 };
187
188 enum {
189 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
190 SERNUM_LEN = 16, /* Serial # length */
191 EC_LEN = 16, /* E/C length */
192 ID_LEN = 16, /* ID length */
193 TRACE_LEN = 112, /* length of trace data and mask */
194 };
195
196 enum {
197 SF_PAGE_SIZE = 256, /* serial flash page size */
198 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
199 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
200 };
201
202 /* serial flash and firmware constants */
203 enum {
204 SF_ATTEMPTS = 10, /* max retries for SF operations */
205
206 /* flash command opcodes */
207 SF_PROG_PAGE = 2, /* program page */
208 SF_WR_DISABLE = 4, /* disable writes */
209 SF_RD_STATUS = 5, /* read status register */
210 SF_WR_ENABLE = 6, /* enable writes */
211 SF_RD_DATA_FAST = 0xb, /* read flash */
212 SF_RD_ID = 0x9f, /* read ID */
213 SF_ERASE_SECTOR = 0xd8, /* erase sector */
214
215 FW_START_SEC = 8, /* first flash sector for FW */
216 FW_END_SEC = 15, /* last flash sector for FW */
217 FW_IMG_START = FW_START_SEC * SF_SEC_SIZE,
218 FW_MAX_SIZE = (FW_END_SEC - FW_START_SEC + 1) * SF_SEC_SIZE,
219
220 FLASH_CFG_MAX_SIZE = 0x10000 , /* max size of the flash config file*/
221 FLASH_CFG_OFFSET = 0x1f0000,
222 FLASH_CFG_START_SEC = FLASH_CFG_OFFSET / SF_SEC_SIZE,
223 };
224
225 /*
226 * Flash layout.
227 */
228 #define FLASH_START(start) ((start) * SF_SEC_SIZE)
229 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
230
231 enum {
232 /*
233 * Location of firmware image in FLASH.
234 */
235 FLASH_FW_START_SEC = 8,
236 FLASH_FW_NSECS = 8,
237 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
238 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
239
240 /* Location of Firmware Configuration File in FLASH. */
241 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
242 };
243
244 #undef FLASH_START
245 #undef FLASH_MAX_SIZE
246
247 /* Management module */
248 enum {
249 CSIO_MGMT_EQ_WRSIZE = 512,
250 CSIO_MGMT_IQ_WRSIZE = 128,
251 CSIO_MGMT_EQLEN = 64,
252 CSIO_MGMT_IQLEN = 64,
253 };
254
255 #define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
256 #define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
257
258 /* mgmt module stats */
259 struct csio_mgmtm_stats {
260 uint32_t n_abort_req; /* Total abort request */
261 uint32_t n_abort_rsp; /* Total abort response */
262 uint32_t n_close_req; /* Total close request */
263 uint32_t n_close_rsp; /* Total close response */
264 uint32_t n_err; /* Total Errors */
265 uint32_t n_drop; /* Total request dropped */
266 uint32_t n_active; /* Count of active_q */
267 uint32_t n_cbfn; /* Count of cbfn_q */
268 };
269
270 /* MGMT module */
271 struct csio_mgmtm {
272 struct csio_hw *hw; /* Pointer to HW moduel */
273 int eq_idx; /* Egress queue index */
274 int iq_idx; /* Ingress queue index */
275 int msi_vec; /* MSI vector */
276 struct list_head active_q; /* Outstanding ELS/CT */
277 struct list_head abort_q; /* Outstanding abort req */
278 struct list_head cbfn_q; /* Completion queue */
279 struct list_head mgmt_req_freelist; /* Free poll of reqs */
280 /* ELSCT request freelist*/
281 struct timer_list mgmt_timer; /* MGMT timer */
282 struct csio_mgmtm_stats stats; /* ELS/CT stats */
283 };
284
285 struct csio_adap_desc {
286 char model_no[16];
287 char description[32];
288 };
289
290 struct pci_params {
291 uint16_t vendor_id;
292 uint16_t device_id;
293 int vpd_cap_addr;
294 uint16_t speed;
295 uint8_t width;
296 };
297
298 /* User configurable hw parameters */
299 struct csio_hw_params {
300 uint32_t sf_size; /* serial flash
301 * size in bytes
302 */
303 uint32_t sf_nsec; /* # of flash sectors */
304 struct pci_params pci;
305 uint32_t log_level; /* Module-level for
306 * debug log.
307 */
308 };
309
310 struct csio_vpd {
311 uint32_t cclk;
312 uint8_t ec[EC_LEN + 1];
313 uint8_t sn[SERNUM_LEN + 1];
314 uint8_t id[ID_LEN + 1];
315 };
316
317 struct csio_pport {
318 uint16_t pcap;
319 uint8_t portid;
320 uint8_t link_status;
321 uint16_t link_speed;
322 uint8_t mac[6];
323 uint8_t mod_type;
324 uint8_t rsvd1;
325 uint8_t rsvd2;
326 uint8_t rsvd3;
327 };
328
329 /* fcoe resource information */
330 struct csio_fcoe_res_info {
331 uint16_t e_d_tov;
332 uint16_t r_a_tov_seq;
333 uint16_t r_a_tov_els;
334 uint16_t r_r_tov;
335 uint32_t max_xchgs;
336 uint32_t max_ssns;
337 uint32_t used_xchgs;
338 uint32_t used_ssns;
339 uint32_t max_fcfs;
340 uint32_t max_vnps;
341 uint32_t used_fcfs;
342 uint32_t used_vnps;
343 };
344
345 /* HW State machine Events */
346 enum csio_hw_ev {
347 CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */
348 CSIO_HWE_INIT, /* Config done, start Init */
349 CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */
350 CSIO_HWE_FATAL, /* Fatal error during initialization */
351 CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */
352 CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */
353 CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */
354 CSIO_HWE_QUIESCED, /* HBA quiesced */
355 CSIO_HWE_HBA_RESET, /* HBA reset requested */
356 CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */
357 CSIO_HWE_FW_DLOAD, /* FW download requested */
358 CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */
359 CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */
360 CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */
361 CSIO_HWE_MAX, /* Max HW event */
362 };
363
364 /* hw stats */
365 struct csio_hw_stats {
366 uint32_t n_evt_activeq; /* Number of event in active Q */
367 uint32_t n_evt_freeq; /* Number of event in free Q */
368 uint32_t n_evt_drop; /* Number of event droped */
369 uint32_t n_evt_unexp; /* Number of unexpected events */
370 uint32_t n_pcich_offline;/* Number of pci channel offline */
371 uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */
372 uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/
373 uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/
374 uint32_t n_cpl_unexp; /* Number of unexpected cpl */
375 uint32_t n_mbint_unexp; /* Number of unexpected mbox */
376 /* interrupt */
377 uint32_t n_plint_unexp; /* Number of unexpected PL */
378 /* interrupt */
379 uint32_t n_plint_cnt; /* Number of PL interrupt */
380 uint32_t n_int_stray; /* Number of stray interrupt */
381 uint32_t n_err; /* Number of hw errors */
382 uint32_t n_err_fatal; /* Number of fatal errors */
383 uint32_t n_err_nomem; /* Number of memory alloc failure */
384 uint32_t n_err_io; /* Number of IO failure */
385 enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */
386 uint64_t n_reset_start; /* Start time after the reset */
387 uint32_t rsvd1;
388 };
389
390 /* Defines for hw->flags */
391 #define CSIO_HWF_MASTER 0x00000001 /* This is the Master
392 * function for the
393 * card.
394 */
395 #define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt
396 * enable bit set?
397 */
398 #define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */
399 #define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been
400 * allocated memory.
401 */
402 #define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been
403 * allocated in FW.
404 */
405 #define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */
406 #define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device
407 * id cached */
408 #define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing
409 * FW events
410 */
411 #define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config
412 * params
413 */
414 #define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts
415 * enabled?
416 */
417
418 #define csio_is_hw_intr_enabled(__hw) \
419 ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
420 #define csio_is_host_intr_enabled(__hw) \
421 ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
422 #define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
423 #define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
424 #define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
425 #define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
426 #define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
427
428 /* Defines for intr_mode */
429 enum csio_intr_mode {
430 CSIO_IM_NONE = 0,
431 CSIO_IM_INTX = 1,
432 CSIO_IM_MSI = 2,
433 CSIO_IM_MSIX = 3,
434 };
435
436 /* Master HW structure: One per function */
437 struct csio_hw {
438 struct csio_sm sm; /* State machine: should
439 * be the 1st member.
440 */
441 spinlock_t lock; /* Lock for hw */
442
443 struct csio_scsim scsim; /* SCSI module*/
444 struct csio_wrm wrm; /* Work request module*/
445 struct pci_dev *pdev; /* PCI device */
446
447 void __iomem *regstart; /* Virtual address of
448 * register map
449 */
450 /* SCSI queue sets */
451 uint32_t num_sqsets; /* Number of SCSI
452 * queue sets */
453 uint32_t num_scsi_msix_cpus; /* Number of CPUs that
454 * will be used
455 * for ingress
456 * processing.
457 */
458
459 struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
460 struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
461
462 uint32_t evtflag; /* Event flag */
463 uint32_t flags; /* HW flags */
464
465 struct csio_mgmtm mgmtm; /* management module */
466 struct csio_mbm mbm; /* Mailbox module */
467
468 /* Lnodes */
469 uint32_t num_lns; /* Number of lnodes */
470 struct csio_lnode *rln; /* Root lnode */
471 struct list_head sln_head; /* Sibling node list
472 * list
473 */
474 int intr_iq_idx; /* Forward interrupt
475 * queue.
476 */
477 int fwevt_iq_idx; /* FW evt queue */
478 struct work_struct evtq_work; /* Worker thread for
479 * HW events.
480 */
481 struct list_head evt_free_q; /* freelist of evt
482 * elements
483 */
484 struct list_head evt_active_q; /* active evt queue*/
485
486 /* board related info */
487 char name[32];
488 char hw_ver[16];
489 char model_desc[32];
490 char drv_version[32];
491 char fwrev_str[32];
492 uint32_t optrom_ver;
493 uint32_t fwrev;
494 uint32_t tp_vers;
495 char chip_ver;
496 uint16_t chip_id; /* Tells T4/T5 chip */
497 uint32_t cfg_finiver;
498 uint32_t cfg_finicsum;
499 uint32_t cfg_cfcsum;
500 uint8_t cfg_csum_status;
501 uint8_t cfg_store;
502 enum csio_dev_state fw_state;
503 struct csio_vpd vpd;
504
505 uint8_t pfn; /* Physical Function
506 * number
507 */
508 uint32_t port_vec; /* Port vector */
509 uint8_t num_pports; /* Number of physical
510 * ports.
511 */
512 uint8_t rst_retries; /* Reset retries */
513 uint8_t cur_evt; /* current s/m evt */
514 uint8_t prev_evt; /* Previous s/m evt */
515 uint32_t dev_num; /* device number */
516 struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */
517 struct csio_hw_params params; /* Hw parameters */
518
519 struct pci_pool *scsi_pci_pool; /* PCI pool for SCSI */
520 mempool_t *mb_mempool; /* Mailbox memory pool*/
521 mempool_t *rnode_mempool; /* rnode memory pool */
522
523 /* Interrupt */
524 enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */
525 uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt
526 * index
527 */
528 uint32_t nondata_intr_idx; /* nondata MSIX/intr
529 * idx
530 */
531
532 uint8_t cfg_neq; /* FW configured no of
533 * egress queues
534 */
535 uint8_t cfg_niq; /* FW configured no of
536 * iq queues.
537 */
538
539 struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
540 struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific
541 * Operations
542 */
543
544 /* MSIX vectors */
545 struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
546
547 struct dentry *debugfs_root; /* Debug FS */
548 struct csio_hw_stats stats; /* Hw statistics */
549 };
550
551 /* Register access macros */
552 #define csio_reg(_b, _r) ((_b) + (_r))
553
554 #define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
555 #define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
556 #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
557 #define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
558
559 #define csio_wr_reg8(_h, _v, _r) writeb((_v), \
560 csio_reg((_h)->regstart, (_r)))
561 #define csio_wr_reg16(_h, _v, _r) writew((_v), \
562 csio_reg((_h)->regstart, (_r)))
563 #define csio_wr_reg32(_h, _v, _r) writel((_v), \
564 csio_reg((_h)->regstart, (_r)))
565 #define csio_wr_reg64(_h, _v, _r) writeq((_v), \
566 csio_reg((_h)->regstart, (_r)))
567
568 void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
569
570 /* Core clocks <==> uSecs */
571 static inline uint32_t
572 csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
573 {
574 /* add Core Clock / 2 to round ticks to nearest uS */
575 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
576 }
577
578 static inline uint32_t
579 csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
580 {
581 return (us * hw->vpd.cclk) / 1000;
582 }
583
584 /* Easy access macros */
585 #define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
586 #define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
587 #define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
588 #define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
589
590 #define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
591 #define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
592 #define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
593
594 #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
595 #define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
596 #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
597 #define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
598
599 /* Printing/logging */
600 #define CSIO_DEVID(__dev) ((__dev)->dev_num)
601 #define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
602 #define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
603
604 #define csio_info(__hw, __fmt, ...) \
605 dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
606
607 #define csio_fatal(__hw, __fmt, ...) \
608 dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
609
610 #define csio_err(__hw, __fmt, ...) \
611 dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
612
613 #define csio_warn(__hw, __fmt, ...) \
614 dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
615
616 #ifdef __CSIO_DEBUG__
617 #define csio_dbg(__hw, __fmt, ...) \
618 csio_info((__hw), __fmt, ##__VA_ARGS__);
619 #else
620 #define csio_dbg(__hw, __fmt, ...)
621 #endif
622
623 int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
624 int, int, uint32_t *);
625 void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
626 unsigned int, unsigned int);
627 int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
628 void csio_hw_intr_disable(struct csio_hw *);
629 int csio_hw_slow_intr_handler(struct csio_hw *);
630 int csio_handle_intr_status(struct csio_hw *, unsigned int,
631 const struct intr_info *);
632
633 int csio_hw_start(struct csio_hw *);
634 int csio_hw_stop(struct csio_hw *);
635 int csio_hw_reset(struct csio_hw *);
636 int csio_is_hw_ready(struct csio_hw *);
637 int csio_is_hw_removing(struct csio_hw *);
638
639 int csio_fwevtq_handler(struct csio_hw *);
640 void csio_evtq_worker(struct work_struct *);
641 int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
642 void csio_evtq_flush(struct csio_hw *hw);
643
644 int csio_request_irqs(struct csio_hw *);
645 void csio_intr_enable(struct csio_hw *);
646 void csio_intr_disable(struct csio_hw *, bool);
647 void csio_hw_fatal_err(struct csio_hw *);
648
649 struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
650 int csio_config_queues(struct csio_hw *);
651
652 int csio_hw_init(struct csio_hw *);
653 void csio_hw_exit(struct csio_hw *);
654 #endif /* ifndef __CSIO_HW_H__ */
Linux with added FPC-III support