1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
5 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
7 * Documentation: ARM DDI 0173B
9 #include <linux/module.h>
10 #include <linux/delay.h>
11 #include <linux/init.h>
12 #include <linux/ioport.h>
13 #include <linux/device.h>
14 #include <linux/spinlock.h>
15 #include <linux/interrupt.h>
16 #include <linux/err.h>
17 #include <linux/amba/bus.h>
20 #include <sound/core.h>
21 #include <sound/initval.h>
22 #include <sound/ac97_codec.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
28 #define DRIVER_NAME "aaci-pl041"
30 #define FRAME_PERIOD_US 21
33 * PM support is not complete. Turn it off.
37 static void aaci_ac97_select_codec(struct aaci
*aaci
, struct snd_ac97
*ac97
)
39 u32 v
, maincr
= aaci
->maincr
| MAINCR_SCRA(ac97
->num
);
42 * Ensure that the slot 1/2 RX registers are empty.
44 v
= readl(aaci
->base
+ AACI_SLFR
);
46 readl(aaci
->base
+ AACI_SL2RX
);
48 readl(aaci
->base
+ AACI_SL1RX
);
50 if (maincr
!= readl(aaci
->base
+ AACI_MAINCR
)) {
51 writel(maincr
, aaci
->base
+ AACI_MAINCR
);
52 readl(aaci
->base
+ AACI_MAINCR
);
59 * The recommended use of programming the external codec through slot 1
60 * and slot 2 data is to use the channels during setup routines and the
61 * slot register at any other time. The data written into slot 1, slot 2
62 * and slot 12 registers is transmitted only when their corresponding
63 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
66 static void aaci_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
69 struct aaci
*aaci
= ac97
->private_data
;
76 mutex_lock(&aaci
->ac97_sem
);
78 aaci_ac97_select_codec(aaci
, ac97
);
81 * P54: You must ensure that AACI_SL2TX is always written
82 * to, if required, before data is written to AACI_SL1TX.
84 writel(val
<< 4, aaci
->base
+ AACI_SL2TX
);
85 writel(reg
<< 12, aaci
->base
+ AACI_SL1TX
);
87 /* Initially, wait one frame period */
88 udelay(FRAME_PERIOD_US
);
90 /* And then wait an additional eight frame periods for it to be sent */
91 timeout
= FRAME_PERIOD_US
* 8;
94 v
= readl(aaci
->base
+ AACI_SLFR
);
95 } while ((v
& (SLFR_1TXB
|SLFR_2TXB
)) && --timeout
);
97 if (v
& (SLFR_1TXB
|SLFR_2TXB
))
98 dev_err(&aaci
->dev
->dev
,
99 "timeout waiting for write to complete\n");
101 mutex_unlock(&aaci
->ac97_sem
);
105 * Read an AC'97 register.
107 static unsigned short aaci_ac97_read(struct snd_ac97
*ac97
, unsigned short reg
)
109 struct aaci
*aaci
= ac97
->private_data
;
110 int timeout
, retries
= 10;
116 mutex_lock(&aaci
->ac97_sem
);
118 aaci_ac97_select_codec(aaci
, ac97
);
121 * Write the register address to slot 1.
123 writel((reg
<< 12) | (1 << 19), aaci
->base
+ AACI_SL1TX
);
125 /* Initially, wait one frame period */
126 udelay(FRAME_PERIOD_US
);
128 /* And then wait an additional eight frame periods for it to be sent */
129 timeout
= FRAME_PERIOD_US
* 8;
132 v
= readl(aaci
->base
+ AACI_SLFR
);
133 } while ((v
& SLFR_1TXB
) && --timeout
);
136 dev_err(&aaci
->dev
->dev
, "timeout on slot 1 TX busy\n");
141 /* Now wait for the response frame */
142 udelay(FRAME_PERIOD_US
);
144 /* And then wait an additional eight frame periods for data */
145 timeout
= FRAME_PERIOD_US
* 8;
149 v
= readl(aaci
->base
+ AACI_SLFR
) & (SLFR_1RXV
|SLFR_2RXV
);
150 } while ((v
!= (SLFR_1RXV
|SLFR_2RXV
)) && --timeout
);
152 if (v
!= (SLFR_1RXV
|SLFR_2RXV
)) {
153 dev_err(&aaci
->dev
->dev
, "timeout on RX valid\n");
159 v
= readl(aaci
->base
+ AACI_SL1RX
) >> 12;
161 v
= readl(aaci
->base
+ AACI_SL2RX
) >> 4;
163 } else if (--retries
) {
164 dev_warn(&aaci
->dev
->dev
,
165 "ac97 read back fail. retry\n");
168 dev_warn(&aaci
->dev
->dev
,
169 "wrong ac97 register read back (%x != %x)\n",
175 mutex_unlock(&aaci
->ac97_sem
);
180 aaci_chan_wait_ready(struct aaci_runtime
*aacirun
, unsigned long mask
)
187 val
= readl(aacirun
->base
+ AACI_SR
);
188 } while (val
& mask
&& timeout
--);
196 static void aaci_fifo_irq(struct aaci
*aaci
, int channel
, u32 mask
)
198 if (mask
& ISR_ORINTR
) {
199 dev_warn(&aaci
->dev
->dev
, "RX overrun on chan %d\n", channel
);
200 writel(ICLR_RXOEC1
<< channel
, aaci
->base
+ AACI_INTCLR
);
203 if (mask
& ISR_RXTOINTR
) {
204 dev_warn(&aaci
->dev
->dev
, "RX timeout on chan %d\n", channel
);
205 writel(ICLR_RXTOFEC1
<< channel
, aaci
->base
+ AACI_INTCLR
);
208 if (mask
& ISR_RXINTR
) {
209 struct aaci_runtime
*aacirun
= &aaci
->capture
;
210 bool period_elapsed
= false;
213 if (!aacirun
->substream
|| !aacirun
->start
) {
214 dev_warn(&aaci
->dev
->dev
, "RX interrupt???\n");
215 writel(0, aacirun
->base
+ AACI_IE
);
219 spin_lock(&aacirun
->lock
);
223 unsigned int len
= aacirun
->fifo_bytes
;
226 if (aacirun
->bytes
<= 0) {
227 aacirun
->bytes
+= aacirun
->period
;
228 period_elapsed
= true;
230 if (!(aacirun
->cr
& CR_EN
))
233 val
= readl(aacirun
->base
+ AACI_SR
);
234 if (!(val
& SR_RXHF
))
236 if (!(val
& SR_RXFF
))
239 aacirun
->bytes
-= len
;
241 /* reading 16 bytes at a time */
242 for( ; len
> 0; len
-= 16) {
244 "ldmia %1, {r0, r1, r2, r3}\n\t"
245 "stmia %0!, {r0, r1, r2, r3}"
247 : "r" (aacirun
->fifo
)
248 : "r0", "r1", "r2", "r3", "cc");
250 if (ptr
>= aacirun
->end
)
251 ptr
= aacirun
->start
;
257 spin_unlock(&aacirun
->lock
);
260 snd_pcm_period_elapsed(aacirun
->substream
);
263 if (mask
& ISR_URINTR
) {
264 dev_dbg(&aaci
->dev
->dev
, "TX underrun on chan %d\n", channel
);
265 writel(ICLR_TXUEC1
<< channel
, aaci
->base
+ AACI_INTCLR
);
268 if (mask
& ISR_TXINTR
) {
269 struct aaci_runtime
*aacirun
= &aaci
->playback
;
270 bool period_elapsed
= false;
273 if (!aacirun
->substream
|| !aacirun
->start
) {
274 dev_warn(&aaci
->dev
->dev
, "TX interrupt???\n");
275 writel(0, aacirun
->base
+ AACI_IE
);
279 spin_lock(&aacirun
->lock
);
283 unsigned int len
= aacirun
->fifo_bytes
;
286 if (aacirun
->bytes
<= 0) {
287 aacirun
->bytes
+= aacirun
->period
;
288 period_elapsed
= true;
290 if (!(aacirun
->cr
& CR_EN
))
293 val
= readl(aacirun
->base
+ AACI_SR
);
294 if (!(val
& SR_TXHE
))
296 if (!(val
& SR_TXFE
))
299 aacirun
->bytes
-= len
;
301 /* writing 16 bytes at a time */
302 for ( ; len
> 0; len
-= 16) {
304 "ldmia %0!, {r0, r1, r2, r3}\n\t"
305 "stmia %1, {r0, r1, r2, r3}"
307 : "r" (aacirun
->fifo
)
308 : "r0", "r1", "r2", "r3", "cc");
310 if (ptr
>= aacirun
->end
)
311 ptr
= aacirun
->start
;
317 spin_unlock(&aacirun
->lock
);
320 snd_pcm_period_elapsed(aacirun
->substream
);
324 static irqreturn_t
aaci_irq(int irq
, void *devid
)
326 struct aaci
*aaci
= devid
;
330 mask
= readl(aaci
->base
+ AACI_ALLINTS
);
333 for (i
= 0; i
< 4; i
++, m
>>= 7) {
335 aaci_fifo_irq(aaci
, i
, m
);
340 return mask
? IRQ_HANDLED
: IRQ_NONE
;
348 static const struct snd_pcm_hardware aaci_hw_info
= {
349 .info
= SNDRV_PCM_INFO_MMAP
|
350 SNDRV_PCM_INFO_MMAP_VALID
|
351 SNDRV_PCM_INFO_INTERLEAVED
|
352 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
353 SNDRV_PCM_INFO_RESUME
,
356 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
357 * words. It also doesn't support 12-bit at all.
359 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
361 /* rates are setup from the AC'97 codec */
364 .buffer_bytes_max
= 64 * 1024,
365 .period_bytes_min
= 256,
366 .period_bytes_max
= PAGE_SIZE
,
368 .periods_max
= PAGE_SIZE
/ 16,
372 * We can support two and four channel audio. Unfortunately
373 * six channel audio requires a non-standard channel ordering:
375 * 4 -> FL(3), FR(4), SL(7), SR(8)
376 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
377 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
378 * This requires an ALSA configuration file to correct.
380 static int aaci_rule_channels(struct snd_pcm_hw_params
*p
,
381 struct snd_pcm_hw_rule
*rule
)
383 static unsigned int channel_list
[] = { 2, 4, 6 };
384 struct aaci
*aaci
= rule
->private;
385 unsigned int mask
= 1 << 0, slots
;
387 /* pcms[0] is the our 5.1 PCM instance. */
388 slots
= aaci
->ac97_bus
->pcms
[0].r
[0].slots
;
389 if (slots
& (1 << AC97_SLOT_PCM_SLEFT
)) {
391 if (slots
& (1 << AC97_SLOT_LFE
))
395 return snd_interval_list(hw_param_interval(p
, rule
->var
),
396 ARRAY_SIZE(channel_list
), channel_list
, mask
);
399 static int aaci_pcm_open(struct snd_pcm_substream
*substream
)
401 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
402 struct aaci
*aaci
= substream
->private_data
;
403 struct aaci_runtime
*aacirun
;
406 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
407 aacirun
= &aaci
->playback
;
409 aacirun
= &aaci
->capture
;
412 aacirun
->substream
= substream
;
413 runtime
->private_data
= aacirun
;
414 runtime
->hw
= aaci_hw_info
;
415 runtime
->hw
.rates
= aacirun
->pcm
->rates
;
416 snd_pcm_limit_hw_rates(runtime
);
418 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
419 runtime
->hw
.channels_max
= 6;
421 /* Add rule describing channel dependency. */
422 ret
= snd_pcm_hw_rule_add(substream
->runtime
, 0,
423 SNDRV_PCM_HW_PARAM_CHANNELS
,
424 aaci_rule_channels
, aaci
,
425 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
429 if (aacirun
->pcm
->r
[1].slots
)
430 snd_ac97_pcm_double_rate_rules(runtime
);
434 * ALSA wants the byte-size of the FIFOs. As we only support
435 * 16-bit samples, this is twice the FIFO depth irrespective
436 * of whether it's in compact mode or not.
438 runtime
->hw
.fifo_size
= aaci
->fifo_depth
* 2;
440 mutex_lock(&aaci
->irq_lock
);
441 if (!aaci
->users
++) {
442 ret
= request_irq(aaci
->dev
->irq
[0], aaci_irq
,
443 IRQF_SHARED
, DRIVER_NAME
, aaci
);
447 mutex_unlock(&aaci
->irq_lock
);
456 static int aaci_pcm_close(struct snd_pcm_substream
*substream
)
458 struct aaci
*aaci
= substream
->private_data
;
459 struct aaci_runtime
*aacirun
= substream
->runtime
->private_data
;
461 WARN_ON(aacirun
->cr
& CR_EN
);
463 aacirun
->substream
= NULL
;
465 mutex_lock(&aaci
->irq_lock
);
467 free_irq(aaci
->dev
->irq
[0], aaci
);
468 mutex_unlock(&aaci
->irq_lock
);
473 static int aaci_pcm_hw_free(struct snd_pcm_substream
*substream
)
475 struct aaci_runtime
*aacirun
= substream
->runtime
->private_data
;
478 * This must not be called with the device enabled.
480 WARN_ON(aacirun
->cr
& CR_EN
);
482 if (aacirun
->pcm_open
)
483 snd_ac97_pcm_close(aacirun
->pcm
);
484 aacirun
->pcm_open
= 0;
487 * Clear out the DMA and any allocated buffers.
489 snd_pcm_lib_free_pages(substream
);
494 /* Channel to slot mask */
495 static const u32 channels_to_slotmask
[] = {
496 [2] = CR_SL3
| CR_SL4
,
497 [4] = CR_SL3
| CR_SL4
| CR_SL7
| CR_SL8
,
498 [6] = CR_SL3
| CR_SL4
| CR_SL7
| CR_SL8
| CR_SL6
| CR_SL9
,
501 static int aaci_pcm_hw_params(struct snd_pcm_substream
*substream
,
502 struct snd_pcm_hw_params
*params
)
504 struct aaci_runtime
*aacirun
= substream
->runtime
->private_data
;
505 unsigned int channels
= params_channels(params
);
506 unsigned int rate
= params_rate(params
);
507 int dbl
= rate
> 48000;
510 aaci_pcm_hw_free(substream
);
511 if (aacirun
->pcm_open
) {
512 snd_ac97_pcm_close(aacirun
->pcm
);
513 aacirun
->pcm_open
= 0;
516 /* channels is already limited to 2, 4, or 6 by aaci_rule_channels */
517 if (dbl
&& channels
!= 2)
520 err
= snd_pcm_lib_malloc_pages(substream
,
521 params_buffer_bytes(params
));
523 struct aaci
*aaci
= substream
->private_data
;
525 err
= snd_ac97_pcm_open(aacirun
->pcm
, rate
, channels
,
526 aacirun
->pcm
->r
[dbl
].slots
);
528 aacirun
->pcm_open
= err
== 0;
529 aacirun
->cr
= CR_FEN
| CR_COMPACT
| CR_SZ16
;
530 aacirun
->cr
|= channels_to_slotmask
[channels
+ dbl
* 2];
533 * fifo_bytes is the number of bytes we transfer to/from
534 * the FIFO, including padding. So that's x4. As we're
535 * in compact mode, the FIFO is half the size.
537 aacirun
->fifo_bytes
= aaci
->fifo_depth
* 4 / 2;
543 static int aaci_pcm_prepare(struct snd_pcm_substream
*substream
)
545 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
546 struct aaci_runtime
*aacirun
= runtime
->private_data
;
548 aacirun
->period
= snd_pcm_lib_period_bytes(substream
);
549 aacirun
->start
= runtime
->dma_area
;
550 aacirun
->end
= aacirun
->start
+ snd_pcm_lib_buffer_bytes(substream
);
551 aacirun
->ptr
= aacirun
->start
;
552 aacirun
->bytes
= aacirun
->period
;
557 static snd_pcm_uframes_t
aaci_pcm_pointer(struct snd_pcm_substream
*substream
)
559 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
560 struct aaci_runtime
*aacirun
= runtime
->private_data
;
561 ssize_t bytes
= aacirun
->ptr
- aacirun
->start
;
563 return bytes_to_frames(runtime
, bytes
);
568 * Playback specific ALSA stuff
570 static void aaci_pcm_playback_stop(struct aaci_runtime
*aacirun
)
574 ie
= readl(aacirun
->base
+ AACI_IE
);
575 ie
&= ~(IE_URIE
|IE_TXIE
);
576 writel(ie
, aacirun
->base
+ AACI_IE
);
577 aacirun
->cr
&= ~CR_EN
;
578 aaci_chan_wait_ready(aacirun
, SR_TXB
);
579 writel(aacirun
->cr
, aacirun
->base
+ AACI_TXCR
);
582 static void aaci_pcm_playback_start(struct aaci_runtime
*aacirun
)
586 aaci_chan_wait_ready(aacirun
, SR_TXB
);
587 aacirun
->cr
|= CR_EN
;
589 ie
= readl(aacirun
->base
+ AACI_IE
);
590 ie
|= IE_URIE
| IE_TXIE
;
591 writel(ie
, aacirun
->base
+ AACI_IE
);
592 writel(aacirun
->cr
, aacirun
->base
+ AACI_TXCR
);
595 static int aaci_pcm_playback_trigger(struct snd_pcm_substream
*substream
, int cmd
)
597 struct aaci_runtime
*aacirun
= substream
->runtime
->private_data
;
601 spin_lock_irqsave(&aacirun
->lock
, flags
);
604 case SNDRV_PCM_TRIGGER_START
:
605 aaci_pcm_playback_start(aacirun
);
608 case SNDRV_PCM_TRIGGER_RESUME
:
609 aaci_pcm_playback_start(aacirun
);
612 case SNDRV_PCM_TRIGGER_STOP
:
613 aaci_pcm_playback_stop(aacirun
);
616 case SNDRV_PCM_TRIGGER_SUSPEND
:
617 aaci_pcm_playback_stop(aacirun
);
620 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
623 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
630 spin_unlock_irqrestore(&aacirun
->lock
, flags
);
635 static const struct snd_pcm_ops aaci_playback_ops
= {
636 .open
= aaci_pcm_open
,
637 .close
= aaci_pcm_close
,
638 .ioctl
= snd_pcm_lib_ioctl
,
639 .hw_params
= aaci_pcm_hw_params
,
640 .hw_free
= aaci_pcm_hw_free
,
641 .prepare
= aaci_pcm_prepare
,
642 .trigger
= aaci_pcm_playback_trigger
,
643 .pointer
= aaci_pcm_pointer
,
646 static void aaci_pcm_capture_stop(struct aaci_runtime
*aacirun
)
650 aaci_chan_wait_ready(aacirun
, SR_RXB
);
652 ie
= readl(aacirun
->base
+ AACI_IE
);
653 ie
&= ~(IE_ORIE
| IE_RXIE
);
654 writel(ie
, aacirun
->base
+AACI_IE
);
656 aacirun
->cr
&= ~CR_EN
;
658 writel(aacirun
->cr
, aacirun
->base
+ AACI_RXCR
);
661 static void aaci_pcm_capture_start(struct aaci_runtime
*aacirun
)
665 aaci_chan_wait_ready(aacirun
, SR_RXB
);
668 /* RX Timeout value: bits 28:17 in RXCR */
669 aacirun
->cr
|= 0xf << 17;
672 aacirun
->cr
|= CR_EN
;
673 writel(aacirun
->cr
, aacirun
->base
+ AACI_RXCR
);
675 ie
= readl(aacirun
->base
+ AACI_IE
);
676 ie
|= IE_ORIE
|IE_RXIE
; // overrun and rx interrupt -- half full
677 writel(ie
, aacirun
->base
+ AACI_IE
);
680 static int aaci_pcm_capture_trigger(struct snd_pcm_substream
*substream
, int cmd
)
682 struct aaci_runtime
*aacirun
= substream
->runtime
->private_data
;
686 spin_lock_irqsave(&aacirun
->lock
, flags
);
689 case SNDRV_PCM_TRIGGER_START
:
690 aaci_pcm_capture_start(aacirun
);
693 case SNDRV_PCM_TRIGGER_RESUME
:
694 aaci_pcm_capture_start(aacirun
);
697 case SNDRV_PCM_TRIGGER_STOP
:
698 aaci_pcm_capture_stop(aacirun
);
701 case SNDRV_PCM_TRIGGER_SUSPEND
:
702 aaci_pcm_capture_stop(aacirun
);
705 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
708 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
715 spin_unlock_irqrestore(&aacirun
->lock
, flags
);
720 static int aaci_pcm_capture_prepare(struct snd_pcm_substream
*substream
)
722 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
723 struct aaci
*aaci
= substream
->private_data
;
725 aaci_pcm_prepare(substream
);
727 /* allow changing of sample rate */
728 aaci_ac97_write(aaci
->ac97
, AC97_EXTENDED_STATUS
, 0x0001); /* VRA */
729 aaci_ac97_write(aaci
->ac97
, AC97_PCM_LR_ADC_RATE
, runtime
->rate
);
730 aaci_ac97_write(aaci
->ac97
, AC97_PCM_MIC_ADC_RATE
, runtime
->rate
);
732 /* Record select: Mic: 0, Aux: 3, Line: 4 */
733 aaci_ac97_write(aaci
->ac97
, AC97_REC_SEL
, 0x0404);
738 static const struct snd_pcm_ops aaci_capture_ops
= {
739 .open
= aaci_pcm_open
,
740 .close
= aaci_pcm_close
,
741 .ioctl
= snd_pcm_lib_ioctl
,
742 .hw_params
= aaci_pcm_hw_params
,
743 .hw_free
= aaci_pcm_hw_free
,
744 .prepare
= aaci_pcm_capture_prepare
,
745 .trigger
= aaci_pcm_capture_trigger
,
746 .pointer
= aaci_pcm_pointer
,
753 static int aaci_do_suspend(struct snd_card
*card
)
755 struct aaci
*aaci
= card
->private_data
;
756 snd_power_change_state(card
, SNDRV_CTL_POWER_D3cold
);
760 static int aaci_do_resume(struct snd_card
*card
)
762 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
766 static int aaci_suspend(struct device
*dev
)
768 struct snd_card
*card
= dev_get_drvdata(dev
);
769 return card
? aaci_do_suspend(card
) : 0;
772 static int aaci_resume(struct device
*dev
)
774 struct snd_card
*card
= dev_get_drvdata(dev
);
775 return card
? aaci_do_resume(card
) : 0;
778 static SIMPLE_DEV_PM_OPS(aaci_dev_pm_ops
, aaci_suspend
, aaci_resume
);
779 #define AACI_DEV_PM_OPS (&aaci_dev_pm_ops)
781 #define AACI_DEV_PM_OPS NULL
785 static const struct ac97_pcm ac97_defs
[] = {
786 [0] = { /* Front PCM */
790 .slots
= (1 << AC97_SLOT_PCM_LEFT
) |
791 (1 << AC97_SLOT_PCM_RIGHT
) |
792 (1 << AC97_SLOT_PCM_CENTER
) |
793 (1 << AC97_SLOT_PCM_SLEFT
) |
794 (1 << AC97_SLOT_PCM_SRIGHT
) |
795 (1 << AC97_SLOT_LFE
),
798 .slots
= (1 << AC97_SLOT_PCM_LEFT
) |
799 (1 << AC97_SLOT_PCM_RIGHT
) |
800 (1 << AC97_SLOT_PCM_LEFT_0
) |
801 (1 << AC97_SLOT_PCM_RIGHT_0
),
810 .slots
= (1 << AC97_SLOT_PCM_LEFT
) |
811 (1 << AC97_SLOT_PCM_RIGHT
),
820 .slots
= (1 << AC97_SLOT_MIC
),
826 static struct snd_ac97_bus_ops aaci_bus_ops
= {
827 .write
= aaci_ac97_write
,
828 .read
= aaci_ac97_read
,
831 static int aaci_probe_ac97(struct aaci
*aaci
)
833 struct snd_ac97_template ac97_template
;
834 struct snd_ac97_bus
*ac97_bus
;
835 struct snd_ac97
*ac97
;
839 * Assert AACIRESET for 2us
841 writel(0, aaci
->base
+ AACI_RESET
);
843 writel(RESET_NRST
, aaci
->base
+ AACI_RESET
);
846 * Give the AC'97 codec more than enough time
847 * to wake up. (42us = ~2 frames at 48kHz.)
849 udelay(FRAME_PERIOD_US
* 2);
851 ret
= snd_ac97_bus(aaci
->card
, 0, &aaci_bus_ops
, aaci
, &ac97_bus
);
855 ac97_bus
->clock
= 48000;
856 aaci
->ac97_bus
= ac97_bus
;
858 memset(&ac97_template
, 0, sizeof(struct snd_ac97_template
));
859 ac97_template
.private_data
= aaci
;
860 ac97_template
.num
= 0;
861 ac97_template
.scaps
= AC97_SCAP_SKIP_MODEM
;
863 ret
= snd_ac97_mixer(ac97_bus
, &ac97_template
, &ac97
);
869 * Disable AC97 PC Beep input on audio codecs.
871 if (ac97_is_audio(ac97
))
872 snd_ac97_write_cache(ac97
, AC97_PC_BEEP
, 0x801e);
874 ret
= snd_ac97_pcm_assign(ac97_bus
, ARRAY_SIZE(ac97_defs
), ac97_defs
);
878 aaci
->playback
.pcm
= &ac97_bus
->pcms
[0];
879 aaci
->capture
.pcm
= &ac97_bus
->pcms
[1];
885 static void aaci_free_card(struct snd_card
*card
)
887 struct aaci
*aaci
= card
->private_data
;
892 static struct aaci
*aaci_init_card(struct amba_device
*dev
)
895 struct snd_card
*card
;
898 err
= snd_card_new(&dev
->dev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
,
899 THIS_MODULE
, sizeof(struct aaci
), &card
);
903 card
->private_free
= aaci_free_card
;
905 strlcpy(card
->driver
, DRIVER_NAME
, sizeof(card
->driver
));
906 strlcpy(card
->shortname
, "ARM AC'97 Interface", sizeof(card
->shortname
));
907 snprintf(card
->longname
, sizeof(card
->longname
),
908 "%s PL%03x rev%u at 0x%08llx, irq %d",
909 card
->shortname
, amba_part(dev
), amba_rev(dev
),
910 (unsigned long long)dev
->res
.start
, dev
->irq
[0]);
912 aaci
= card
->private_data
;
913 mutex_init(&aaci
->ac97_sem
);
914 mutex_init(&aaci
->irq_lock
);
918 /* Set MAINCR to allow slot 1 and 2 data IO */
919 aaci
->maincr
= MAINCR_IE
| MAINCR_SL1RXEN
| MAINCR_SL1TXEN
|
920 MAINCR_SL2RXEN
| MAINCR_SL2TXEN
;
925 static int aaci_init_pcm(struct aaci
*aaci
)
930 ret
= snd_pcm_new(aaci
->card
, "AACI AC'97", 0, 1, 1, &pcm
);
933 pcm
->private_data
= aaci
;
936 strlcpy(pcm
->name
, DRIVER_NAME
, sizeof(pcm
->name
));
938 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &aaci_playback_ops
);
939 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &aaci_capture_ops
);
940 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
948 static unsigned int aaci_size_fifo(struct aaci
*aaci
)
950 struct aaci_runtime
*aacirun
= &aaci
->playback
;
954 * Enable the channel, but don't assign it to any slots, so
955 * it won't empty onto the AC'97 link.
957 writel(CR_FEN
| CR_SZ16
| CR_EN
, aacirun
->base
+ AACI_TXCR
);
959 for (i
= 0; !(readl(aacirun
->base
+ AACI_SR
) & SR_TXFF
) && i
< 4096; i
++)
960 writel(0, aacirun
->fifo
);
962 writel(0, aacirun
->base
+ AACI_TXCR
);
965 * Re-initialise the AACI after the FIFO depth test, to
966 * ensure that the FIFOs are empty. Unfortunately, merely
967 * disabling the channel doesn't clear the FIFO.
969 writel(aaci
->maincr
& ~MAINCR_IE
, aaci
->base
+ AACI_MAINCR
);
970 readl(aaci
->base
+ AACI_MAINCR
);
972 writel(aaci
->maincr
, aaci
->base
+ AACI_MAINCR
);
975 * If we hit 4096 entries, we failed. Go back to the specified
984 static int aaci_probe(struct amba_device
*dev
,
985 const struct amba_id
*id
)
990 ret
= amba_request_regions(dev
, NULL
);
994 aaci
= aaci_init_card(dev
);
1000 aaci
->base
= ioremap(dev
->res
.start
, resource_size(&dev
->res
));
1007 * Playback uses AACI channel 0
1009 spin_lock_init(&aaci
->playback
.lock
);
1010 aaci
->playback
.base
= aaci
->base
+ AACI_CSCH1
;
1011 aaci
->playback
.fifo
= aaci
->base
+ AACI_DR1
;
1014 * Capture uses AACI channel 0
1016 spin_lock_init(&aaci
->capture
.lock
);
1017 aaci
->capture
.base
= aaci
->base
+ AACI_CSCH1
;
1018 aaci
->capture
.fifo
= aaci
->base
+ AACI_DR1
;
1020 for (i
= 0; i
< 4; i
++) {
1021 void __iomem
*base
= aaci
->base
+ i
* 0x14;
1023 writel(0, base
+ AACI_IE
);
1024 writel(0, base
+ AACI_TXCR
);
1025 writel(0, base
+ AACI_RXCR
);
1028 writel(0x1fff, aaci
->base
+ AACI_INTCLR
);
1029 writel(aaci
->maincr
, aaci
->base
+ AACI_MAINCR
);
1031 * Fix: ac97 read back fail errors by reading
1032 * from any arbitrary aaci register.
1034 readl(aaci
->base
+ AACI_CSCH1
);
1035 ret
= aaci_probe_ac97(aaci
);
1040 * Size the FIFOs (must be multiple of 16).
1041 * This is the number of entries in the FIFO.
1043 aaci
->fifo_depth
= aaci_size_fifo(aaci
);
1044 if (aaci
->fifo_depth
& 15) {
1045 printk(KERN_WARNING
"AACI: FIFO depth %d not supported\n",
1051 ret
= aaci_init_pcm(aaci
);
1055 ret
= snd_card_register(aaci
->card
);
1057 dev_info(&dev
->dev
, "%s\n", aaci
->card
->longname
);
1058 dev_info(&dev
->dev
, "FIFO %u entries\n", aaci
->fifo_depth
);
1059 amba_set_drvdata(dev
, aaci
->card
);
1065 snd_card_free(aaci
->card
);
1066 amba_release_regions(dev
);
1070 static int aaci_remove(struct amba_device
*dev
)
1072 struct snd_card
*card
= amba_get_drvdata(dev
);
1075 struct aaci
*aaci
= card
->private_data
;
1076 writel(0, aaci
->base
+ AACI_MAINCR
);
1078 snd_card_free(card
);
1079 amba_release_regions(dev
);
1085 static struct amba_id aaci_ids
[] = {
1093 MODULE_DEVICE_TABLE(amba
, aaci_ids
);
1095 static struct amba_driver aaci_driver
= {
1097 .name
= DRIVER_NAME
,
1098 .pm
= AACI_DEV_PM_OPS
,
1100 .probe
= aaci_probe
,
1101 .remove
= aaci_remove
,
1102 .id_table
= aaci_ids
,
1105 module_amba_driver(aaci_driver
);
1107 MODULE_LICENSE("GPL");
1108 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");