include/drm/drm_edid.h

   1 /*
   2  * Copyright © 2007-2008 Intel Corporation
   3  *   Jesse Barnes <jesse.barnes@intel.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef __DRM_EDID_H__
  24 #define __DRM_EDID_H__
  25
  26 #include <linux/types.h>
  27 #include <linux/hdmi.h>
  28
  29 struct drm_device;
  30 struct i2c_adapter;
  31
  32 #define EDID_LENGTH 128
  33 #define DDC_ADDR 0x50
  34 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
  35
  36 #define CEA_EXT     0x02
  37 #define VTB_EXT     0x10
  38 #define DI_EXT      0x40
  39 #define LS_EXT      0x50
  40 #define MI_EXT      0x60
  41 #define DISPLAYID_EXT 0x70
  42
  43 struct est_timings {
  44         u8 t1;
  45         u8 t2;
  46         u8 mfg_rsvd;
  47 } __attribute__((packed));
  48
  49 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
  50 #define EDID_TIMING_ASPECT_SHIFT 6
  51 #define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)
  52
  53 /* need to add 60 */
  54 #define EDID_TIMING_VFREQ_SHIFT  0
  55 #define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)
  56
  57 struct std_timing {
  58         u8 hsize; /* need to multiply by 8 then add 248 */
  59         u8 vfreq_aspect;
  60 } __attribute__((packed));
  61
  62 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
  63 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
  64 #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
  65 #define DRM_EDID_PT_STEREO         (1 << 5)
  66 #define DRM_EDID_PT_INTERLACED     (1 << 7)
  67
  68 /* If detailed data is pixel timing */
  69 struct detailed_pixel_timing {
  70         u8 hactive_lo;
  71         u8 hblank_lo;
  72         u8 hactive_hblank_hi;
  73         u8 vactive_lo;
  74         u8 vblank_lo;
  75         u8 vactive_vblank_hi;
  76         u8 hsync_offset_lo;
  77         u8 hsync_pulse_width_lo;
  78         u8 vsync_offset_pulse_width_lo;
  79         u8 hsync_vsync_offset_pulse_width_hi;
  80         u8 width_mm_lo;
  81         u8 height_mm_lo;
  82         u8 width_height_mm_hi;
  83         u8 hborder;
  84         u8 vborder;
  85         u8 misc;
  86 } __attribute__((packed));
  87
  88 /* If it's not pixel timing, it'll be one of the below */
  89 struct detailed_data_string {
  90         u8 str[13];
  91 } __attribute__((packed));
  92
  93 struct detailed_data_monitor_range {
  94         u8 min_vfreq;
  95         u8 max_vfreq;
  96         u8 min_hfreq_khz;
  97         u8 max_hfreq_khz;
  98         u8 pixel_clock_mhz; /* need to multiply by 10 */
  99         u8 flags;
 100         union {
 101                 struct {
 102                         u8 reserved;
 103                         u8 hfreq_start_khz; /* need to multiply by 2 */
 104                         u8 c; /* need to divide by 2 */
 105                         __le16 m;
 106                         u8 k;
 107                         u8 j; /* need to divide by 2 */
 108                 } __attribute__((packed)) gtf2;
 109                 struct {
 110                         u8 version;
 111                         u8 data1; /* high 6 bits: extra clock resolution */
 112                         u8 data2; /* plus low 2 of above: max hactive */
 113                         u8 supported_aspects;
 114                         u8 flags; /* preferred aspect and blanking support */
 115                         u8 supported_scalings;
 116                         u8 preferred_refresh;
 117                 } __attribute__((packed)) cvt;
 118         } formula;
 119 } __attribute__((packed));
 120
 121 struct detailed_data_wpindex {
 122         u8 white_yx_lo; /* Lower 2 bits each */
 123         u8 white_x_hi;
 124         u8 white_y_hi;
 125         u8 gamma; /* need to divide by 100 then add 1 */
 126 } __attribute__((packed));
 127
 128 struct detailed_data_color_point {
 129         u8 windex1;
 130         u8 wpindex1[3];
 131         u8 windex2;
 132         u8 wpindex2[3];
 133 } __attribute__((packed));
 134
 135 struct cvt_timing {
 136         u8 code[3];
 137 } __attribute__((packed));
 138
 139 struct detailed_non_pixel {
 140         u8 pad1;
 141         u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
 142                     fb=color point data, fa=standard timing data,
 143                     f9=undefined, f8=mfg. reserved */
 144         u8 pad2;
 145         union {
 146                 struct detailed_data_string str;
 147                 struct detailed_data_monitor_range range;
 148                 struct detailed_data_wpindex color;
 149                 struct std_timing timings[6];
 150                 struct cvt_timing cvt[4];
 151         } data;
 152 } __attribute__((packed));
 153
 154 #define EDID_DETAIL_EST_TIMINGS 0xf7
 155 #define EDID_DETAIL_CVT_3BYTE 0xf8
 156 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
 157 #define EDID_DETAIL_STD_MODES 0xfa
 158 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
 159 #define EDID_DETAIL_MONITOR_NAME 0xfc
 160 #define EDID_DETAIL_MONITOR_RANGE 0xfd
 161 #define EDID_DETAIL_MONITOR_STRING 0xfe
 162 #define EDID_DETAIL_MONITOR_SERIAL 0xff
 163
 164 struct detailed_timing {
 165         __le16 pixel_clock; /* need to multiply by 10 KHz */
 166         union {
 167                 struct detailed_pixel_timing pixel_data;
 168                 struct detailed_non_pixel other_data;
 169         } data;
 170 } __attribute__((packed));
 171
 172 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
 173 #define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
 174 #define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
 175 #define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
 176 #define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
 177 #define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
 178 #define DRM_EDID_INPUT_DIGITAL         (1 << 7)
 179 #define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4)
 180 #define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4)
 181 #define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4)
 182 #define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4)
 183 #define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4)
 184 #define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4)
 185 #define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4)
 186 #define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4)
 187 #define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4)
 188 #define DRM_EDID_DIGITAL_TYPE_UNDEF    (0)
 189 #define DRM_EDID_DIGITAL_TYPE_DVI      (1)
 190 #define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2)
 191 #define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3)
 192 #define DRM_EDID_DIGITAL_TYPE_MDDI     (4)
 193 #define DRM_EDID_DIGITAL_TYPE_DP       (5)
 194
 195 #define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
 196 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
 197 #define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
 198 /* If analog */
 199 #define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
 200 /* If digital */
 201 #define DRM_EDID_FEATURE_COLOR_MASK       (3 << 3)
 202 #define DRM_EDID_FEATURE_RGB              (0 << 3)
 203 #define DRM_EDID_FEATURE_RGB_YCRCB444     (1 << 3)
 204 #define DRM_EDID_FEATURE_RGB_YCRCB422     (2 << 3)
 205 #define DRM_EDID_FEATURE_RGB_YCRCB        (3 << 3) /* both 4:4:4 and 4:2:2 */
 206
 207 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
 208 #define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
 209 #define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)
 210
 211 #define DRM_EDID_HDMI_DC_48               (1 << 6)
 212 #define DRM_EDID_HDMI_DC_36               (1 << 5)
 213 #define DRM_EDID_HDMI_DC_30               (1 << 4)
 214 #define DRM_EDID_HDMI_DC_Y444             (1 << 3)
 215
 216 /* ELD Header Block */
 217 #define DRM_ELD_HEADER_BLOCK_SIZE       4
 218
 219 #define DRM_ELD_VER                     0
 220 # define DRM_ELD_VER_SHIFT              3
 221 # define DRM_ELD_VER_MASK               (0x1f << 3)
 222 # define DRM_ELD_VER_CEA861D            (2 << 3) /* supports 861D or below */
 223 # define DRM_ELD_VER_CANNED             (0x1f << 3)
 224
 225 #define DRM_ELD_BASELINE_ELD_LEN        2       /* in dwords! */
 226
 227 /* ELD Baseline Block for ELD_Ver == 2 */
 228 #define DRM_ELD_CEA_EDID_VER_MNL        4
 229 # define DRM_ELD_CEA_EDID_VER_SHIFT     5
 230 # define DRM_ELD_CEA_EDID_VER_MASK      (7 << 5)
 231 # define DRM_ELD_CEA_EDID_VER_NONE      (0 << 5)
 232 # define DRM_ELD_CEA_EDID_VER_CEA861    (1 << 5)
 233 # define DRM_ELD_CEA_EDID_VER_CEA861A   (2 << 5)
 234 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
 235 # define DRM_ELD_MNL_SHIFT              0
 236 # define DRM_ELD_MNL_MASK               (0x1f << 0)
 237
 238 #define DRM_ELD_SAD_COUNT_CONN_TYPE     5
 239 # define DRM_ELD_SAD_COUNT_SHIFT        4
 240 # define DRM_ELD_SAD_COUNT_MASK         (0xf << 4)
 241 # define DRM_ELD_CONN_TYPE_SHIFT        2
 242 # define DRM_ELD_CONN_TYPE_MASK         (3 << 2)
 243 # define DRM_ELD_CONN_TYPE_HDMI         (0 << 2)
 244 # define DRM_ELD_CONN_TYPE_DP           (1 << 2)
 245 # define DRM_ELD_SUPPORTS_AI            (1 << 1)
 246 # define DRM_ELD_SUPPORTS_HDCP          (1 << 0)
 247
 248 #define DRM_ELD_AUD_SYNCH_DELAY         6       /* in units of 2 ms */
 249 # define DRM_ELD_AUD_SYNCH_DELAY_MAX    0xfa    /* 500 ms */
 250
 251 #define DRM_ELD_SPEAKER                 7
 252 # define DRM_ELD_SPEAKER_MASK           0x7f
 253 # define DRM_ELD_SPEAKER_RLRC           (1 << 6)
 254 # define DRM_ELD_SPEAKER_FLRC           (1 << 5)
 255 # define DRM_ELD_SPEAKER_RC             (1 << 4)
 256 # define DRM_ELD_SPEAKER_RLR            (1 << 3)
 257 # define DRM_ELD_SPEAKER_FC             (1 << 2)
 258 # define DRM_ELD_SPEAKER_LFE            (1 << 1)
 259 # define DRM_ELD_SPEAKER_FLR            (1 << 0)
 260
 261 #define DRM_ELD_PORT_ID                 8       /* offsets 8..15 inclusive */
 262 # define DRM_ELD_PORT_ID_LEN            8
 263
 264 #define DRM_ELD_MANUFACTURER_NAME0      16
 265 #define DRM_ELD_MANUFACTURER_NAME1      17
 266
 267 #define DRM_ELD_PRODUCT_CODE0           18
 268 #define DRM_ELD_PRODUCT_CODE1           19
 269
 270 #define DRM_ELD_MONITOR_NAME_STRING     20      /* offsets 20..(20+mnl-1) inclusive */
 271
 272 #define DRM_ELD_CEA_SAD(mnl, sad)       (20 + (mnl) + 3 * (sad))
 273
 274 struct edid {
 275         u8 header[8];
 276         /* Vendor & product info */
 277         u8 mfg_id[2];
 278         u8 prod_code[2];
 279         u32 serial; /* FIXME: byte order */
 280         u8 mfg_week;
 281         u8 mfg_year;
 282         /* EDID version */
 283         u8 version;
 284         u8 revision;
 285         /* Display info: */
 286         u8 input;
 287         u8 width_cm;
 288         u8 height_cm;
 289         u8 gamma;
 290         u8 features;
 291         /* Color characteristics */
 292         u8 red_green_lo;
 293         u8 black_white_lo;
 294         u8 red_x;
 295         u8 red_y;
 296         u8 green_x;
 297         u8 green_y;
 298         u8 blue_x;
 299         u8 blue_y;
 300         u8 white_x;
 301         u8 white_y;
 302         /* Est. timings and mfg rsvd timings*/
 303         struct est_timings established_timings;
 304         /* Standard timings 1-8*/
 305         struct std_timing standard_timings[8];
 306         /* Detailing timings 1-4 */
 307         struct detailed_timing detailed_timings[4];
 308         /* Number of 128 byte ext. blocks */
 309         u8 extensions;
 310         /* Checksum */
 311         u8 checksum;
 312 } __attribute__((packed));
 313
 314 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
 315
 316 /* Short Audio Descriptor */
 317 struct cea_sad {
 318         u8 format;
 319         u8 channels; /* max number of channels - 1 */
 320         u8 freq;
 321         u8 byte2; /* meaning depends on format */
 322 };
 323
 324 struct drm_encoder;
 325 struct drm_connector;
 326 struct drm_display_mode;
 327
 328 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
 329 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
 330 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
 331 int drm_av_sync_delay(struct drm_connector *connector,
 332                       const struct drm_display_mode *mode);
 333
 334 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
 335 struct edid *drm_load_edid_firmware(struct drm_connector *connector);
 336 #else
 337 static inline struct edid *
 338 drm_load_edid_firmware(struct drm_connector *connector)
 339 {
 340         return ERR_PTR(-ENOENT);
 341 }
 342 #endif
 343
 344 int
 345 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
 346                                          const struct drm_display_mode *mode);
 347 int
 348 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
 349                                             const struct drm_display_mode *mode);
 350 void
 351 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
 352                                    const struct drm_display_mode *mode,
 353                                    enum hdmi_quantization_range rgb_quant_range,
 354                                    bool rgb_quant_range_selectable);
 355
 356 /**
 357  * drm_eld_mnl - Get ELD monitor name length in bytes.
 358  * @eld: pointer to an eld memory structure with mnl set
 359  */
 360 static inline int drm_eld_mnl(const uint8_t *eld)
 361 {
 362         return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
 363 }
 364
 365 /**
 366  * drm_eld_sad - Get ELD SAD structures.
 367  * @eld: pointer to an eld memory structure with sad_count set
 368  */
 369 static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
 370 {
 371         unsigned int ver, mnl;
 372
 373         ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
 374         if (ver != 2 && ver != 31)
 375                 return NULL;
 376
 377         mnl = drm_eld_mnl(eld);
 378         if (mnl > 16)
 379                 return NULL;
 380
 381         return eld + DRM_ELD_CEA_SAD(mnl, 0);
 382 }
 383
 384 /**
 385  * drm_eld_sad_count - Get ELD SAD count.
 386  * @eld: pointer to an eld memory structure with sad_count set
 387  */
 388 static inline int drm_eld_sad_count(const uint8_t *eld)
 389 {
 390         return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
 391                 DRM_ELD_SAD_COUNT_SHIFT;
 392 }
 393
 394 /**
 395  * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
 396  * @eld: pointer to an eld memory structure with mnl and sad_count set
 397  *
 398  * This is a helper for determining the payload size of the baseline block, in
 399  * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
 400  */
 401 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
 402 {
 403         return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
 404                 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
 405 }
 406
 407 /**
 408  * drm_eld_size - Get ELD size in bytes
 409  * @eld: pointer to a complete eld memory structure
 410  *
 411  * The returned value does not include the vendor block. It's vendor specific,
 412  * and comprises of the remaining bytes in the ELD memory buffer after
 413  * drm_eld_size() bytes of header and baseline block.
 414  *
 415  * The returned value is guaranteed to be a multiple of 4.
 416  */
 417 static inline int drm_eld_size(const uint8_t *eld)
 418 {
 419         return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
 420 }
 421
 422 /**
 423  * drm_eld_get_spk_alloc - Get speaker allocation
 424  * @eld: pointer to an ELD memory structure
 425  *
 426  * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
 427  * field definitions to identify speakers.
 428  */
 429 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
 430 {
 431         return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
 432 }
 433
 434 /**
 435  * drm_eld_get_conn_type - Get device type hdmi/dp connected
 436  * @eld: pointer to an ELD memory structure
 437  *
 438  * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
 439  * identify the display type connected.
 440  */
 441 static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
 442 {
 443         return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
 444 }
 445
 446 bool drm_probe_ddc(struct i2c_adapter *adapter);
 447 struct edid *drm_do_get_edid(struct drm_connector *connector,
 448         int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
 449                               size_t len),
 450         void *data);
 451 struct edid *drm_get_edid(struct drm_connector *connector,
 452                           struct i2c_adapter *adapter);
 453 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
 454                                      struct i2c_adapter *adapter);
 455 struct edid *drm_edid_duplicate(const struct edid *edid);
 456 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
 457
 458 u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
 459 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
 460 bool drm_detect_hdmi_monitor(struct edid *edid);
 461 bool drm_detect_monitor_audio(struct edid *edid);
 462 bool drm_rgb_quant_range_selectable(struct edid *edid);
 463 enum hdmi_quantization_range
 464 drm_default_rgb_quant_range(const struct drm_display_mode *mode);
 465 int drm_add_modes_noedid(struct drm_connector *connector,
 466                          int hdisplay, int vdisplay);
 467 void drm_set_preferred_mode(struct drm_connector *connector,
 468                             int hpref, int vpref);
 469
 470 int drm_edid_header_is_valid(const u8 *raw_edid);
 471 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
 472                           bool *edid_corrupt);
 473 bool drm_edid_is_valid(struct edid *edid);
 474 void drm_edid_get_monitor_name(struct edid *edid, char *name,
 475                                int buflen);
 476 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
 477                                            int hsize, int vsize, int fresh,
 478                                            bool rb);
 479 #endif /* __DRM_EDID_H__ */