2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/mii.h>
24 #include <linux/crc32.h>
30 * return 1 if eeprom exist
32 int atl1c_check_eeprom_exist(struct atl1c_hw
*hw
)
36 AT_READ_REG(hw
, REG_TWSI_DEBUG
, &data
);
37 if (data
& TWSI_DEBUG_DEV_EXIST
)
40 AT_READ_REG(hw
, REG_MASTER_CTRL
, &data
);
41 if (data
& MASTER_CTRL_OTP_SEL
)
46 void atl1c_hw_set_mac_addr(struct atl1c_hw
*hw
, u8
*mac_addr
)
54 value
= mac_addr
[2] << 24 |
58 AT_WRITE_REG_ARRAY(hw
, REG_MAC_STA_ADDR
, 0, value
);
60 value
= mac_addr
[0] << 8 |
62 AT_WRITE_REG_ARRAY(hw
, REG_MAC_STA_ADDR
, 1, value
);
65 /* read mac address from hardware register */
66 static bool atl1c_read_current_addr(struct atl1c_hw
*hw
, u8
*eth_addr
)
70 AT_READ_REG(hw
, REG_MAC_STA_ADDR
, &addr
[0]);
71 AT_READ_REG(hw
, REG_MAC_STA_ADDR
+ 4, &addr
[1]);
73 *(u32
*) ð_addr
[2] = htonl(addr
[0]);
74 *(u16
*) ð_addr
[0] = htons((u16
)addr
[1]);
76 return is_valid_ether_addr(eth_addr
);
80 * atl1c_get_permanent_address
81 * return 0 if get valid mac address,
83 static int atl1c_get_permanent_address(struct atl1c_hw
*hw
)
89 bool raise_vol
= false;
91 /* MAC-address from BIOS is the 1st priority */
92 if (atl1c_read_current_addr(hw
, hw
->perm_mac_addr
))
96 AT_READ_REG(hw
, REG_OTP_CTRL
, &otp_ctrl_data
);
97 if (atl1c_check_eeprom_exist(hw
)) {
98 if (hw
->nic_type
== athr_l1c
|| hw
->nic_type
== athr_l2c
) {
100 if (!(otp_ctrl_data
& OTP_CTRL_CLK_EN
)) {
101 otp_ctrl_data
|= OTP_CTRL_CLK_EN
;
102 AT_WRITE_REG(hw
, REG_OTP_CTRL
, otp_ctrl_data
);
107 /* raise voltage temporally for l2cb */
108 if (hw
->nic_type
== athr_l2c_b
|| hw
->nic_type
== athr_l2c_b2
) {
109 atl1c_read_phy_dbg(hw
, MIIDBG_ANACTRL
, &phy_data
);
110 phy_data
&= ~ANACTRL_HB_EN
;
111 atl1c_write_phy_dbg(hw
, MIIDBG_ANACTRL
, phy_data
);
112 atl1c_read_phy_dbg(hw
, MIIDBG_VOLT_CTRL
, &phy_data
);
113 phy_data
|= VOLT_CTRL_SWLOWEST
;
114 atl1c_write_phy_dbg(hw
, MIIDBG_VOLT_CTRL
, phy_data
);
119 AT_READ_REG(hw
, REG_TWSI_CTRL
, &twsi_ctrl_data
);
120 twsi_ctrl_data
|= TWSI_CTRL_SW_LDSTART
;
121 AT_WRITE_REG(hw
, REG_TWSI_CTRL
, twsi_ctrl_data
);
122 for (i
= 0; i
< AT_TWSI_EEPROM_TIMEOUT
; i
++) {
124 AT_READ_REG(hw
, REG_TWSI_CTRL
, &twsi_ctrl_data
);
125 if ((twsi_ctrl_data
& TWSI_CTRL_SW_LDSTART
) == 0)
128 if (i
>= AT_TWSI_EEPROM_TIMEOUT
)
131 /* Disable OTP_CLK */
132 if ((hw
->nic_type
== athr_l1c
|| hw
->nic_type
== athr_l2c
)) {
133 otp_ctrl_data
&= ~OTP_CTRL_CLK_EN
;
134 AT_WRITE_REG(hw
, REG_OTP_CTRL
, otp_ctrl_data
);
138 atl1c_read_phy_dbg(hw
, MIIDBG_ANACTRL
, &phy_data
);
139 phy_data
|= ANACTRL_HB_EN
;
140 atl1c_write_phy_dbg(hw
, MIIDBG_ANACTRL
, phy_data
);
141 atl1c_read_phy_dbg(hw
, MIIDBG_VOLT_CTRL
, &phy_data
);
142 phy_data
&= ~VOLT_CTRL_SWLOWEST
;
143 atl1c_write_phy_dbg(hw
, MIIDBG_VOLT_CTRL
, phy_data
);
147 if (atl1c_read_current_addr(hw
, hw
->perm_mac_addr
))
153 bool atl1c_read_eeprom(struct atl1c_hw
*hw
, u32 offset
, u32
*p_value
)
162 return ret
; /* address do not align */
164 AT_READ_REG(hw
, REG_OTP_CTRL
, &otp_ctrl_data
);
165 if (!(otp_ctrl_data
& OTP_CTRL_CLK_EN
))
166 AT_WRITE_REG(hw
, REG_OTP_CTRL
,
167 (otp_ctrl_data
| OTP_CTRL_CLK_EN
));
169 AT_WRITE_REG(hw
, REG_EEPROM_DATA_LO
, 0);
170 control
= (offset
& EEPROM_CTRL_ADDR_MASK
) << EEPROM_CTRL_ADDR_SHIFT
;
171 AT_WRITE_REG(hw
, REG_EEPROM_CTRL
, control
);
173 for (i
= 0; i
< 10; i
++) {
175 AT_READ_REG(hw
, REG_EEPROM_CTRL
, &control
);
176 if (control
& EEPROM_CTRL_RW
)
179 if (control
& EEPROM_CTRL_RW
) {
180 AT_READ_REG(hw
, REG_EEPROM_CTRL
, &data
);
181 AT_READ_REG(hw
, REG_EEPROM_DATA_LO
, p_value
);
182 data
= data
& 0xFFFF;
183 *p_value
= swab32((data
<< 16) | (*p_value
>> 16));
186 if (!(otp_ctrl_data
& OTP_CTRL_CLK_EN
))
187 AT_WRITE_REG(hw
, REG_OTP_CTRL
, otp_ctrl_data
);
192 * Reads the adapter's MAC address from the EEPROM
194 * hw - Struct containing variables accessed by shared code
196 int atl1c_read_mac_addr(struct atl1c_hw
*hw
)
200 err
= atl1c_get_permanent_address(hw
);
202 eth_random_addr(hw
->perm_mac_addr
);
204 memcpy(hw
->mac_addr
, hw
->perm_mac_addr
, sizeof(hw
->perm_mac_addr
));
211 * set hash value for a multicast address
212 * hash calcu processing :
213 * 1. calcu 32bit CRC for multicast address
214 * 2. reverse crc with MSB to LSB
216 u32
atl1c_hash_mc_addr(struct atl1c_hw
*hw
, u8
*mc_addr
)
222 crc32
= ether_crc_le(6, mc_addr
);
223 for (i
= 0; i
< 32; i
++)
224 value
|= (((crc32
>> i
) & 1) << (31 - i
));
230 * Sets the bit in the multicast table corresponding to the hash value.
231 * hw - Struct containing variables accessed by shared code
232 * hash_value - Multicast address hash value
234 void atl1c_hash_set(struct atl1c_hw
*hw
, u32 hash_value
)
236 u32 hash_bit
, hash_reg
;
240 * The HASH Table is a register array of 2 32-bit registers.
241 * It is treated like an array of 64 bits. We want to set
242 * bit BitArray[hash_value]. So we figure out what register
243 * the bit is in, read it, OR in the new bit, then write
244 * back the new value. The register is determined by the
245 * upper bit of the hash value and the bit within that
246 * register are determined by the lower 5 bits of the value.
248 hash_reg
= (hash_value
>> 31) & 0x1;
249 hash_bit
= (hash_value
>> 26) & 0x1F;
251 mta
= AT_READ_REG_ARRAY(hw
, REG_RX_HASH_TABLE
, hash_reg
);
253 mta
|= (1 << hash_bit
);
255 AT_WRITE_REG_ARRAY(hw
, REG_RX_HASH_TABLE
, hash_reg
, mta
);
259 * wait mdio module be idle
263 bool atl1c_wait_mdio_idle(struct atl1c_hw
*hw
)
268 for (i
= 0; i
< MDIO_MAX_AC_TO
; i
++) {
269 AT_READ_REG(hw
, REG_MDIO_CTRL
, &val
);
270 if (!(val
& (MDIO_CTRL_BUSY
| MDIO_CTRL_START
)))
275 return i
!= MDIO_MAX_AC_TO
;
278 void atl1c_stop_phy_polling(struct atl1c_hw
*hw
)
280 if (!(hw
->ctrl_flags
& ATL1C_FPGA_VERSION
))
283 AT_WRITE_REG(hw
, REG_MDIO_CTRL
, 0);
284 atl1c_wait_mdio_idle(hw
);
287 void atl1c_start_phy_polling(struct atl1c_hw
*hw
, u16 clk_sel
)
291 if (!(hw
->ctrl_flags
& ATL1C_FPGA_VERSION
))
294 val
= MDIO_CTRL_SPRES_PRMBL
|
295 FIELDX(MDIO_CTRL_CLK_SEL
, clk_sel
) |
296 FIELDX(MDIO_CTRL_REG
, 1) |
299 AT_WRITE_REG(hw
, REG_MDIO_CTRL
, val
);
300 atl1c_wait_mdio_idle(hw
);
301 val
|= MDIO_CTRL_AP_EN
;
302 val
&= ~MDIO_CTRL_START
;
303 AT_WRITE_REG(hw
, REG_MDIO_CTRL
, val
);
309 * atl1c_read_phy_core
310 * core funtion to read register in PHY via MDIO control regsiter.
311 * ext: extension register (see IEEE 802.3)
312 * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
315 int atl1c_read_phy_core(struct atl1c_hw
*hw
, bool ext
, u8 dev
,
316 u16 reg
, u16
*phy_data
)
319 u16 clk_sel
= MDIO_CTRL_CLK_25_4
;
321 atl1c_stop_phy_polling(hw
);
325 /* only l2c_b2 & l1d_2 could use slow clock */
326 if ((hw
->nic_type
== athr_l2c_b2
|| hw
->nic_type
== athr_l1d_2
) &&
328 clk_sel
= MDIO_CTRL_CLK_25_128
;
330 val
= FIELDX(MDIO_EXTN_DEVAD
, dev
) | FIELDX(MDIO_EXTN_REG
, reg
);
331 AT_WRITE_REG(hw
, REG_MDIO_EXTN
, val
);
332 val
= MDIO_CTRL_SPRES_PRMBL
|
333 FIELDX(MDIO_CTRL_CLK_SEL
, clk_sel
) |
338 val
= MDIO_CTRL_SPRES_PRMBL
|
339 FIELDX(MDIO_CTRL_CLK_SEL
, clk_sel
) |
340 FIELDX(MDIO_CTRL_REG
, reg
) |
344 AT_WRITE_REG(hw
, REG_MDIO_CTRL
, val
);
346 if (!atl1c_wait_mdio_idle(hw
))
349 AT_READ_REG(hw
, REG_MDIO_CTRL
, &val
);
350 *phy_data
= (u16
)FIELD_GETX(val
, MDIO_CTRL_DATA
);
352 atl1c_start_phy_polling(hw
, clk_sel
);
358 * atl1c_write_phy_core
359 * core funtion to write to register in PHY via MDIO control regsiter.
360 * ext: extension register (see IEEE 802.3)
361 * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
364 int atl1c_write_phy_core(struct atl1c_hw
*hw
, bool ext
, u8 dev
,
365 u16 reg
, u16 phy_data
)
368 u16 clk_sel
= MDIO_CTRL_CLK_25_4
;
370 atl1c_stop_phy_polling(hw
);
373 /* only l2c_b2 & l1d_2 could use slow clock */
374 if ((hw
->nic_type
== athr_l2c_b2
|| hw
->nic_type
== athr_l1d_2
) &&
376 clk_sel
= MDIO_CTRL_CLK_25_128
;
379 val
= FIELDX(MDIO_EXTN_DEVAD
, dev
) | FIELDX(MDIO_EXTN_REG
, reg
);
380 AT_WRITE_REG(hw
, REG_MDIO_EXTN
, val
);
381 val
= MDIO_CTRL_SPRES_PRMBL
|
382 FIELDX(MDIO_CTRL_CLK_SEL
, clk_sel
) |
383 FIELDX(MDIO_CTRL_DATA
, phy_data
) |
387 val
= MDIO_CTRL_SPRES_PRMBL
|
388 FIELDX(MDIO_CTRL_CLK_SEL
, clk_sel
) |
389 FIELDX(MDIO_CTRL_DATA
, phy_data
) |
390 FIELDX(MDIO_CTRL_REG
, reg
) |
393 AT_WRITE_REG(hw
, REG_MDIO_CTRL
, val
);
395 if (!atl1c_wait_mdio_idle(hw
))
398 atl1c_start_phy_polling(hw
, clk_sel
);
404 * Reads the value from a PHY register
405 * hw - Struct containing variables accessed by shared code
406 * reg_addr - address of the PHY register to read
408 int atl1c_read_phy_reg(struct atl1c_hw
*hw
, u16 reg_addr
, u16
*phy_data
)
410 return atl1c_read_phy_core(hw
, false, 0, reg_addr
, phy_data
);
414 * Writes a value to a PHY register
415 * hw - Struct containing variables accessed by shared code
416 * reg_addr - address of the PHY register to write
417 * data - data to write to the PHY
419 int atl1c_write_phy_reg(struct atl1c_hw
*hw
, u32 reg_addr
, u16 phy_data
)
421 return atl1c_write_phy_core(hw
, false, 0, reg_addr
, phy_data
);
424 /* read from PHY extension register */
425 int atl1c_read_phy_ext(struct atl1c_hw
*hw
, u8 dev_addr
,
426 u16 reg_addr
, u16
*phy_data
)
428 return atl1c_read_phy_core(hw
, true, dev_addr
, reg_addr
, phy_data
);
431 /* write to PHY extension register */
432 int atl1c_write_phy_ext(struct atl1c_hw
*hw
, u8 dev_addr
,
433 u16 reg_addr
, u16 phy_data
)
435 return atl1c_write_phy_core(hw
, true, dev_addr
, reg_addr
, phy_data
);
438 int atl1c_read_phy_dbg(struct atl1c_hw
*hw
, u16 reg_addr
, u16
*phy_data
)
442 err
= atl1c_write_phy_reg(hw
, MII_DBG_ADDR
, reg_addr
);
446 err
= atl1c_read_phy_reg(hw
, MII_DBG_DATA
, phy_data
);
451 int atl1c_write_phy_dbg(struct atl1c_hw
*hw
, u16 reg_addr
, u16 phy_data
)
455 err
= atl1c_write_phy_reg(hw
, MII_DBG_ADDR
, reg_addr
);
459 err
= atl1c_write_phy_reg(hw
, MII_DBG_DATA
, phy_data
);
465 * Configures PHY autoneg and flow control advertisement settings
467 * hw - Struct containing variables accessed by shared code
469 static int atl1c_phy_setup_adv(struct atl1c_hw
*hw
)
471 u16 mii_adv_data
= ADVERTISE_DEFAULT_CAP
& ~ADVERTISE_ALL
;
472 u16 mii_giga_ctrl_data
= GIGA_CR_1000T_DEFAULT_CAP
&
473 ~GIGA_CR_1000T_SPEED_MASK
;
475 if (hw
->autoneg_advertised
& ADVERTISED_10baseT_Half
)
476 mii_adv_data
|= ADVERTISE_10HALF
;
477 if (hw
->autoneg_advertised
& ADVERTISED_10baseT_Full
)
478 mii_adv_data
|= ADVERTISE_10FULL
;
479 if (hw
->autoneg_advertised
& ADVERTISED_100baseT_Half
)
480 mii_adv_data
|= ADVERTISE_100HALF
;
481 if (hw
->autoneg_advertised
& ADVERTISED_100baseT_Full
)
482 mii_adv_data
|= ADVERTISE_100FULL
;
484 if (hw
->autoneg_advertised
& ADVERTISED_Autoneg
)
485 mii_adv_data
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
|
486 ADVERTISE_100HALF
| ADVERTISE_100FULL
;
488 if (hw
->link_cap_flags
& ATL1C_LINK_CAP_1000M
) {
489 if (hw
->autoneg_advertised
& ADVERTISED_1000baseT_Half
)
490 mii_giga_ctrl_data
|= ADVERTISE_1000HALF
;
491 if (hw
->autoneg_advertised
& ADVERTISED_1000baseT_Full
)
492 mii_giga_ctrl_data
|= ADVERTISE_1000FULL
;
493 if (hw
->autoneg_advertised
& ADVERTISED_Autoneg
)
494 mii_giga_ctrl_data
|= ADVERTISE_1000HALF
|
498 if (atl1c_write_phy_reg(hw
, MII_ADVERTISE
, mii_adv_data
) != 0 ||
499 atl1c_write_phy_reg(hw
, MII_CTRL1000
, mii_giga_ctrl_data
) != 0)
504 void atl1c_phy_disable(struct atl1c_hw
*hw
)
506 atl1c_power_saving(hw
, 0);
510 int atl1c_phy_reset(struct atl1c_hw
*hw
)
512 struct atl1c_adapter
*adapter
= hw
->adapter
;
513 struct pci_dev
*pdev
= adapter
->pdev
;
515 u32 phy_ctrl_data
, lpi_ctrl
;
519 AT_READ_REG(hw
, REG_GPHY_CTRL
, &phy_ctrl_data
);
520 phy_ctrl_data
&= ~(GPHY_CTRL_EXT_RESET
| GPHY_CTRL_PHY_IDDQ
|
521 GPHY_CTRL_GATE_25M_EN
| GPHY_CTRL_PWDOWN_HW
| GPHY_CTRL_CLS
);
522 phy_ctrl_data
|= GPHY_CTRL_SEL_ANA_RST
;
523 if (!(hw
->ctrl_flags
& ATL1C_HIB_DISABLE
))
524 phy_ctrl_data
|= (GPHY_CTRL_HIB_EN
| GPHY_CTRL_HIB_PULSE
);
526 phy_ctrl_data
&= ~(GPHY_CTRL_HIB_EN
| GPHY_CTRL_HIB_PULSE
);
527 AT_WRITE_REG(hw
, REG_GPHY_CTRL
, phy_ctrl_data
);
530 AT_WRITE_REG(hw
, REG_GPHY_CTRL
, phy_ctrl_data
| GPHY_CTRL_EXT_RESET
);
532 udelay(10 * GPHY_CTRL_EXT_RST_TO
); /* delay 800us */
535 if (hw
->nic_type
== athr_l2c_b
) {
536 atl1c_read_phy_dbg(hw
, MIIDBG_CFGLPSPD
, &phy_data
);
537 atl1c_write_phy_dbg(hw
, MIIDBG_CFGLPSPD
,
538 phy_data
& ~CFGLPSPD_RSTCNT_CLK125SW
);
541 /* tx-half amplitude issue fix */
542 if (hw
->nic_type
== athr_l2c_b
|| hw
->nic_type
== athr_l2c_b2
) {
543 atl1c_read_phy_dbg(hw
, MIIDBG_CABLE1TH_DET
, &phy_data
);
544 phy_data
|= CABLE1TH_DET_EN
;
545 atl1c_write_phy_dbg(hw
, MIIDBG_CABLE1TH_DET
, phy_data
);
548 /* clear bit3 of dbgport 3B to lower voltage */
549 if (!(hw
->ctrl_flags
& ATL1C_HIB_DISABLE
)) {
550 if (hw
->nic_type
== athr_l2c_b
|| hw
->nic_type
== athr_l2c_b2
) {
551 atl1c_read_phy_dbg(hw
, MIIDBG_VOLT_CTRL
, &phy_data
);
552 phy_data
&= ~VOLT_CTRL_SWLOWEST
;
553 atl1c_write_phy_dbg(hw
, MIIDBG_VOLT_CTRL
, phy_data
);
555 /* power saving config */
557 hw
->nic_type
== athr_l1d
|| hw
->nic_type
== athr_l1d_2
?
558 L1D_LEGCYPS_DEF
: L1C_LEGCYPS_DEF
;
559 atl1c_write_phy_dbg(hw
, MIIDBG_LEGCYPS
, phy_data
);
561 atl1c_write_phy_dbg(hw
, MIIDBG_SYSMODCTRL
,
562 SYSMODCTRL_IECHOADJ_DEF
);
565 atl1c_read_phy_dbg(hw
, MIIDBG_LEGCYPS
, &phy_data
);
566 atl1c_write_phy_dbg(hw
, MIIDBG_LEGCYPS
,
567 phy_data
& ~LEGCYPS_EN
);
568 /* disable hibernate */
569 atl1c_read_phy_dbg(hw
, MIIDBG_HIBNEG
, &phy_data
);
570 atl1c_write_phy_dbg(hw
, MIIDBG_HIBNEG
,
571 phy_data
& HIBNEG_PSHIB_EN
);
573 /* disable AZ(EEE) by default */
574 if (hw
->nic_type
== athr_l1d
|| hw
->nic_type
== athr_l1d_2
||
575 hw
->nic_type
== athr_l2c_b2
) {
576 AT_READ_REG(hw
, REG_LPI_CTRL
, &lpi_ctrl
);
577 AT_WRITE_REG(hw
, REG_LPI_CTRL
, lpi_ctrl
& ~LPI_CTRL_EN
);
578 atl1c_write_phy_ext(hw
, MIIEXT_ANEG
, MIIEXT_LOCAL_EEEADV
, 0);
579 atl1c_write_phy_ext(hw
, MIIEXT_PCS
, MIIEXT_CLDCTRL3
,
583 /* other debug port to set */
584 atl1c_write_phy_dbg(hw
, MIIDBG_ANACTRL
, ANACTRL_DEF
);
585 atl1c_write_phy_dbg(hw
, MIIDBG_SRDSYSMOD
, SRDSYSMOD_DEF
);
586 atl1c_write_phy_dbg(hw
, MIIDBG_TST10BTCFG
, TST10BTCFG_DEF
);
587 /* UNH-IOL test issue, set bit7 */
588 atl1c_write_phy_dbg(hw
, MIIDBG_TST100BTCFG
,
589 TST100BTCFG_DEF
| TST100BTCFG_LITCH_EN
);
591 /* set phy interrupt mask */
592 phy_data
= IER_LINK_UP
| IER_LINK_DOWN
;
593 err
= atl1c_write_phy_reg(hw
, MII_IER
, phy_data
);
595 if (netif_msg_hw(adapter
))
597 "Error enable PHY linkChange Interrupt\n");
603 int atl1c_phy_init(struct atl1c_hw
*hw
)
605 struct atl1c_adapter
*adapter
= hw
->adapter
;
606 struct pci_dev
*pdev
= adapter
->pdev
;
608 u16 mii_bmcr_data
= BMCR_RESET
;
610 if ((atl1c_read_phy_reg(hw
, MII_PHYSID1
, &hw
->phy_id1
) != 0) ||
611 (atl1c_read_phy_reg(hw
, MII_PHYSID2
, &hw
->phy_id2
) != 0)) {
612 dev_err(&pdev
->dev
, "Error get phy ID\n");
615 switch (hw
->media_type
) {
616 case MEDIA_TYPE_AUTO_SENSOR
:
617 ret_val
= atl1c_phy_setup_adv(hw
);
619 if (netif_msg_link(adapter
))
621 "Error Setting up Auto-Negotiation\n");
624 mii_bmcr_data
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
626 case MEDIA_TYPE_100M_FULL
:
627 mii_bmcr_data
|= BMCR_SPEED100
| BMCR_FULLDPLX
;
629 case MEDIA_TYPE_100M_HALF
:
630 mii_bmcr_data
|= BMCR_SPEED100
;
632 case MEDIA_TYPE_10M_FULL
:
633 mii_bmcr_data
|= BMCR_FULLDPLX
;
635 case MEDIA_TYPE_10M_HALF
:
638 if (netif_msg_link(adapter
))
639 dev_err(&pdev
->dev
, "Wrong Media type %d\n",
644 ret_val
= atl1c_write_phy_reg(hw
, MII_BMCR
, mii_bmcr_data
);
647 hw
->phy_configured
= true;
653 * Detects the current speed and duplex settings of the hardware.
655 * hw - Struct containing variables accessed by shared code
656 * speed - Speed of the connection
657 * duplex - Duplex setting of the connection
659 int atl1c_get_speed_and_duplex(struct atl1c_hw
*hw
, u16
*speed
, u16
*duplex
)
664 /* Read PHY Specific Status Register (17) */
665 err
= atl1c_read_phy_reg(hw
, MII_GIGA_PSSR
, &phy_data
);
669 if (!(phy_data
& GIGA_PSSR_SPD_DPLX_RESOLVED
))
672 switch (phy_data
& GIGA_PSSR_SPEED
) {
673 case GIGA_PSSR_1000MBS
:
676 case GIGA_PSSR_100MBS
:
679 case GIGA_PSSR_10MBS
:
686 if (phy_data
& GIGA_PSSR_DPLX
)
687 *duplex
= FULL_DUPLEX
;
689 *duplex
= HALF_DUPLEX
;
694 /* select one link mode to get lower power consumption */
695 int atl1c_phy_to_ps_link(struct atl1c_hw
*hw
)
697 struct atl1c_adapter
*adapter
= hw
->adapter
;
698 struct pci_dev
*pdev
= adapter
->pdev
;
700 u16 autoneg_advertised
= ADVERTISED_10baseT_Half
;
701 u16 save_autoneg_advertised
;
705 u16 duplex
= FULL_DUPLEX
;
708 atl1c_read_phy_reg(hw
, MII_BMSR
, &phy_data
);
709 atl1c_read_phy_reg(hw
, MII_BMSR
, &phy_data
);
710 if (phy_data
& BMSR_LSTATUS
) {
711 atl1c_read_phy_reg(hw
, MII_LPA
, &mii_lpa_data
);
712 if (mii_lpa_data
& LPA_10FULL
)
713 autoneg_advertised
= ADVERTISED_10baseT_Full
;
714 else if (mii_lpa_data
& LPA_10HALF
)
715 autoneg_advertised
= ADVERTISED_10baseT_Half
;
716 else if (mii_lpa_data
& LPA_100HALF
)
717 autoneg_advertised
= ADVERTISED_100baseT_Half
;
718 else if (mii_lpa_data
& LPA_100FULL
)
719 autoneg_advertised
= ADVERTISED_100baseT_Full
;
721 save_autoneg_advertised
= hw
->autoneg_advertised
;
722 hw
->phy_configured
= false;
723 hw
->autoneg_advertised
= autoneg_advertised
;
724 if (atl1c_restart_autoneg(hw
) != 0) {
725 dev_dbg(&pdev
->dev
, "phy autoneg failed\n");
728 hw
->autoneg_advertised
= save_autoneg_advertised
;
731 for (i
= 0; i
< AT_SUSPEND_LINK_TIMEOUT
; i
++) {
733 atl1c_read_phy_reg(hw
, MII_BMSR
, &phy_data
);
734 atl1c_read_phy_reg(hw
, MII_BMSR
, &phy_data
);
735 if (phy_data
& BMSR_LSTATUS
) {
736 if (atl1c_get_speed_and_duplex(hw
, &speed
,
739 "get speed and duplex failed\n");
746 duplex
= HALF_DUPLEX
;
748 adapter
->link_speed
= speed
;
749 adapter
->link_duplex
= duplex
;
754 int atl1c_restart_autoneg(struct atl1c_hw
*hw
)
757 u16 mii_bmcr_data
= BMCR_RESET
;
759 err
= atl1c_phy_setup_adv(hw
);
762 mii_bmcr_data
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
764 return atl1c_write_phy_reg(hw
, MII_BMCR
, mii_bmcr_data
);
767 int atl1c_power_saving(struct atl1c_hw
*hw
, u32 wufc
)
769 struct atl1c_adapter
*adapter
= hw
->adapter
;
770 struct pci_dev
*pdev
= adapter
->pdev
;
771 u32 master_ctrl
, mac_ctrl
, phy_ctrl
;
776 speed
= adapter
->link_speed
== SPEED_1000
?
777 MAC_CTRL_SPEED_1000
: MAC_CTRL_SPEED_10_100
;
779 AT_READ_REG(hw
, REG_MASTER_CTRL
, &master_ctrl
);
780 AT_READ_REG(hw
, REG_MAC_CTRL
, &mac_ctrl
);
781 AT_READ_REG(hw
, REG_GPHY_CTRL
, &phy_ctrl
);
783 master_ctrl
&= ~MASTER_CTRL_CLK_SEL_DIS
;
784 mac_ctrl
= FIELD_SETX(mac_ctrl
, MAC_CTRL_SPEED
, speed
);
785 mac_ctrl
&= ~(MAC_CTRL_DUPLX
| MAC_CTRL_RX_EN
| MAC_CTRL_TX_EN
);
786 if (adapter
->link_duplex
== FULL_DUPLEX
)
787 mac_ctrl
|= MAC_CTRL_DUPLX
;
788 phy_ctrl
&= ~(GPHY_CTRL_EXT_RESET
| GPHY_CTRL_CLS
);
789 phy_ctrl
|= GPHY_CTRL_SEL_ANA_RST
| GPHY_CTRL_HIB_PULSE
|
791 if (!wufc
) { /* without WoL */
792 master_ctrl
|= MASTER_CTRL_CLK_SEL_DIS
;
793 phy_ctrl
|= GPHY_CTRL_PHY_IDDQ
| GPHY_CTRL_PWDOWN_HW
;
794 AT_WRITE_REG(hw
, REG_MASTER_CTRL
, master_ctrl
);
795 AT_WRITE_REG(hw
, REG_MAC_CTRL
, mac_ctrl
);
796 AT_WRITE_REG(hw
, REG_GPHY_CTRL
, phy_ctrl
);
797 AT_WRITE_REG(hw
, REG_WOL_CTRL
, 0);
798 hw
->phy_configured
= false; /* re-init PHY when resume */
801 phy_ctrl
|= GPHY_CTRL_EXT_RESET
;
802 if (wufc
& AT_WUFC_MAG
) {
803 mac_ctrl
|= MAC_CTRL_RX_EN
| MAC_CTRL_BC_EN
;
804 wol_ctrl
|= WOL_MAGIC_EN
| WOL_MAGIC_PME_EN
;
805 if (hw
->nic_type
== athr_l2c_b
&& hw
->revision_id
== L2CB_V11
)
806 wol_ctrl
|= WOL_PATTERN_EN
| WOL_PATTERN_PME_EN
;
808 if (wufc
& AT_WUFC_LNKC
) {
809 wol_ctrl
|= WOL_LINK_CHG_EN
| WOL_LINK_CHG_PME_EN
;
810 if (atl1c_write_phy_reg(hw
, MII_IER
, IER_LINK_UP
) != 0) {
811 dev_dbg(&pdev
->dev
, "%s: write phy MII_IER failed.\n",
815 /* clear PHY interrupt */
816 atl1c_read_phy_reg(hw
, MII_ISR
, &phy_data
);
818 dev_dbg(&pdev
->dev
, "%s: suspend MAC=%x,MASTER=%x,PHY=0x%x,WOL=%x\n",
819 atl1c_driver_name
, mac_ctrl
, master_ctrl
, phy_ctrl
, wol_ctrl
);
820 AT_WRITE_REG(hw
, REG_MASTER_CTRL
, master_ctrl
);
821 AT_WRITE_REG(hw
, REG_MAC_CTRL
, mac_ctrl
);
822 AT_WRITE_REG(hw
, REG_GPHY_CTRL
, phy_ctrl
);
823 AT_WRITE_REG(hw
, REG_WOL_CTRL
, wol_ctrl
);
829 /* configure phy after Link change Event */
830 void atl1c_post_phy_linkchg(struct atl1c_hw
*hw
, u16 link_speed
)
833 bool adj_thresh
= false;
835 if (hw
->nic_type
== athr_l2c_b
|| hw
->nic_type
== athr_l2c_b2
||
836 hw
->nic_type
== athr_l1d
|| hw
->nic_type
== athr_l1d_2
)
839 if (link_speed
!= SPEED_0
) { /* link up */
840 /* az with brcm, half-amp */
841 if (hw
->nic_type
== athr_l1d_2
) {
842 atl1c_read_phy_ext(hw
, MIIEXT_PCS
, MIIEXT_CLDCTRL6
,
844 phy_val
= FIELD_GETX(phy_val
, CLDCTRL6_CAB_LEN
);
845 phy_val
= phy_val
> CLDCTRL6_CAB_LEN_SHORT
?
846 AZ_ANADECT_LONG
: AZ_ANADECT_DEF
;
847 atl1c_write_phy_dbg(hw
, MIIDBG_AZ_ANADECT
, phy_val
);
849 /* threshold adjust */
850 if (adj_thresh
&& link_speed
== SPEED_100
&& hw
->msi_lnkpatch
) {
851 atl1c_write_phy_dbg(hw
, MIIDBG_MSE16DB
, L1D_MSE16DB_UP
);
852 atl1c_write_phy_dbg(hw
, MIIDBG_SYSMODCTRL
,
853 L1D_SYSMODCTRL_IECHOADJ_DEF
);
855 } else { /* link down */
856 if (adj_thresh
&& hw
->msi_lnkpatch
) {
857 atl1c_write_phy_dbg(hw
, MIIDBG_SYSMODCTRL
,
858 SYSMODCTRL_IECHOADJ_DEF
);
859 atl1c_write_phy_dbg(hw
, MIIDBG_MSE16DB
,