drivers/dma/fsldma.h

   1 /*
   2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
   3  *
   4  * Author:
   5  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
   6  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
   7  *
   8  * This is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #ifndef __DMA_FSLDMA_H
  15 #define __DMA_FSLDMA_H
  16
  17 #include <linux/device.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/dmaengine.h>
  20
  21 /* Define data structures needed by Freescale
  22  * MPC8540 and MPC8349 DMA controller.
  23  */
  24 #define FSL_DMA_MR_CS           0x00000001
  25 #define FSL_DMA_MR_CC           0x00000002
  26 #define FSL_DMA_MR_CA           0x00000008
  27 #define FSL_DMA_MR_EIE          0x00000040
  28 #define FSL_DMA_MR_XFE          0x00000020
  29 #define FSL_DMA_MR_EOLNIE       0x00000100
  30 #define FSL_DMA_MR_EOLSIE       0x00000080
  31 #define FSL_DMA_MR_EOSIE        0x00000200
  32 #define FSL_DMA_MR_CDSM         0x00000010
  33 #define FSL_DMA_MR_CTM          0x00000004
  34 #define FSL_DMA_MR_EMP_EN       0x00200000
  35 #define FSL_DMA_MR_EMS_EN       0x00040000
  36 #define FSL_DMA_MR_DAHE         0x00002000
  37 #define FSL_DMA_MR_SAHE         0x00001000
  38
  39 #define FSL_DMA_MR_SAHTS_MASK   0x0000C000
  40 #define FSL_DMA_MR_DAHTS_MASK   0x00030000
  41 #define FSL_DMA_MR_BWC_MASK     0x0f000000
  42
  43 /*
  44  * Bandwidth/pause control determines how many bytes a given
  45  * channel is allowed to transfer before the DMA engine pauses
  46  * the current channel and switches to the next channel
  47  */
  48 #define FSL_DMA_MR_BWC         0x0A000000
  49
  50 /* Special MR definition for MPC8349 */
  51 #define FSL_DMA_MR_EOTIE        0x00000080
  52 #define FSL_DMA_MR_PRC_RM       0x00000800
  53
  54 #define FSL_DMA_SR_CH           0x00000020
  55 #define FSL_DMA_SR_PE           0x00000010
  56 #define FSL_DMA_SR_CB           0x00000004
  57 #define FSL_DMA_SR_TE           0x00000080
  58 #define FSL_DMA_SR_EOSI         0x00000002
  59 #define FSL_DMA_SR_EOLSI        0x00000001
  60 #define FSL_DMA_SR_EOCDI        0x00000001
  61 #define FSL_DMA_SR_EOLNI        0x00000008
  62
  63 #define FSL_DMA_SATR_SBPATMU                    0x20000000
  64 #define FSL_DMA_SATR_STRANSINT_RIO              0x00c00000
  65 #define FSL_DMA_SATR_SREADTYPE_SNOOP_READ       0x00050000
  66 #define FSL_DMA_SATR_SREADTYPE_BP_IORH          0x00020000
  67 #define FSL_DMA_SATR_SREADTYPE_BP_NREAD         0x00040000
  68 #define FSL_DMA_SATR_SREADTYPE_BP_MREAD         0x00070000
  69
  70 #define FSL_DMA_DATR_DBPATMU                    0x20000000
  71 #define FSL_DMA_DATR_DTRANSINT_RIO              0x00c00000
  72 #define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE     0x00050000
  73 #define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH        0x00010000
  74
  75 #define FSL_DMA_EOL             ((u64)0x1)
  76 #define FSL_DMA_SNEN            ((u64)0x10)
  77 #define FSL_DMA_EOSIE           0x8
  78 #define FSL_DMA_NLDA_MASK       (~(u64)0x1f)
  79
  80 #define FSL_DMA_BCR_MAX_CNT     0x03ffffffu
  81
  82 #define FSL_DMA_DGSR_TE         0x80
  83 #define FSL_DMA_DGSR_CH         0x20
  84 #define FSL_DMA_DGSR_PE         0x10
  85 #define FSL_DMA_DGSR_EOLNI      0x08
  86 #define FSL_DMA_DGSR_CB         0x04
  87 #define FSL_DMA_DGSR_EOSI       0x02
  88 #define FSL_DMA_DGSR_EOLSI      0x01
  89
  90 #define FSL_DMA_BUSWIDTHS       (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  91                                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  92                                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  93                                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
  94 typedef u64 __bitwise v64;
  95 typedef u32 __bitwise v32;
  96
  97 struct fsl_dma_ld_hw {
  98         v64 src_addr;
  99         v64 dst_addr;
 100         v64 next_ln_addr;
 101         v32 count;
 102         v32 reserve;
 103 } __attribute__((aligned(32)));
 104
 105 struct fsl_desc_sw {
 106         struct fsl_dma_ld_hw hw;
 107         struct list_head node;
 108         struct list_head tx_list;
 109         struct dma_async_tx_descriptor async_tx;
 110 } __attribute__((aligned(32)));
 111
 112 struct fsldma_chan_regs {
 113         u32 mr;         /* 0x00 - Mode Register */
 114         u32 sr;         /* 0x04 - Status Register */
 115         u64 cdar;       /* 0x08 - Current descriptor address register */
 116         u64 sar;        /* 0x10 - Source Address Register */
 117         u64 dar;        /* 0x18 - Destination Address Register */
 118         u32 bcr;        /* 0x20 - Byte Count Register */
 119         u64 ndar;       /* 0x24 - Next Descriptor Address Register */
 120 };
 121
 122 struct fsldma_chan;
 123 #define FSL_DMA_MAX_CHANS_PER_DEVICE 8
 124
 125 struct fsldma_device {
 126         void __iomem *regs;     /* DGSR register base */
 127         struct device *dev;
 128         struct dma_device common;
 129         struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
 130         u32 feature;            /* The same as DMA channels */
 131         int irq;                /* Channel IRQ */
 132 };
 133
 134 /* Define macros for fsldma_chan->feature property */
 135 #define FSL_DMA_LITTLE_ENDIAN   0x00000000
 136 #define FSL_DMA_BIG_ENDIAN      0x00000001
 137
 138 #define FSL_DMA_IP_MASK         0x00000ff0
 139 #define FSL_DMA_IP_85XX         0x00000010
 140 #define FSL_DMA_IP_83XX         0x00000020
 141
 142 #define FSL_DMA_CHAN_PAUSE_EXT  0x00001000
 143 #define FSL_DMA_CHAN_START_EXT  0x00002000
 144
 145 #ifdef CONFIG_PM
 146 struct fsldma_chan_regs_save {
 147         u32 mr;
 148 };
 149
 150 enum fsldma_pm_state {
 151         RUNNING = 0,
 152         SUSPENDED,
 153 };
 154 #endif
 155
 156 struct fsldma_chan {
 157         char name[8];                   /* Channel name */
 158         struct fsldma_chan_regs __iomem *regs;
 159         spinlock_t desc_lock;           /* Descriptor operation lock */
 160         /*
 161          * Descriptors which are queued to run, but have not yet been
 162          * submitted to the hardware for execution
 163          */
 164         struct list_head ld_pending;
 165         /*
 166          * Descriptors which are currently being executed by the hardware
 167          */
 168         struct list_head ld_running;
 169         /*
 170          * Descriptors which have finished execution by the hardware. These
 171          * descriptors have already had their cleanup actions run. They are
 172          * waiting for the ACK bit to be set by the async_tx API.
 173          */
 174         struct list_head ld_completed;  /* Link descriptors queue */
 175         struct dma_chan common;         /* DMA common channel */
 176         struct dma_pool *desc_pool;     /* Descriptors pool */
 177         struct device *dev;             /* Channel device */
 178         int irq;                        /* Channel IRQ */
 179         int id;                         /* Raw id of this channel */
 180         struct tasklet_struct tasklet;
 181         u32 feature;
 182         bool idle;                      /* DMA controller is idle */
 183 #ifdef CONFIG_PM
 184         struct fsldma_chan_regs_save regs_save;
 185         enum fsldma_pm_state pm_state;
 186 #endif
 187
 188         void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
 189         void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
 190         void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
 191         void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
 192         void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
 193 };
 194
 195 #define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
 196 #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
 197 #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
 198
 199 #ifndef __powerpc64__
 200 static u64 in_be64(const u64 __iomem *addr)
 201 {
 202         return ((u64)in_be32((u32 __iomem *)addr) << 32) |
 203                 (in_be32((u32 __iomem *)addr + 1));
 204 }
 205
 206 static void out_be64(u64 __iomem *addr, u64 val)
 207 {
 208         out_be32((u32 __iomem *)addr, val >> 32);
 209         out_be32((u32 __iomem *)addr + 1, (u32)val);
 210 }
 211
 212 /* There is no asm instructions for 64 bits reverse loads and stores */
 213 static u64 in_le64(const u64 __iomem *addr)
 214 {
 215         return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
 216                 (in_le32((u32 __iomem *)addr));
 217 }
 218
 219 static void out_le64(u64 __iomem *addr, u64 val)
 220 {
 221         out_le32((u32 __iomem *)addr + 1, val >> 32);
 222         out_le32((u32 __iomem *)addr, (u32)val);
 223 }
 224 #endif
 225
 226 #define DMA_IN(fsl_chan, addr, width)                                   \
 227                 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?           \
 228                         in_be##width(addr) : in_le##width(addr))
 229 #define DMA_OUT(fsl_chan, addr, val, width)                             \
 230                 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?           \
 231                         out_be##width(addr, val) : out_le##width(addr, val))
 232
 233 #define DMA_TO_CPU(fsl_chan, d, width)                                  \
 234                 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?           \
 235                         be##width##_to_cpu((__force __be##width)(v##width)d) : \
 236                         le##width##_to_cpu((__force __le##width)(v##width)d))
 237 #define CPU_TO_DMA(fsl_chan, c, width)                                  \
 238                 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?           \
 239                         (__force v##width)cpu_to_be##width(c) :         \
 240                         (__force v##width)cpu_to_le##width(c))
 241
 242 #endif  /* __DMA_FSLDMA_H */