drivers/ide/cmd64x.c

   1 /*
   2  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
   3  *           Due to massive hardware bugs, UltraDMA is only supported
   4  *           on the 646U2 and not on the 646U.
   5  *
   6  * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
   7  * Copyright (C) 1998           David S. Miller (davem@redhat.com)
   8  *
   9  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
  10  * Copyright (C) 2007-2010      Bartlomiej Zolnierkiewicz
  11  * Copyright (C) 2007,2009      MontaVista Software, Inc. <source@mvista.com>
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/types.h>
  16 #include <linux/pci.h>
  17 #include <linux/ide.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/io.h>
  21
  22 #define DRV_NAME "cmd64x"
  23
  24 /*
  25  * CMD64x specific registers definition.
  26  */
  27 #define CFR             0x50
  28 #define   CFR_INTR_CH0          0x04
  29
  30 #define CMDTIM          0x52
  31 #define ARTTIM0         0x53
  32 #define DRWTIM0         0x54
  33 #define ARTTIM1         0x55
  34 #define DRWTIM1         0x56
  35 #define ARTTIM23        0x57
  36 #define   ARTTIM23_DIS_RA2      0x04
  37 #define   ARTTIM23_DIS_RA3      0x08
  38 #define   ARTTIM23_INTR_CH1     0x10
  39 #define DRWTIM2         0x58
  40 #define BRST            0x59
  41 #define DRWTIM3         0x5b
  42
  43 #define BMIDECR0        0x70
  44 #define MRDMODE         0x71
  45 #define   MRDMODE_INTR_CH0      0x04
  46 #define   MRDMODE_INTR_CH1      0x08
  47 #define UDIDETCR0       0x73
  48 #define DTPR0           0x74
  49 #define BMIDECR1        0x78
  50 #define BMIDECSR        0x79
  51 #define UDIDETCR1       0x7B
  52 #define DTPR1           0x7C
  53
  54 static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
  55 {
  56         ide_hwif_t *hwif = drive->hwif;
  57         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  58         int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  59         const unsigned long T = 1000000 / bus_speed;
  60         static const u8 recovery_values[] =
  61                 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
  62         static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
  63         static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
  64         static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
  65         struct ide_timing t;
  66         u8 arttim = 0;
  67
  68         if (drive->dn >= ARRAY_SIZE(drwtim_regs))
  69                 return;
  70
  71         ide_timing_compute(drive, mode, &t, T, 0);
  72
  73         /*
  74          * In case we've got too long recovery phase, try to lengthen
  75          * the active phase
  76          */
  77         if (t.recover > 16) {
  78                 t.active += t.recover - 16;
  79                 t.recover = 16;
  80         }
  81         if (t.active > 16)              /* shouldn't actually happen... */
  82                 t.active = 16;
  83
  84         /*
  85          * Convert values to internal chipset representation
  86          */
  87         t.recover = recovery_values[t.recover];
  88         t.active &= 0x0f;
  89
  90         /* Program the active/recovery counts into the DRWTIM register */
  91         pci_write_config_byte(dev, drwtim_regs[drive->dn],
  92                               (t.active << 4) | t.recover);
  93
  94         /*
  95          * The primary channel has individual address setup timing registers
  96          * for each drive and the hardware selects the slowest timing itself.
  97          * The secondary channel has one common register and we have to select
  98          * the slowest address setup timing ourselves.
  99          */
 100         if (hwif->channel) {
 101                 ide_drive_t *pair = ide_get_pair_dev(drive);
 102
 103                 if (pair) {
 104                         struct ide_timing tp;
 105
 106                         ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
 107                         ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
 108                         if (pair->dma_mode) {
 109                                 ide_timing_compute(pair, pair->dma_mode,
 110                                                 &tp, T, 0);
 111                                 ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
 112                         }
 113                 }
 114         }
 115
 116         if (t.setup > 5)                /* shouldn't actually happen... */
 117                 t.setup = 5;
 118
 119         /*
 120          * Program the address setup clocks into the ARTTIM registers.
 121          * Avoid clearing the secondary channel's interrupt bit.
 122          */
 123         (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
 124         if (hwif->channel)
 125                 arttim &= ~ARTTIM23_INTR_CH1;
 126         arttim &= ~0xc0;
 127         arttim |= setup_values[t.setup];
 128         (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
 129 }
 130
 131 /*
 132  * Attempts to set drive's PIO mode.
 133  * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 134  */
 135
 136 static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 137 {
 138         const u8 pio = drive->pio_mode - XFER_PIO_0;
 139
 140         /*
 141          * Filter out the prefetch control values
 142          * to prevent PIO5 from being programmed
 143          */
 144         if (pio == 8 || pio == 9)
 145                 return;
 146
 147         cmd64x_program_timings(drive, XFER_PIO_0 + pio);
 148 }
 149
 150 static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 151 {
 152         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 153         u8 unit                 = drive->dn & 0x01;
 154         u8 regU = 0, pciU       = hwif->channel ? UDIDETCR1 : UDIDETCR0;
 155         const u8 speed          = drive->dma_mode;
 156
 157         pci_read_config_byte(dev, pciU, &regU);
 158         regU &= ~(unit ? 0xCA : 0x35);
 159
 160         switch(speed) {
 161         case XFER_UDMA_5:
 162                 regU |= unit ? 0x0A : 0x05;
 163                 break;
 164         case XFER_UDMA_4:
 165                 regU |= unit ? 0x4A : 0x15;
 166                 break;
 167         case XFER_UDMA_3:
 168                 regU |= unit ? 0x8A : 0x25;
 169                 break;
 170         case XFER_UDMA_2:
 171                 regU |= unit ? 0x42 : 0x11;
 172                 break;
 173         case XFER_UDMA_1:
 174                 regU |= unit ? 0x82 : 0x21;
 175                 break;
 176         case XFER_UDMA_0:
 177                 regU |= unit ? 0xC2 : 0x31;
 178                 break;
 179         case XFER_MW_DMA_2:
 180         case XFER_MW_DMA_1:
 181         case XFER_MW_DMA_0:
 182                 cmd64x_program_timings(drive, speed);
 183                 break;
 184         }
 185
 186         pci_write_config_byte(dev, pciU, regU);
 187 }
 188
 189 static void cmd648_clear_irq(ide_drive_t *drive)
 190 {
 191         ide_hwif_t *hwif        = drive->hwif;
 192         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 193         unsigned long base      = pci_resource_start(dev, 4);
 194         u8  irq_mask            = hwif->channel ? MRDMODE_INTR_CH1 :
 195                                                   MRDMODE_INTR_CH0;
 196         u8  mrdmode             = inb(base + 1);
 197
 198         /* clear the interrupt bit */
 199         outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
 200              base + 1);
 201 }
 202
 203 static void cmd64x_clear_irq(ide_drive_t *drive)
 204 {
 205         ide_hwif_t *hwif        = drive->hwif;
 206         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 207         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 208         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 209                                                   CFR_INTR_CH0;
 210         u8  irq_stat            = 0;
 211
 212         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 213         /* clear the interrupt bit */
 214         (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
 215 }
 216
 217 static int cmd648_test_irq(ide_hwif_t *hwif)
 218 {
 219         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 220         unsigned long base      = pci_resource_start(dev, 4);
 221         u8 irq_mask             = hwif->channel ? MRDMODE_INTR_CH1 :
 222                                                   MRDMODE_INTR_CH0;
 223         u8 mrdmode              = inb(base + 1);
 224
 225         pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
 226                  hwif->name, mrdmode, irq_mask);
 227
 228         return (mrdmode & irq_mask) ? 1 : 0;
 229 }
 230
 231 static int cmd64x_test_irq(ide_hwif_t *hwif)
 232 {
 233         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 234         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 235         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 236                                                   CFR_INTR_CH0;
 237         u8  irq_stat            = 0;
 238
 239         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 240
 241         pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
 242                  hwif->name, irq_stat, irq_mask);
 243
 244         return (irq_stat & irq_mask) ? 1 : 0;
 245 }
 246
 247 /*
 248  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 249  * event order for DMA transfers.
 250  */
 251
 252 static int cmd646_1_dma_end(ide_drive_t *drive)
 253 {
 254         ide_hwif_t *hwif = drive->hwif;
 255         u8 dma_stat = 0, dma_cmd = 0;
 256
 257         /* get DMA status */
 258         dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 259         /* read DMA command state */
 260         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 261         /* stop DMA */
 262         outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
 263         /* clear the INTR & ERROR bits */
 264         outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
 265         /* verify good DMA status */
 266         return (dma_stat & 7) != 4;
 267 }
 268
 269 static int init_chipset_cmd64x(struct pci_dev *dev)
 270 {
 271         u8 mrdmode = 0;
 272
 273         /* Set a good latency timer and cache line size value. */
 274         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 275         /* FIXME: pci_set_master() to ensure a good latency timer value */
 276
 277         /*
 278          * Enable interrupts, select MEMORY READ LINE for reads.
 279          *
 280          * NOTE: although not mentioned in the PCI0646U specs,
 281          * bits 0-1 are write only and won't be read back as
 282          * set or not -- PCI0646U2 specs clarify this point.
 283          */
 284         (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
 285         mrdmode &= ~0x30;
 286         (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
 287
 288         return 0;
 289 }
 290
 291 static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
 292 {
 293         struct pci_dev  *dev    = to_pci_dev(hwif->dev);
 294         u8 bmidecsr = 0, mask   = hwif->channel ? 0x02 : 0x01;
 295
 296         switch (dev->device) {
 297         case PCI_DEVICE_ID_CMD_648:
 298         case PCI_DEVICE_ID_CMD_649:
 299                 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
 300                 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 301         default:
 302                 return ATA_CBL_PATA40;
 303         }
 304 }
 305
 306 static const struct ide_port_ops cmd64x_port_ops = {
 307         .set_pio_mode           = cmd64x_set_pio_mode,
 308         .set_dma_mode           = cmd64x_set_dma_mode,
 309         .clear_irq              = cmd64x_clear_irq,
 310         .test_irq               = cmd64x_test_irq,
 311         .cable_detect           = cmd64x_cable_detect,
 312 };
 313
 314 static const struct ide_port_ops cmd648_port_ops = {
 315         .set_pio_mode           = cmd64x_set_pio_mode,
 316         .set_dma_mode           = cmd64x_set_dma_mode,
 317         .clear_irq              = cmd648_clear_irq,
 318         .test_irq               = cmd648_test_irq,
 319         .cable_detect           = cmd64x_cable_detect,
 320 };
 321
 322 static const struct ide_dma_ops cmd646_rev1_dma_ops = {
 323         .dma_host_set           = ide_dma_host_set,
 324         .dma_setup              = ide_dma_setup,
 325         .dma_start              = ide_dma_start,
 326         .dma_end                = cmd646_1_dma_end,
 327         .dma_test_irq           = ide_dma_test_irq,
 328         .dma_lost_irq           = ide_dma_lost_irq,
 329         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 330         .dma_sff_read_status    = ide_dma_sff_read_status,
 331 };
 332
 333 static const struct ide_port_info cmd64x_chipsets[] = {
 334         {       /* 0: CMD643 */
 335                 .name           = DRV_NAME,
 336                 .init_chipset   = init_chipset_cmd64x,
 337                 .enablebits     = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
 338                 .port_ops       = &cmd64x_port_ops,
 339                 .host_flags     = IDE_HFLAG_CLEAR_SIMPLEX |
 340                                   IDE_HFLAG_ABUSE_PREFETCH |
 341                                   IDE_HFLAG_SERIALIZE,
 342                 .pio_mask       = ATA_PIO5,
 343                 .mwdma_mask     = ATA_MWDMA2,
 344                 .udma_mask      = 0x00, /* no udma */
 345         },
 346         {       /* 1: CMD646 */
 347                 .name           = DRV_NAME,
 348                 .init_chipset   = init_chipset_cmd64x,
 349                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 350                 .port_ops       = &cmd648_port_ops,
 351                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH |
 352                                   IDE_HFLAG_SERIALIZE,
 353                 .pio_mask       = ATA_PIO5,
 354                 .mwdma_mask     = ATA_MWDMA2,
 355                 .udma_mask      = ATA_UDMA2,
 356         },
 357         {       /* 2: CMD648 */
 358                 .name           = DRV_NAME,
 359                 .init_chipset   = init_chipset_cmd64x,
 360                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 361                 .port_ops       = &cmd648_port_ops,
 362                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH,
 363                 .pio_mask       = ATA_PIO5,
 364                 .mwdma_mask     = ATA_MWDMA2,
 365                 .udma_mask      = ATA_UDMA4,
 366         },
 367         {       /* 3: CMD649 */
 368                 .name           = DRV_NAME,
 369                 .init_chipset   = init_chipset_cmd64x,
 370                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 371                 .port_ops       = &cmd648_port_ops,
 372                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH,
 373                 .pio_mask       = ATA_PIO5,
 374                 .mwdma_mask     = ATA_MWDMA2,
 375                 .udma_mask      = ATA_UDMA5,
 376         }
 377 };
 378
 379 static int cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 380 {
 381         struct ide_port_info d;
 382         u8 idx = id->driver_data;
 383
 384         d = cmd64x_chipsets[idx];
 385
 386         if (idx == 1) {
 387                 /*
 388                  * UltraDMA only supported on PCI646U and PCI646U2, which
 389                  * correspond to revisions 0x03, 0x05 and 0x07 respectively.
 390                  * Actually, although the CMD tech support people won't
 391                  * tell me the details, the 0x03 revision cannot support
 392                  * UDMA correctly without hardware modifications, and even
 393                  * then it only works with Quantum disks due to some
 394                  * hold time assumptions in the 646U part which are fixed
 395                  * in the 646U2.
 396                  *
 397                  * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
 398                  */
 399                 if (dev->revision < 5) {
 400                         d.udma_mask = 0x00;
 401                         /*
 402                          * The original PCI0646 didn't have the primary
 403                          * channel enable bit, it appeared starting with
 404                          * PCI0646U (i.e. revision ID 3).
 405                          */
 406                         if (dev->revision < 3) {
 407                                 d.enablebits[0].reg = 0;
 408                                 d.port_ops = &cmd64x_port_ops;
 409                                 if (dev->revision == 1)
 410                                         d.dma_ops = &cmd646_rev1_dma_ops;
 411                         }
 412                 }
 413         }
 414
 415         return ide_pci_init_one(dev, &d, NULL);
 416 }
 417
 418 static const struct pci_device_id cmd64x_pci_tbl[] = {
 419         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
 420         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
 421         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
 422         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
 423         { 0, },
 424 };
 425 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
 426
 427 static struct pci_driver cmd64x_pci_driver = {
 428         .name           = "CMD64x_IDE",
 429         .id_table       = cmd64x_pci_tbl,
 430         .probe          = cmd64x_init_one,
 431         .remove         = ide_pci_remove,
 432         .suspend        = ide_pci_suspend,
 433         .resume         = ide_pci_resume,
 434 };
 435
 436 static int __init cmd64x_ide_init(void)
 437 {
 438         return ide_pci_register_driver(&cmd64x_pci_driver);
 439 }
 440
 441 static void __exit cmd64x_ide_exit(void)
 442 {
 443         pci_unregister_driver(&cmd64x_pci_driver);
 444 }
 445
 446 module_init(cmd64x_ide_init);
 447 module_exit(cmd64x_ide_exit);
 448
 449 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
 450 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
 451 MODULE_LICENSE("GPL");