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thermal/drivers/hisi: Set the thermal zone private data to the sensor pointer
[linux/fpc-iii.git] / drivers / gpu / ipu-v3 / ipu-common.c
blob474b00e19697d90e7a60ee60fb8f8badd330f81e
1 /*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
31 #include <linux/of_graph.h>
32
33 #include <drm/drm_fourcc.h>
34
35 #include <video/imx-ipu-v3.h>
36 #include "ipu-prv.h"
37
38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
39 {
40 return readl(ipu->cm_reg + offset);
41 }
42
43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
44 {
45 writel(value, ipu->cm_reg + offset);
46 }
47
48 int ipu_get_num(struct ipu_soc *ipu)
49 {
50 return ipu->id;
51 }
52 EXPORT_SYMBOL_GPL(ipu_get_num);
53
54 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
55 {
56 u32 val;
57
58 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
59 val &= ~DP_S_SRM_MODE_MASK;
60 val |= sync ? DP_S_SRM_MODE_NEXT_FRAME :
61 DP_S_SRM_MODE_NOW;
62 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
63 }
64 EXPORT_SYMBOL_GPL(ipu_srm_dp_update);
65
66 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
67 {
68 switch (drm_fourcc) {
69 case DRM_FORMAT_ARGB1555:
70 case DRM_FORMAT_ABGR1555:
71 case DRM_FORMAT_RGBA5551:
72 case DRM_FORMAT_BGRA5551:
73 case DRM_FORMAT_RGB565:
74 case DRM_FORMAT_BGR565:
75 case DRM_FORMAT_RGB888:
76 case DRM_FORMAT_BGR888:
77 case DRM_FORMAT_ARGB4444:
78 case DRM_FORMAT_XRGB8888:
79 case DRM_FORMAT_XBGR8888:
80 case DRM_FORMAT_RGBX8888:
81 case DRM_FORMAT_BGRX8888:
82 case DRM_FORMAT_ARGB8888:
83 case DRM_FORMAT_ABGR8888:
84 case DRM_FORMAT_RGBA8888:
85 case DRM_FORMAT_BGRA8888:
86 case DRM_FORMAT_RGB565_A8:
87 case DRM_FORMAT_BGR565_A8:
88 case DRM_FORMAT_RGB888_A8:
89 case DRM_FORMAT_BGR888_A8:
90 case DRM_FORMAT_RGBX8888_A8:
91 case DRM_FORMAT_BGRX8888_A8:
92 return IPUV3_COLORSPACE_RGB;
93 case DRM_FORMAT_YUYV:
94 case DRM_FORMAT_UYVY:
95 case DRM_FORMAT_YUV420:
96 case DRM_FORMAT_YVU420:
97 case DRM_FORMAT_YUV422:
98 case DRM_FORMAT_YVU422:
99 case DRM_FORMAT_YUV444:
100 case DRM_FORMAT_YVU444:
101 case DRM_FORMAT_NV12:
102 case DRM_FORMAT_NV21:
103 case DRM_FORMAT_NV16:
104 case DRM_FORMAT_NV61:
105 return IPUV3_COLORSPACE_YUV;
106 default:
107 return IPUV3_COLORSPACE_UNKNOWN;
108 }
109 }
110 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
111
112 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
113 {
114 switch (pixelformat) {
115 case V4L2_PIX_FMT_YUV420:
116 case V4L2_PIX_FMT_YVU420:
117 case V4L2_PIX_FMT_YUV422P:
118 case V4L2_PIX_FMT_UYVY:
119 case V4L2_PIX_FMT_YUYV:
120 case V4L2_PIX_FMT_NV12:
121 case V4L2_PIX_FMT_NV21:
122 case V4L2_PIX_FMT_NV16:
123 case V4L2_PIX_FMT_NV61:
124 return IPUV3_COLORSPACE_YUV;
125 case V4L2_PIX_FMT_XRGB32:
126 case V4L2_PIX_FMT_XBGR32:
127 case V4L2_PIX_FMT_RGB32:
128 case V4L2_PIX_FMT_BGR32:
129 case V4L2_PIX_FMT_RGB24:
130 case V4L2_PIX_FMT_BGR24:
131 case V4L2_PIX_FMT_RGB565:
132 return IPUV3_COLORSPACE_RGB;
133 default:
134 return IPUV3_COLORSPACE_UNKNOWN;
135 }
136 }
137 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
138
139 bool ipu_pixelformat_is_planar(u32 pixelformat)
140 {
141 switch (pixelformat) {
142 case V4L2_PIX_FMT_YUV420:
143 case V4L2_PIX_FMT_YVU420:
144 case V4L2_PIX_FMT_YUV422P:
145 case V4L2_PIX_FMT_NV12:
146 case V4L2_PIX_FMT_NV21:
147 case V4L2_PIX_FMT_NV16:
148 case V4L2_PIX_FMT_NV61:
149 return true;
150 }
151
152 return false;
153 }
154 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
155
156 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
157 {
158 switch (mbus_code & 0xf000) {
159 case 0x1000:
160 return IPUV3_COLORSPACE_RGB;
161 case 0x2000:
162 return IPUV3_COLORSPACE_YUV;
163 default:
164 return IPUV3_COLORSPACE_UNKNOWN;
165 }
166 }
167 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
168
169 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
170 {
171 switch (pixelformat) {
172 case V4L2_PIX_FMT_YUV420:
173 case V4L2_PIX_FMT_YVU420:
174 case V4L2_PIX_FMT_YUV422P:
175 case V4L2_PIX_FMT_NV12:
176 case V4L2_PIX_FMT_NV21:
177 case V4L2_PIX_FMT_NV16:
178 case V4L2_PIX_FMT_NV61:
179 /*
180 * for the planar YUV formats, the stride passed to
181 * cpmem must be the stride in bytes of the Y plane.
182 * And all the planar YUV formats have an 8-bit
183 * Y component.
184 */
185 return (8 * pixel_stride) >> 3;
186 case V4L2_PIX_FMT_RGB565:
187 case V4L2_PIX_FMT_YUYV:
188 case V4L2_PIX_FMT_UYVY:
189 return (16 * pixel_stride) >> 3;
190 case V4L2_PIX_FMT_BGR24:
191 case V4L2_PIX_FMT_RGB24:
192 return (24 * pixel_stride) >> 3;
193 case V4L2_PIX_FMT_BGR32:
194 case V4L2_PIX_FMT_RGB32:
195 case V4L2_PIX_FMT_XBGR32:
196 case V4L2_PIX_FMT_XRGB32:
197 return (32 * pixel_stride) >> 3;
198 default:
199 break;
200 }
201
202 return -EINVAL;
203 }
204 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
205
206 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
207 bool hflip, bool vflip)
208 {
209 u32 r90, vf, hf;
210
211 switch (degrees) {
212 case 0:
213 vf = hf = r90 = 0;
214 break;
215 case 90:
216 vf = hf = 0;
217 r90 = 1;
218 break;
219 case 180:
220 vf = hf = 1;
221 r90 = 0;
222 break;
223 case 270:
224 vf = hf = r90 = 1;
225 break;
226 default:
227 return -EINVAL;
228 }
229
230 hf ^= (u32)hflip;
231 vf ^= (u32)vflip;
232
233 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
234 return 0;
235 }
236 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
237
238 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
239 bool hflip, bool vflip)
240 {
241 u32 r90, vf, hf;
242
243 r90 = ((u32)mode >> 2) & 0x1;
244 hf = ((u32)mode >> 1) & 0x1;
245 vf = ((u32)mode >> 0) & 0x1;
246 hf ^= (u32)hflip;
247 vf ^= (u32)vflip;
248
249 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
250 case IPU_ROTATE_NONE:
251 *degrees = 0;
252 break;
253 case IPU_ROTATE_90_RIGHT:
254 *degrees = 90;
255 break;
256 case IPU_ROTATE_180:
257 *degrees = 180;
258 break;
259 case IPU_ROTATE_90_LEFT:
260 *degrees = 270;
261 break;
262 default:
263 return -EINVAL;
264 }
265
266 return 0;
267 }
268 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
269
270 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
271 {
272 struct ipuv3_channel *channel;
273
274 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
275
276 if (num > 63)
277 return ERR_PTR(-ENODEV);
278
279 mutex_lock(&ipu->channel_lock);
280
281 list_for_each_entry(channel, &ipu->channels, list) {
282 if (channel->num == num) {
283 channel = ERR_PTR(-EBUSY);
284 goto out;
285 }
286 }
287
288 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
289 if (!channel) {
290 channel = ERR_PTR(-ENOMEM);
291 goto out;
292 }
293
294 channel->num = num;
295 channel->ipu = ipu;
296 list_add(&channel->list, &ipu->channels);
297
298 out:
299 mutex_unlock(&ipu->channel_lock);
300
301 return channel;
302 }
303 EXPORT_SYMBOL_GPL(ipu_idmac_get);
304
305 void ipu_idmac_put(struct ipuv3_channel *channel)
306 {
307 struct ipu_soc *ipu = channel->ipu;
308
309 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
310
311 mutex_lock(&ipu->channel_lock);
312
313 list_del(&channel->list);
314 kfree(channel);
315
316 mutex_unlock(&ipu->channel_lock);
317 }
318 EXPORT_SYMBOL_GPL(ipu_idmac_put);
319
320 #define idma_mask(ch) (1 << ((ch) & 0x1f))
321
322 /*
323 * This is an undocumented feature, a write one to a channel bit in
324 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
325 * internal current buffer pointer so that transfers start from buffer
326 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
327 * only says these are read-only registers). This operation is required
328 * for channel linking to work correctly, for instance video capture
329 * pipelines that carry out image rotations will fail after the first
330 * streaming unless this function is called for each channel before
331 * re-enabling the channels.
332 */
333 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
334 {
335 struct ipu_soc *ipu = channel->ipu;
336 unsigned int chno = channel->num;
337
338 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
339 }
340
341 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
342 bool doublebuffer)
343 {
344 struct ipu_soc *ipu = channel->ipu;
345 unsigned long flags;
346 u32 reg;
347
348 spin_lock_irqsave(&ipu->lock, flags);
349
350 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
351 if (doublebuffer)
352 reg |= idma_mask(channel->num);
353 else
354 reg &= ~idma_mask(channel->num);
355 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
356
357 __ipu_idmac_reset_current_buffer(channel);
358
359 spin_unlock_irqrestore(&ipu->lock, flags);
360 }
361 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
362
363 static const struct {
364 int chnum;
365 u32 reg;
366 int shift;
367 } idmac_lock_en_info[] = {
368 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
369 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
370 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
371 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
372 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
373 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
374 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
375 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
376 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
377 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
378 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
379 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
380 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
381 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
382 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
383 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
384 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
385 };
386
387 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
388 {
389 struct ipu_soc *ipu = channel->ipu;
390 unsigned long flags;
391 u32 bursts, regval;
392 int i;
393
394 switch (num_bursts) {
395 case 0:
396 case 1:
397 bursts = 0x00; /* locking disabled */
398 break;
399 case 2:
400 bursts = 0x01;
401 break;
402 case 4:
403 bursts = 0x02;
404 break;
405 case 8:
406 bursts = 0x03;
407 break;
408 default:
409 return -EINVAL;
410 }
411
412 /*
413 * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
414 * i.MX53 channel arbitration locking doesn't seem to work properly.
415 * Allow enabling the lock feature on IPUv3H / i.MX6 only.
416 */
417 if (bursts && ipu->ipu_type != IPUV3H)
418 return -EINVAL;
419
420 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
421 if (channel->num == idmac_lock_en_info[i].chnum)
422 break;
423 }
424 if (i >= ARRAY_SIZE(idmac_lock_en_info))
425 return -EINVAL;
426
427 spin_lock_irqsave(&ipu->lock, flags);
428
429 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
430 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
431 regval |= (bursts << idmac_lock_en_info[i].shift);
432 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
433
434 spin_unlock_irqrestore(&ipu->lock, flags);
435
436 return 0;
437 }
438 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
439
440 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
441 {
442 unsigned long lock_flags;
443 u32 val;
444
445 spin_lock_irqsave(&ipu->lock, lock_flags);
446
447 val = ipu_cm_read(ipu, IPU_DISP_GEN);
448
449 if (mask & IPU_CONF_DI0_EN)
450 val |= IPU_DI0_COUNTER_RELEASE;
451 if (mask & IPU_CONF_DI1_EN)
452 val |= IPU_DI1_COUNTER_RELEASE;
453
454 ipu_cm_write(ipu, val, IPU_DISP_GEN);
455
456 val = ipu_cm_read(ipu, IPU_CONF);
457 val |= mask;
458 ipu_cm_write(ipu, val, IPU_CONF);
459
460 spin_unlock_irqrestore(&ipu->lock, lock_flags);
461
462 return 0;
463 }
464 EXPORT_SYMBOL_GPL(ipu_module_enable);
465
466 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
467 {
468 unsigned long lock_flags;
469 u32 val;
470
471 spin_lock_irqsave(&ipu->lock, lock_flags);
472
473 val = ipu_cm_read(ipu, IPU_CONF);
474 val &= ~mask;
475 ipu_cm_write(ipu, val, IPU_CONF);
476
477 val = ipu_cm_read(ipu, IPU_DISP_GEN);
478
479 if (mask & IPU_CONF_DI0_EN)
480 val &= ~IPU_DI0_COUNTER_RELEASE;
481 if (mask & IPU_CONF_DI1_EN)
482 val &= ~IPU_DI1_COUNTER_RELEASE;
483
484 ipu_cm_write(ipu, val, IPU_DISP_GEN);
485
486 spin_unlock_irqrestore(&ipu->lock, lock_flags);
487
488 return 0;
489 }
490 EXPORT_SYMBOL_GPL(ipu_module_disable);
491
492 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
493 {
494 struct ipu_soc *ipu = channel->ipu;
495 unsigned int chno = channel->num;
496
497 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
498 }
499 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
500
501 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
502 {
503 struct ipu_soc *ipu = channel->ipu;
504 unsigned long flags;
505 u32 reg = 0;
506
507 spin_lock_irqsave(&ipu->lock, flags);
508 switch (buf_num) {
509 case 0:
510 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
511 break;
512 case 1:
513 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
514 break;
515 case 2:
516 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
517 break;
518 }
519 spin_unlock_irqrestore(&ipu->lock, flags);
520
521 return ((reg & idma_mask(channel->num)) != 0);
522 }
523 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
524
525 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
526 {
527 struct ipu_soc *ipu = channel->ipu;
528 unsigned int chno = channel->num;
529 unsigned long flags;
530
531 spin_lock_irqsave(&ipu->lock, flags);
532
533 /* Mark buffer as ready. */
534 if (buf_num == 0)
535 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
536 else
537 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
538
539 spin_unlock_irqrestore(&ipu->lock, flags);
540 }
541 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
542
543 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
544 {
545 struct ipu_soc *ipu = channel->ipu;
546 unsigned int chno = channel->num;
547 unsigned long flags;
548
549 spin_lock_irqsave(&ipu->lock, flags);
550
551 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
552 switch (buf_num) {
553 case 0:
554 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
555 break;
556 case 1:
557 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
558 break;
559 case 2:
560 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
561 break;
562 default:
563 break;
564 }
565 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
566
567 spin_unlock_irqrestore(&ipu->lock, flags);
568 }
569 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
570
571 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
572 {
573 struct ipu_soc *ipu = channel->ipu;
574 u32 val;
575 unsigned long flags;
576
577 spin_lock_irqsave(&ipu->lock, flags);
578
579 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
580 val |= idma_mask(channel->num);
581 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
582
583 spin_unlock_irqrestore(&ipu->lock, flags);
584
585 return 0;
586 }
587 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
588
589 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
590 {
591 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
592 }
593 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
594
595 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
596 {
597 struct ipu_soc *ipu = channel->ipu;
598 unsigned long timeout;
599
600 timeout = jiffies + msecs_to_jiffies(ms);
601 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
602 idma_mask(channel->num)) {
603 if (time_after(jiffies, timeout))
604 return -ETIMEDOUT;
605 cpu_relax();
606 }
607
608 return 0;
609 }
610 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
611
612 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
613 {
614 struct ipu_soc *ipu = channel->ipu;
615 u32 val;
616 unsigned long flags;
617
618 spin_lock_irqsave(&ipu->lock, flags);
619
620 /* Disable DMA channel(s) */
621 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
622 val &= ~idma_mask(channel->num);
623 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
624
625 __ipu_idmac_reset_current_buffer(channel);
626
627 /* Set channel buffers NOT to be ready */
628 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
629
630 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
631 idma_mask(channel->num)) {
632 ipu_cm_write(ipu, idma_mask(channel->num),
633 IPU_CHA_BUF0_RDY(channel->num));
634 }
635
636 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
637 idma_mask(channel->num)) {
638 ipu_cm_write(ipu, idma_mask(channel->num),
639 IPU_CHA_BUF1_RDY(channel->num));
640 }
641
642 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
643
644 /* Reset the double buffer */
645 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
646 val &= ~idma_mask(channel->num);
647 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
648
649 spin_unlock_irqrestore(&ipu->lock, flags);
650
651 return 0;
652 }
653 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
654
655 /*
656 * The imx6 rev. D TRM says that enabling the WM feature will increase
657 * a channel's priority. Refer to Table 36-8 Calculated priority value.
658 * The sub-module that is the sink or source for the channel must enable
659 * watermark signal for this to take effect (SMFC_WM for instance).
660 */
661 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
662 {
663 struct ipu_soc *ipu = channel->ipu;
664 unsigned long flags;
665 u32 val;
666
667 spin_lock_irqsave(&ipu->lock, flags);
668
669 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
670 if (enable)
671 val |= 1 << (channel->num % 32);
672 else
673 val &= ~(1 << (channel->num % 32));
674 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
675
676 spin_unlock_irqrestore(&ipu->lock, flags);
677 }
678 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
679
680 static int ipu_memory_reset(struct ipu_soc *ipu)
681 {
682 unsigned long timeout;
683
684 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
685
686 timeout = jiffies + msecs_to_jiffies(1000);
687 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
688 if (time_after(jiffies, timeout))
689 return -ETIME;
690 cpu_relax();
691 }
692
693 return 0;
694 }
695
696 /*
697 * Set the source mux for the given CSI. Selects either parallel or
698 * MIPI CSI2 sources.
699 */
700 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
701 {
702 unsigned long flags;
703 u32 val, mask;
704
705 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
706 IPU_CONF_CSI0_DATA_SOURCE;
707
708 spin_lock_irqsave(&ipu->lock, flags);
709
710 val = ipu_cm_read(ipu, IPU_CONF);
711 if (mipi_csi2)
712 val |= mask;
713 else
714 val &= ~mask;
715 ipu_cm_write(ipu, val, IPU_CONF);
716
717 spin_unlock_irqrestore(&ipu->lock, flags);
718 }
719 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
720
721 /*
722 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
723 */
724 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
725 {
726 unsigned long flags;
727 u32 val;
728
729 spin_lock_irqsave(&ipu->lock, flags);
730
731 val = ipu_cm_read(ipu, IPU_CONF);
732 if (vdi)
733 val |= IPU_CONF_IC_INPUT;
734 else
735 val &= ~IPU_CONF_IC_INPUT;
736
737 if (csi_id == 1)
738 val |= IPU_CONF_CSI_SEL;
739 else
740 val &= ~IPU_CONF_CSI_SEL;
741
742 ipu_cm_write(ipu, val, IPU_CONF);
743
744 spin_unlock_irqrestore(&ipu->lock, flags);
745 }
746 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
747
748
749 /* Frame Synchronization Unit Channel Linking */
750
751 struct fsu_link_reg_info {
752 int chno;
753 u32 reg;
754 u32 mask;
755 u32 val;
756 };
757
758 struct fsu_link_info {
759 struct fsu_link_reg_info src;
760 struct fsu_link_reg_info sink;
761 };
762
763 static const struct fsu_link_info fsu_link_info[] = {
764 {
765 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
766 FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
767 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
768 FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
769 }, {
770 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
771 FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
772 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
773 FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
774 }, {
775 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
776 FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
777 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
778 FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
779 }, {
780 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
781 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
782 FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
783 },
784 };
785
786 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
787 {
788 int i;
789
790 for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
791 if (src == fsu_link_info[i].src.chno &&
792 sink == fsu_link_info[i].sink.chno)
793 return &fsu_link_info[i];
794 }
795
796 return NULL;
797 }
798
799 /*
800 * Links a source channel to a sink channel in the FSU.
801 */
802 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
803 {
804 const struct fsu_link_info *link;
805 u32 src_reg, sink_reg;
806 unsigned long flags;
807
808 link = find_fsu_link_info(src_ch, sink_ch);
809 if (!link)
810 return -EINVAL;
811
812 spin_lock_irqsave(&ipu->lock, flags);
813
814 if (link->src.mask) {
815 src_reg = ipu_cm_read(ipu, link->src.reg);
816 src_reg &= ~link->src.mask;
817 src_reg |= link->src.val;
818 ipu_cm_write(ipu, src_reg, link->src.reg);
819 }
820
821 if (link->sink.mask) {
822 sink_reg = ipu_cm_read(ipu, link->sink.reg);
823 sink_reg &= ~link->sink.mask;
824 sink_reg |= link->sink.val;
825 ipu_cm_write(ipu, sink_reg, link->sink.reg);
826 }
827
828 spin_unlock_irqrestore(&ipu->lock, flags);
829 return 0;
830 }
831 EXPORT_SYMBOL_GPL(ipu_fsu_link);
832
833 /*
834 * Unlinks source and sink channels in the FSU.
835 */
836 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
837 {
838 const struct fsu_link_info *link;
839 u32 src_reg, sink_reg;
840 unsigned long flags;
841
842 link = find_fsu_link_info(src_ch, sink_ch);
843 if (!link)
844 return -EINVAL;
845
846 spin_lock_irqsave(&ipu->lock, flags);
847
848 if (link->src.mask) {
849 src_reg = ipu_cm_read(ipu, link->src.reg);
850 src_reg &= ~link->src.mask;
851 ipu_cm_write(ipu, src_reg, link->src.reg);
852 }
853
854 if (link->sink.mask) {
855 sink_reg = ipu_cm_read(ipu, link->sink.reg);
856 sink_reg &= ~link->sink.mask;
857 ipu_cm_write(ipu, sink_reg, link->sink.reg);
858 }
859
860 spin_unlock_irqrestore(&ipu->lock, flags);
861 return 0;
862 }
863 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
864
865 /* Link IDMAC channels in the FSU */
866 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
867 {
868 return ipu_fsu_link(src->ipu, src->num, sink->num);
869 }
870 EXPORT_SYMBOL_GPL(ipu_idmac_link);
871
872 /* Unlink IDMAC channels in the FSU */
873 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
874 {
875 return ipu_fsu_unlink(src->ipu, src->num, sink->num);
876 }
877 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
878
879 struct ipu_devtype {
880 const char *name;
881 unsigned long cm_ofs;
882 unsigned long cpmem_ofs;
883 unsigned long srm_ofs;
884 unsigned long tpm_ofs;
885 unsigned long csi0_ofs;
886 unsigned long csi1_ofs;
887 unsigned long ic_ofs;
888 unsigned long disp0_ofs;
889 unsigned long disp1_ofs;
890 unsigned long dc_tmpl_ofs;
891 unsigned long vdi_ofs;
892 enum ipuv3_type type;
893 };
894
895 static struct ipu_devtype ipu_type_imx51 = {
896 .name = "IPUv3EX",
897 .cm_ofs = 0x1e000000,
898 .cpmem_ofs = 0x1f000000,
899 .srm_ofs = 0x1f040000,
900 .tpm_ofs = 0x1f060000,
901 .csi0_ofs = 0x1f030000,
902 .csi1_ofs = 0x1f038000,
903 .ic_ofs = 0x1e020000,
904 .disp0_ofs = 0x1e040000,
905 .disp1_ofs = 0x1e048000,
906 .dc_tmpl_ofs = 0x1f080000,
907 .vdi_ofs = 0x1e068000,
908 .type = IPUV3EX,
909 };
910
911 static struct ipu_devtype ipu_type_imx53 = {
912 .name = "IPUv3M",
913 .cm_ofs = 0x06000000,
914 .cpmem_ofs = 0x07000000,
915 .srm_ofs = 0x07040000,
916 .tpm_ofs = 0x07060000,
917 .csi0_ofs = 0x07030000,
918 .csi1_ofs = 0x07038000,
919 .ic_ofs = 0x06020000,
920 .disp0_ofs = 0x06040000,
921 .disp1_ofs = 0x06048000,
922 .dc_tmpl_ofs = 0x07080000,
923 .vdi_ofs = 0x06068000,
924 .type = IPUV3M,
925 };
926
927 static struct ipu_devtype ipu_type_imx6q = {
928 .name = "IPUv3H",
929 .cm_ofs = 0x00200000,
930 .cpmem_ofs = 0x00300000,
931 .srm_ofs = 0x00340000,
932 .tpm_ofs = 0x00360000,
933 .csi0_ofs = 0x00230000,
934 .csi1_ofs = 0x00238000,
935 .ic_ofs = 0x00220000,
936 .disp0_ofs = 0x00240000,
937 .disp1_ofs = 0x00248000,
938 .dc_tmpl_ofs = 0x00380000,
939 .vdi_ofs = 0x00268000,
940 .type = IPUV3H,
941 };
942
943 static const struct of_device_id imx_ipu_dt_ids[] = {
944 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
945 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
946 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
947 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
948 { /* sentinel */ }
949 };
950 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
951
952 static int ipu_submodules_init(struct ipu_soc *ipu,
953 struct platform_device *pdev, unsigned long ipu_base,
954 struct clk *ipu_clk)
955 {
956 char *unit;
957 int ret;
958 struct device *dev = &pdev->dev;
959 const struct ipu_devtype *devtype = ipu->devtype;
960
961 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
962 if (ret) {
963 unit = "cpmem";
964 goto err_cpmem;
965 }
966
967 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
968 IPU_CONF_CSI0_EN, ipu_clk);
969 if (ret) {
970 unit = "csi0";
971 goto err_csi_0;
972 }
973
974 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
975 IPU_CONF_CSI1_EN, ipu_clk);
976 if (ret) {
977 unit = "csi1";
978 goto err_csi_1;
979 }
980
981 ret = ipu_ic_init(ipu, dev,
982 ipu_base + devtype->ic_ofs,
983 ipu_base + devtype->tpm_ofs);
984 if (ret) {
985 unit = "ic";
986 goto err_ic;
987 }
988
989 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
990 IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
991 IPU_CONF_IC_INPUT);
992 if (ret) {
993 unit = "vdi";
994 goto err_vdi;
995 }
996
997 ret = ipu_image_convert_init(ipu, dev);
998 if (ret) {
999 unit = "image_convert";
1000 goto err_image_convert;
1001 }
1002
1003 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
1004 IPU_CONF_DI0_EN, ipu_clk);
1005 if (ret) {
1006 unit = "di0";
1007 goto err_di_0;
1008 }
1009
1010 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
1011 IPU_CONF_DI1_EN, ipu_clk);
1012 if (ret) {
1013 unit = "di1";
1014 goto err_di_1;
1015 }
1016
1017 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
1018 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
1019 if (ret) {
1020 unit = "dc_template";
1021 goto err_dc;
1022 }
1023
1024 ret = ipu_dmfc_init(ipu, dev, ipu_base +
1025 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1026 if (ret) {
1027 unit = "dmfc";
1028 goto err_dmfc;
1029 }
1030
1031 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1032 if (ret) {
1033 unit = "dp";
1034 goto err_dp;
1035 }
1036
1037 ret = ipu_smfc_init(ipu, dev, ipu_base +
1038 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1039 if (ret) {
1040 unit = "smfc";
1041 goto err_smfc;
1042 }
1043
1044 return 0;
1045
1046 err_smfc:
1047 ipu_dp_exit(ipu);
1048 err_dp:
1049 ipu_dmfc_exit(ipu);
1050 err_dmfc:
1051 ipu_dc_exit(ipu);
1052 err_dc:
1053 ipu_di_exit(ipu, 1);
1054 err_di_1:
1055 ipu_di_exit(ipu, 0);
1056 err_di_0:
1057 ipu_image_convert_exit(ipu);
1058 err_image_convert:
1059 ipu_vdi_exit(ipu);
1060 err_vdi:
1061 ipu_ic_exit(ipu);
1062 err_ic:
1063 ipu_csi_exit(ipu, 1);
1064 err_csi_1:
1065 ipu_csi_exit(ipu, 0);
1066 err_csi_0:
1067 ipu_cpmem_exit(ipu);
1068 err_cpmem:
1069 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1070 return ret;
1071 }
1072
1073 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1074 {
1075 unsigned long status;
1076 int i, bit, irq;
1077
1078 for (i = 0; i < num_regs; i++) {
1079
1080 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1081 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1082
1083 for_each_set_bit(bit, &status, 32) {
1084 irq = irq_linear_revmap(ipu->domain,
1085 regs[i] * 32 + bit);
1086 if (irq)
1087 generic_handle_irq(irq);
1088 }
1089 }
1090 }
1091
1092 static void ipu_irq_handler(struct irq_desc *desc)
1093 {
1094 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1095 struct irq_chip *chip = irq_desc_get_chip(desc);
1096 static const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1097
1098 chained_irq_enter(chip, desc);
1099
1100 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1101
1102 chained_irq_exit(chip, desc);
1103 }
1104
1105 static void ipu_err_irq_handler(struct irq_desc *desc)
1106 {
1107 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1108 struct irq_chip *chip = irq_desc_get_chip(desc);
1109 static const int int_reg[] = { 4, 5, 8, 9};
1110
1111 chained_irq_enter(chip, desc);
1112
1113 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1114
1115 chained_irq_exit(chip, desc);
1116 }
1117
1118 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1119 {
1120 int virq;
1121
1122 virq = irq_linear_revmap(ipu->domain, irq);
1123 if (!virq)
1124 virq = irq_create_mapping(ipu->domain, irq);
1125
1126 return virq;
1127 }
1128 EXPORT_SYMBOL_GPL(ipu_map_irq);
1129
1130 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1131 enum ipu_channel_irq irq_type)
1132 {
1133 return ipu_map_irq(ipu, irq_type + channel->num);
1134 }
1135 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1136
1137 static void ipu_submodules_exit(struct ipu_soc *ipu)
1138 {
1139 ipu_smfc_exit(ipu);
1140 ipu_dp_exit(ipu);
1141 ipu_dmfc_exit(ipu);
1142 ipu_dc_exit(ipu);
1143 ipu_di_exit(ipu, 1);
1144 ipu_di_exit(ipu, 0);
1145 ipu_image_convert_exit(ipu);
1146 ipu_vdi_exit(ipu);
1147 ipu_ic_exit(ipu);
1148 ipu_csi_exit(ipu, 1);
1149 ipu_csi_exit(ipu, 0);
1150 ipu_cpmem_exit(ipu);
1151 }
1152
1153 static int platform_remove_devices_fn(struct device *dev, void *unused)
1154 {
1155 struct platform_device *pdev = to_platform_device(dev);
1156
1157 platform_device_unregister(pdev);
1158
1159 return 0;
1160 }
1161
1162 static void platform_device_unregister_children(struct platform_device *pdev)
1163 {
1164 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1165 }
1166
1167 struct ipu_platform_reg {
1168 struct ipu_client_platformdata pdata;
1169 const char *name;
1170 };
1171
1172 /* These must be in the order of the corresponding device tree port nodes */
1173 static struct ipu_platform_reg client_reg[] = {
1174 {
1175 .pdata = {
1176 .csi = 0,
1177 .dma[0] = IPUV3_CHANNEL_CSI0,
1178 .dma[1] = -EINVAL,
1179 },
1180 .name = "imx-ipuv3-csi",
1181 }, {
1182 .pdata = {
1183 .csi = 1,
1184 .dma[0] = IPUV3_CHANNEL_CSI1,
1185 .dma[1] = -EINVAL,
1186 },
1187 .name = "imx-ipuv3-csi",
1188 }, {
1189 .pdata = {
1190 .di = 0,
1191 .dc = 5,
1192 .dp = IPU_DP_FLOW_SYNC_BG,
1193 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1194 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1195 },
1196 .name = "imx-ipuv3-crtc",
1197 }, {
1198 .pdata = {
1199 .di = 1,
1200 .dc = 1,
1201 .dp = -EINVAL,
1202 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1203 .dma[1] = -EINVAL,
1204 },
1205 .name = "imx-ipuv3-crtc",
1206 },
1207 };
1208
1209 static DEFINE_MUTEX(ipu_client_id_mutex);
1210 static int ipu_client_id;
1211
1212 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1213 {
1214 struct device *dev = ipu->dev;
1215 unsigned i;
1216 int id, ret;
1217
1218 mutex_lock(&ipu_client_id_mutex);
1219 id = ipu_client_id;
1220 ipu_client_id += ARRAY_SIZE(client_reg);
1221 mutex_unlock(&ipu_client_id_mutex);
1222
1223 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1224 struct ipu_platform_reg *reg = &client_reg[i];
1225 struct platform_device *pdev;
1226 struct device_node *of_node;
1227
1228 /* Associate subdevice with the corresponding port node */
1229 of_node = of_graph_get_port_by_id(dev->of_node, i);
1230 if (!of_node) {
1231 dev_info(dev,
1232 "no port@%d node in %pOF, not using %s%d\n",
1233 i, dev->of_node,
1234 (i / 2) ? "DI" : "CSI", i % 2);
1235 continue;
1236 }
1237
1238 pdev = platform_device_alloc(reg->name, id++);
1239 if (!pdev) {
1240 ret = -ENOMEM;
1241 goto err_register;
1242 }
1243
1244 pdev->dev.parent = dev;
1245
1246 reg->pdata.of_node = of_node;
1247 ret = platform_device_add_data(pdev, &reg->pdata,
1248 sizeof(reg->pdata));
1249 if (!ret)
1250 ret = platform_device_add(pdev);
1251 if (ret) {
1252 platform_device_put(pdev);
1253 goto err_register;
1254 }
1255 }
1256
1257 return 0;
1258
1259 err_register:
1260 platform_device_unregister_children(to_platform_device(dev));
1261
1262 return ret;
1263 }
1264
1265
1266 static int ipu_irq_init(struct ipu_soc *ipu)
1267 {
1268 struct irq_chip_generic *gc;
1269 struct irq_chip_type *ct;
1270 unsigned long unused[IPU_NUM_IRQS / 32] = {
1271 0x400100d0, 0xffe000fd,
1272 0x400100d0, 0xffe000fd,
1273 0x400100d0, 0xffe000fd,
1274 0x4077ffff, 0xffe7e1fd,
1275 0x23fffffe, 0x8880fff0,
1276 0xf98fe7d0, 0xfff81fff,
1277 0x400100d0, 0xffe000fd,
1278 0x00000000,
1279 };
1280 int ret, i;
1281
1282 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1283 &irq_generic_chip_ops, ipu);
1284 if (!ipu->domain) {
1285 dev_err(ipu->dev, "failed to add irq domain\n");
1286 return -ENODEV;
1287 }
1288
1289 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1290 handle_level_irq, 0, 0, 0);
1291 if (ret < 0) {
1292 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1293 irq_domain_remove(ipu->domain);
1294 return ret;
1295 }
1296
1297 /* Mask and clear all interrupts */
1298 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1299 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1300 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
1301 }
1302
1303 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1304 gc = irq_get_domain_generic_chip(ipu->domain, i);
1305 gc->reg_base = ipu->cm_reg;
1306 gc->unused = unused[i / 32];
1307 ct = gc->chip_types;
1308 ct->chip.irq_ack = irq_gc_ack_set_bit;
1309 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1310 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1311 ct->regs.ack = IPU_INT_STAT(i / 32);
1312 ct->regs.mask = IPU_INT_CTRL(i / 32);
1313 }
1314
1315 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1316 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1317 ipu);
1318
1319 return 0;
1320 }
1321
1322 static void ipu_irq_exit(struct ipu_soc *ipu)
1323 {
1324 int i, irq;
1325
1326 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1327 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1328
1329 /* TODO: remove irq_domain_generic_chips */
1330
1331 for (i = 0; i < IPU_NUM_IRQS; i++) {
1332 irq = irq_linear_revmap(ipu->domain, i);
1333 if (irq)
1334 irq_dispose_mapping(irq);
1335 }
1336
1337 irq_domain_remove(ipu->domain);
1338 }
1339
1340 void ipu_dump(struct ipu_soc *ipu)
1341 {
1342 int i;
1343
1344 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1345 ipu_cm_read(ipu, IPU_CONF));
1346 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1347 ipu_idmac_read(ipu, IDMAC_CONF));
1348 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1349 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1350 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1351 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1352 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1353 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1354 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1355 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1356 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1357 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1358 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1359 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1360 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1361 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1362 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1363 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1364 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1365 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1366 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1367 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1368 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1369 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1370 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1371 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1372 for (i = 0; i < 15; i++)
1373 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1374 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1375 }
1376 EXPORT_SYMBOL_GPL(ipu_dump);
1377
1378 static int ipu_probe(struct platform_device *pdev)
1379 {
1380 struct device_node *np = pdev->dev.of_node;
1381 struct ipu_soc *ipu;
1382 struct resource *res;
1383 unsigned long ipu_base;
1384 int ret, irq_sync, irq_err;
1385 const struct ipu_devtype *devtype;
1386
1387 devtype = of_device_get_match_data(&pdev->dev);
1388 if (!devtype)
1389 return -EINVAL;
1390
1391 irq_sync = platform_get_irq(pdev, 0);
1392 irq_err = platform_get_irq(pdev, 1);
1393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1394
1395 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1396 irq_sync, irq_err);
1397
1398 if (!res || irq_sync < 0 || irq_err < 0)
1399 return -ENODEV;
1400
1401 ipu_base = res->start;
1402
1403 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1404 if (!ipu)
1405 return -ENODEV;
1406
1407 ipu->id = of_alias_get_id(np, "ipu");
1408 if (ipu->id < 0)
1409 ipu->id = 0;
1410
1411 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") &&
1412 IS_ENABLED(CONFIG_DRM)) {
1413 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev,
1414 "fsl,prg", ipu->id);
1415 if (!ipu->prg_priv)
1416 return -EPROBE_DEFER;
1417 }
1418
1419 ipu->devtype = devtype;
1420 ipu->ipu_type = devtype->type;
1421
1422 spin_lock_init(&ipu->lock);
1423 mutex_init(&ipu->channel_lock);
1424 INIT_LIST_HEAD(&ipu->channels);
1425
1426 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1427 ipu_base + devtype->cm_ofs);
1428 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1429 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1430 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1431 ipu_base + devtype->cpmem_ofs);
1432 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1433 ipu_base + devtype->csi0_ofs);
1434 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1435 ipu_base + devtype->csi1_ofs);
1436 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1437 ipu_base + devtype->ic_ofs);
1438 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1439 ipu_base + devtype->disp0_ofs);
1440 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1441 ipu_base + devtype->disp1_ofs);
1442 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1443 ipu_base + devtype->srm_ofs);
1444 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1445 ipu_base + devtype->tpm_ofs);
1446 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1447 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1448 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1449 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1450 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1451 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1452 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1453 ipu_base + devtype->vdi_ofs);
1454
1455 ipu->cm_reg = devm_ioremap(&pdev->dev,
1456 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1457 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1458 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1459 PAGE_SIZE);
1460
1461 if (!ipu->cm_reg || !ipu->idmac_reg)
1462 return -ENOMEM;
1463
1464 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1465 if (IS_ERR(ipu->clk)) {
1466 ret = PTR_ERR(ipu->clk);
1467 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1468 return ret;
1469 }
1470
1471 platform_set_drvdata(pdev, ipu);
1472
1473 ret = clk_prepare_enable(ipu->clk);
1474 if (ret) {
1475 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1476 return ret;
1477 }
1478
1479 ipu->dev = &pdev->dev;
1480 ipu->irq_sync = irq_sync;
1481 ipu->irq_err = irq_err;
1482
1483 ret = device_reset(&pdev->dev);
1484 if (ret) {
1485 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1486 goto out_failed_reset;
1487 }
1488 ret = ipu_memory_reset(ipu);
1489 if (ret)
1490 goto out_failed_reset;
1491
1492 ret = ipu_irq_init(ipu);
1493 if (ret)
1494 goto out_failed_irq;
1495
1496 /* Set MCU_T to divide MCU access window into 2 */
1497 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1498 IPU_DISP_GEN);
1499
1500 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1501 if (ret)
1502 goto failed_submodules_init;
1503
1504 ret = ipu_add_client_devices(ipu, ipu_base);
1505 if (ret) {
1506 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1507 ret);
1508 goto failed_add_clients;
1509 }
1510
1511 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1512
1513 return 0;
1514
1515 failed_add_clients:
1516 ipu_submodules_exit(ipu);
1517 failed_submodules_init:
1518 ipu_irq_exit(ipu);
1519 out_failed_irq:
1520 out_failed_reset:
1521 clk_disable_unprepare(ipu->clk);
1522 return ret;
1523 }
1524
1525 static int ipu_remove(struct platform_device *pdev)
1526 {
1527 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1528
1529 platform_device_unregister_children(pdev);
1530 ipu_submodules_exit(ipu);
1531 ipu_irq_exit(ipu);
1532
1533 clk_disable_unprepare(ipu->clk);
1534
1535 return 0;
1536 }
1537
1538 static struct platform_driver imx_ipu_driver = {
1539 .driver = {
1540 .name = "imx-ipuv3",
1541 .of_match_table = imx_ipu_dt_ids,
1542 },
1543 .probe = ipu_probe,
1544 .remove = ipu_remove,
1545 };
1546
1547 static struct platform_driver * const drivers[] = {
1548 #if IS_ENABLED(CONFIG_DRM)
1549 &ipu_pre_drv,
1550 &ipu_prg_drv,
1551 #endif
1552 &imx_ipu_driver,
1553 };
1554
1555 static int __init imx_ipu_init(void)
1556 {
1557 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1558 }
1559 module_init(imx_ipu_init);
1560
1561 static void __exit imx_ipu_exit(void)
1562 {
1563 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1564 }
1565 module_exit(imx_ipu_exit);
1566
1567 MODULE_ALIAS("platform:imx-ipuv3");
1568 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1569 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1570 MODULE_LICENSE("GPL");
Linux with added FPC-III support