include/dt-bindings/clock/tegra30-car.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * This header provides constants for binding nvidia,tegra30-car.
   4  *
   5  * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
   6  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
   7  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
   8  * this case, those clocks are assigned IDs above 160 in order to highlight
   9  * this issue. Implementations that interpret these clock IDs as bit values
  10  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  11  * explicitly handle these special cases.
  12  *
  13  * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
  14  * above.
  15  */
  16
  17 #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
  18 #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
  19
  20 #define TEGRA30_CLK_CPU 0
  21 /* 1 */
  22 /* 2 */
  23 /* 3 */
  24 #define TEGRA30_CLK_RTC 4
  25 #define TEGRA30_CLK_TIMER 5
  26 #define TEGRA30_CLK_UARTA 6
  27 /* 7 (register bit affects uartb and vfir) */
  28 #define TEGRA30_CLK_GPIO 8
  29 #define TEGRA30_CLK_SDMMC2 9
  30 /* 10 (register bit affects spdif_in and spdif_out) */
  31 #define TEGRA30_CLK_I2S1 11
  32 #define TEGRA30_CLK_I2C1 12
  33 #define TEGRA30_CLK_NDFLASH 13
  34 #define TEGRA30_CLK_SDMMC1 14
  35 #define TEGRA30_CLK_SDMMC4 15
  36 /* 16 */
  37 #define TEGRA30_CLK_PWM 17
  38 #define TEGRA30_CLK_I2S2 18
  39 #define TEGRA30_CLK_EPP 19
  40 /* 20 (register bit affects vi and vi_sensor) */
  41 #define TEGRA30_CLK_GR2D 21
  42 #define TEGRA30_CLK_USBD 22
  43 #define TEGRA30_CLK_ISP 23
  44 #define TEGRA30_CLK_GR3D 24
  45 /* 25 */
  46 #define TEGRA30_CLK_DISP2 26
  47 #define TEGRA30_CLK_DISP1 27
  48 #define TEGRA30_CLK_HOST1X 28
  49 #define TEGRA30_CLK_VCP 29
  50 #define TEGRA30_CLK_I2S0 30
  51 #define TEGRA30_CLK_COP_CACHE 31
  52
  53 #define TEGRA30_CLK_MC 32
  54 #define TEGRA30_CLK_AHBDMA 33
  55 #define TEGRA30_CLK_APBDMA 34
  56 /* 35 */
  57 #define TEGRA30_CLK_KBC 36
  58 #define TEGRA30_CLK_STATMON 37
  59 #define TEGRA30_CLK_PMC 38
  60 /* 39 (register bit affects fuse and fuse_burn) */
  61 #define TEGRA30_CLK_KFUSE 40
  62 #define TEGRA30_CLK_SBC1 41
  63 #define TEGRA30_CLK_NOR 42
  64 /* 43 */
  65 #define TEGRA30_CLK_SBC2 44
  66 /* 45 */
  67 #define TEGRA30_CLK_SBC3 46
  68 #define TEGRA30_CLK_I2C5 47
  69 #define TEGRA30_CLK_DSIA 48
  70 /* 49 (register bit affects cve and tvo) */
  71 #define TEGRA30_CLK_MIPI 50
  72 #define TEGRA30_CLK_HDMI 51
  73 #define TEGRA30_CLK_CSI 52
  74 #define TEGRA30_CLK_TVDAC 53
  75 #define TEGRA30_CLK_I2C2 54
  76 #define TEGRA30_CLK_UARTC 55
  77 /* 56 */
  78 #define TEGRA30_CLK_EMC 57
  79 #define TEGRA30_CLK_USB2 58
  80 #define TEGRA30_CLK_USB3 59
  81 #define TEGRA30_CLK_MPE 60
  82 #define TEGRA30_CLK_VDE 61
  83 #define TEGRA30_CLK_BSEA 62
  84 #define TEGRA30_CLK_BSEV 63
  85
  86 #define TEGRA30_CLK_SPEEDO 64
  87 #define TEGRA30_CLK_UARTD 65
  88 #define TEGRA30_CLK_UARTE 66
  89 #define TEGRA30_CLK_I2C3 67
  90 #define TEGRA30_CLK_SBC4 68
  91 #define TEGRA30_CLK_SDMMC3 69
  92 #define TEGRA30_CLK_PCIE 70
  93 #define TEGRA30_CLK_OWR 71
  94 #define TEGRA30_CLK_AFI 72
  95 #define TEGRA30_CLK_CSITE 73
  96 /* 74 */
  97 #define TEGRA30_CLK_AVPUCQ 75
  98 #define TEGRA30_CLK_LA 76
  99 /* 77 */
 100 /* 78 */
 101 #define TEGRA30_CLK_DTV 79
 102 #define TEGRA30_CLK_NDSPEED 80
 103 #define TEGRA30_CLK_I2CSLOW 81
 104 #define TEGRA30_CLK_DSIB 82
 105 /* 83 */
 106 #define TEGRA30_CLK_IRAMA 84
 107 #define TEGRA30_CLK_IRAMB 85
 108 #define TEGRA30_CLK_IRAMC 86
 109 #define TEGRA30_CLK_IRAMD 87
 110 #define TEGRA30_CLK_CRAM2 88
 111 /* 89 */
 112 #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
 113 /* 91 */
 114 #define TEGRA30_CLK_CSUS 92
 115 #define TEGRA30_CLK_CDEV2 93
 116 #define TEGRA30_CLK_CDEV1 94
 117 /* 95 */
 118
 119 #define TEGRA30_CLK_CPU_G 96
 120 #define TEGRA30_CLK_CPU_LP 97
 121 #define TEGRA30_CLK_GR3D2 98
 122 #define TEGRA30_CLK_MSELECT 99
 123 #define TEGRA30_CLK_TSENSOR 100
 124 #define TEGRA30_CLK_I2S3 101
 125 #define TEGRA30_CLK_I2S4 102
 126 #define TEGRA30_CLK_I2C4 103
 127 #define TEGRA30_CLK_SBC5 104
 128 #define TEGRA30_CLK_SBC6 105
 129 #define TEGRA30_CLK_D_AUDIO 106
 130 #define TEGRA30_CLK_APBIF 107
 131 #define TEGRA30_CLK_DAM0 108
 132 #define TEGRA30_CLK_DAM1 109
 133 #define TEGRA30_CLK_DAM2 110
 134 #define TEGRA30_CLK_HDA2CODEC_2X 111
 135 #define TEGRA30_CLK_ATOMICS 112
 136 #define TEGRA30_CLK_AUDIO0_2X 113
 137 #define TEGRA30_CLK_AUDIO1_2X 114
 138 #define TEGRA30_CLK_AUDIO2_2X 115
 139 #define TEGRA30_CLK_AUDIO3_2X 116
 140 #define TEGRA30_CLK_AUDIO4_2X 117
 141 #define TEGRA30_CLK_SPDIF_2X 118
 142 #define TEGRA30_CLK_ACTMON 119
 143 #define TEGRA30_CLK_EXTERN1 120
 144 #define TEGRA30_CLK_EXTERN2 121
 145 #define TEGRA30_CLK_EXTERN3 122
 146 #define TEGRA30_CLK_SATA_OOB 123
 147 #define TEGRA30_CLK_SATA 124
 148 #define TEGRA30_CLK_HDA 125
 149 /* 126 */
 150 #define TEGRA30_CLK_SE 127
 151
 152 #define TEGRA30_CLK_HDA2HDMI 128
 153 #define TEGRA30_CLK_SATA_COLD 129
 154 /* 130 */
 155 /* 131 */
 156 /* 132 */
 157 /* 133 */
 158 /* 134 */
 159 /* 135 */
 160 #define TEGRA30_CLK_CEC 136
 161 /* 137 */
 162 /* 138 */
 163 /* 139 */
 164 /* 140 */
 165 /* 141 */
 166 /* 142 */
 167 /* 143 */
 168 /* 144 */
 169 /* 145 */
 170 /* 146 */
 171 /* 147 */
 172 /* 148 */
 173 /* 149 */
 174 /* 150 */
 175 /* 151 */
 176 /* 152 */
 177 /* 153 */
 178 /* 154 */
 179 /* 155 */
 180 /* 156 */
 181 /* 157 */
 182 /* 158 */
 183 /* 159 */
 184
 185 #define TEGRA30_CLK_UARTB 160
 186 #define TEGRA30_CLK_VFIR 161
 187 #define TEGRA30_CLK_SPDIF_IN 162
 188 #define TEGRA30_CLK_SPDIF_OUT 163
 189 #define TEGRA30_CLK_VI 164
 190 #define TEGRA30_CLK_VI_SENSOR 165
 191 #define TEGRA30_CLK_FUSE 166
 192 #define TEGRA30_CLK_FUSE_BURN 167
 193 #define TEGRA30_CLK_CVE 168
 194 #define TEGRA30_CLK_TVO 169
 195 #define TEGRA30_CLK_CLK_32K 170
 196 #define TEGRA30_CLK_CLK_M 171
 197 #define TEGRA30_CLK_CLK_M_DIV2 172
 198 #define TEGRA30_CLK_CLK_M_DIV4 173
 199 #define TEGRA30_CLK_PLL_REF 174
 200 #define TEGRA30_CLK_PLL_C 175
 201 #define TEGRA30_CLK_PLL_C_OUT1 176
 202 #define TEGRA30_CLK_PLL_M 177
 203 #define TEGRA30_CLK_PLL_M_OUT1 178
 204 #define TEGRA30_CLK_PLL_P 179
 205 #define TEGRA30_CLK_PLL_P_OUT1 180
 206 #define TEGRA30_CLK_PLL_P_OUT2 181
 207 #define TEGRA30_CLK_PLL_P_OUT3 182
 208 #define TEGRA30_CLK_PLL_P_OUT4 183
 209 #define TEGRA30_CLK_PLL_A 184
 210 #define TEGRA30_CLK_PLL_A_OUT0 185
 211 #define TEGRA30_CLK_PLL_D 186
 212 #define TEGRA30_CLK_PLL_D_OUT0 187
 213 #define TEGRA30_CLK_PLL_D2 188
 214 #define TEGRA30_CLK_PLL_D2_OUT0 189
 215 #define TEGRA30_CLK_PLL_U 190
 216 #define TEGRA30_CLK_PLL_X 191
 217
 218 #define TEGRA30_CLK_PLL_X_OUT0 192
 219 #define TEGRA30_CLK_PLL_E 193
 220 #define TEGRA30_CLK_SPDIF_IN_SYNC 194
 221 #define TEGRA30_CLK_I2S0_SYNC 195
 222 #define TEGRA30_CLK_I2S1_SYNC 196
 223 #define TEGRA30_CLK_I2S2_SYNC 197
 224 #define TEGRA30_CLK_I2S3_SYNC 198
 225 #define TEGRA30_CLK_I2S4_SYNC 199
 226 #define TEGRA30_CLK_VIMCLK_SYNC 200
 227 #define TEGRA30_CLK_AUDIO0 201
 228 #define TEGRA30_CLK_AUDIO1 202
 229 #define TEGRA30_CLK_AUDIO2 203
 230 #define TEGRA30_CLK_AUDIO3 204
 231 #define TEGRA30_CLK_AUDIO4 205
 232 #define TEGRA30_CLK_SPDIF 206
 233 #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
 234 #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
 235 #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
 236 #define TEGRA30_CLK_SCLK 210
 237 #define TEGRA30_CLK_BLINK 211
 238 #define TEGRA30_CLK_CCLK_G 212
 239 #define TEGRA30_CLK_CCLK_LP 213
 240 #define TEGRA30_CLK_TWD 214
 241 #define TEGRA30_CLK_CML0 215
 242 #define TEGRA30_CLK_CML1 216
 243 #define TEGRA30_CLK_HCLK 217
 244 #define TEGRA30_CLK_PCLK 218
 245 /* 219 */
 246 /* 220 */
 247 /* 221 */
 248 /* 222 */
 249 /* 223 */
 250
 251 /* 288 */
 252 /* 289 */
 253 /* 290 */
 254 /* 291 */
 255 /* 292 */
 256 /* 293 */
 257 /* 294 */
 258 /* 295 */
 259 /* 296 */
 260 /* 297 */
 261 /* 298 */
 262 /* 299 */
 263 #define TEGRA30_CLK_CLK_OUT_1_MUX 300
 264 #define TEGRA30_CLK_CLK_OUT_2_MUX 301
 265 #define TEGRA30_CLK_CLK_OUT_3_MUX 302
 266 #define TEGRA30_CLK_AUDIO0_MUX 303
 267 #define TEGRA30_CLK_AUDIO1_MUX 304
 268 #define TEGRA30_CLK_AUDIO2_MUX 305
 269 #define TEGRA30_CLK_AUDIO3_MUX 306
 270 #define TEGRA30_CLK_AUDIO4_MUX 307
 271 #define TEGRA30_CLK_SPDIF_MUX 308
 272 #define TEGRA30_CLK_CLK_MAX 309
 273
 274 #endif  /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */