[NETFILTER]: Fix deadlock in ip6_queue
[linux/fpc-iii.git] / include / video / tx3912.h
blob6b6d006038c28594495fe411dc257e51fd8f578a
1 /*
2 * linux/include/video/tx3912.h
4 * Copyright (C) 2001 Steven Hill (sjhill@realitydiluted.com)
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
10 * Includes for TMPR3912/05 and PR31700 LCD controller registers
12 #include <asm/tx3912.h>
14 #define VidCtrl1 REG_AT(0x028)
15 #define VidCtrl2 REG_AT(0x02C)
16 #define VidCtrl3 REG_AT(0x030)
17 #define VidCtrl4 REG_AT(0x034)
18 #define VidCtrl5 REG_AT(0x038)
19 #define VidCtrl6 REG_AT(0x03C)
20 #define VidCtrl7 REG_AT(0x040)
21 #define VidCtrl8 REG_AT(0x044)
22 #define VidCtrl9 REG_AT(0x048)
23 #define VidCtrl10 REG_AT(0x04C)
24 #define VidCtrl11 REG_AT(0x050)
25 #define VidCtrl12 REG_AT(0x054)
26 #define VidCtrl13 REG_AT(0x058)
27 #define VidCtrl14 REG_AT(0x05C)
29 /* Video Control 1 Register */
30 #define LINECNT 0xffc00000
31 #define LINECNT_SHIFT 22
32 #define LOADDLY BIT(21)
33 #define BAUDVAL (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16))
34 #define BAUDVAL_SHIFT 16
35 #define VIDDONEVAL (BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9))
36 #define VIDDONEVAL_SHIFT 9
37 #define ENFREEZEFRAME BIT(8)
38 #define TX3912_VIDCTRL1_BITSEL_MASK 0x000000c0
39 #define TX3912_VIDCTRL1_2BIT_GRAY 0x00000040
40 #define TX3912_VIDCTRL1_4BIT_GRAY 0x00000080
41 #define TX3912_VIDCTRL1_8BIT_COLOR 0x000000c0
42 #define BITSEL_SHIFT 6
43 #define DISPSPLIT BIT(5)
44 #define DISP8 BIT(4)
45 #define DFMODE BIT(3)
46 #define INVVID BIT(2)
47 #define DISPON BIT(1)
48 #define ENVID BIT(0)
50 /* Video Control 2 Register */
51 #define VIDRATE_MASK 0xffc00000
52 #define VIDRATE_SHIFT 22
53 #define HORZVAL_MASK 0x001ff000
54 #define HORZVAL_SHIFT 12
55 #define LINEVAL_MASK 0x000001ff
57 /* Video Control 3 Register */
58 #define TX3912_VIDCTRL3_VIDBANK_MASK 0xfff00000
59 #define TX3912_VIDCTRL3_VIDBASEHI_MASK 0x000ffff0
61 /* Video Control 4 Register */
62 #define TX3912_VIDCTRL4_VIDBASELO_MASK 0x000ffff0