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reiserfs: Fix spurious unlock in reiserfs_fill_super() error handling
[linux/fpc-iii.git] / drivers / spi / spi-uniphier.c
blob47cde1864630e02b5e3c8d253bb636c698cebdb9
1 // SPDX-License-Identifier: GPL-2.0
2 // spi-uniphier.c - Socionext UniPhier SPI controller driver
3 // Copyright 2012 Panasonic Corporation
4 // Copyright 2016-2018 Socionext Inc.
5
6 #include <linux/kernel.h>
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/spi/spi.h>
16
17 #include <asm/unaligned.h>
18
19 #define SSI_TIMEOUT_MS 2000
20 #define SSI_POLL_TIMEOUT_US 200
21 #define SSI_MAX_CLK_DIVIDER 254
22 #define SSI_MIN_CLK_DIVIDER 4
23
24 struct uniphier_spi_priv {
25 void __iomem *base;
26 struct clk *clk;
27 struct spi_master *master;
28 struct completion xfer_done;
29
30 int error;
31 unsigned int tx_bytes;
32 unsigned int rx_bytes;
33 const u8 *tx_buf;
34 u8 *rx_buf;
35
36 bool is_save_param;
37 u8 bits_per_word;
38 u16 mode;
39 u32 speed_hz;
40 };
41
42 #define SSI_CTL 0x00
43 #define SSI_CTL_EN BIT(0)
44
45 #define SSI_CKS 0x04
46 #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
47 #define SSI_CKS_CKPHS BIT(14)
48 #define SSI_CKS_CKINIT BIT(13)
49 #define SSI_CKS_CKDLY BIT(12)
50
51 #define SSI_TXWDS 0x08
52 #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
53 #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
54 #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
55
56 #define SSI_RXWDS 0x0c
57 #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
58
59 #define SSI_FPS 0x10
60 #define SSI_FPS_FSPOL BIT(15)
61 #define SSI_FPS_FSTRT BIT(14)
62
63 #define SSI_SR 0x14
64 #define SSI_SR_RNE BIT(0)
65
66 #define SSI_IE 0x18
67 #define SSI_IE_RCIE BIT(3)
68 #define SSI_IE_RORIE BIT(0)
69
70 #define SSI_IS 0x1c
71 #define SSI_IS_RXRS BIT(9)
72 #define SSI_IS_RCID BIT(3)
73 #define SSI_IS_RORID BIT(0)
74
75 #define SSI_IC 0x1c
76 #define SSI_IC_TCIC BIT(4)
77 #define SSI_IC_RCIC BIT(3)
78 #define SSI_IC_RORIC BIT(0)
79
80 #define SSI_FC 0x20
81 #define SSI_FC_TXFFL BIT(12)
82 #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
83 #define SSI_FC_RXFFL BIT(4)
84 #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
85
86 #define SSI_TXDR 0x24
87 #define SSI_RXDR 0x24
88
89 #define SSI_FIFO_DEPTH 8U
90
91 static inline unsigned int bytes_per_word(unsigned int bits)
92 {
93 return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
94 }
95
96 static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask)
97 {
98 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
99 u32 val;
100
101 val = readl(priv->base + SSI_IE);
102 val |= mask;
103 writel(val, priv->base + SSI_IE);
104 }
105
106 static inline void uniphier_spi_irq_disable(struct spi_device *spi, u32 mask)
107 {
108 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
109 u32 val;
110
111 val = readl(priv->base + SSI_IE);
112 val &= ~mask;
113 writel(val, priv->base + SSI_IE);
114 }
115
116 static void uniphier_spi_set_mode(struct spi_device *spi)
117 {
118 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
119 u32 val1, val2;
120
121 /*
122 * clock setting
123 * CKPHS capture timing. 0:rising edge, 1:falling edge
124 * CKINIT clock initial level. 0:low, 1:high
125 * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
126 * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
127 *
128 * frame setting
129 * FSPOL frame signal porarity. 0: low, 1: high
130 * FSTRT start frame timing
131 * 0: rising edge of clock, 1: falling edge of clock
132 */
133 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
134 case SPI_MODE_0:
135 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
136 val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
137 val2 = 0;
138 break;
139 case SPI_MODE_1:
140 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
141 val1 = 0;
142 val2 = SSI_FPS_FSTRT;
143 break;
144 case SPI_MODE_2:
145 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
146 val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
147 val2 = SSI_FPS_FSTRT;
148 break;
149 case SPI_MODE_3:
150 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
151 val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
152 val2 = 0;
153 break;
154 }
155
156 if (!(spi->mode & SPI_CS_HIGH))
157 val2 |= SSI_FPS_FSPOL;
158
159 writel(val1, priv->base + SSI_CKS);
160 writel(val2, priv->base + SSI_FPS);
161
162 val1 = 0;
163 if (spi->mode & SPI_LSB_FIRST)
164 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
165 writel(val1, priv->base + SSI_TXWDS);
166 writel(val1, priv->base + SSI_RXWDS);
167 }
168
169 static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
170 {
171 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
172 u32 val;
173
174 val = readl(priv->base + SSI_TXWDS);
175 val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
176 val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
177 val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
178 writel(val, priv->base + SSI_TXWDS);
179
180 val = readl(priv->base + SSI_RXWDS);
181 val &= ~SSI_RXWDS_DTLEN_MASK;
182 val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
183 writel(val, priv->base + SSI_RXWDS);
184 }
185
186 static void uniphier_spi_set_baudrate(struct spi_device *spi,
187 unsigned int speed)
188 {
189 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
190 u32 val, ckdiv;
191
192 /*
193 * the supported rates are even numbers from 4 to 254. (4,6,8...254)
194 * round up as we look for equal or less speed
195 */
196 ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
197 ckdiv = round_up(ckdiv, 2);
198
199 val = readl(priv->base + SSI_CKS);
200 val &= ~SSI_CKS_CKRAT_MASK;
201 val |= ckdiv & SSI_CKS_CKRAT_MASK;
202 writel(val, priv->base + SSI_CKS);
203 }
204
205 static void uniphier_spi_setup_transfer(struct spi_device *spi,
206 struct spi_transfer *t)
207 {
208 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
209 u32 val;
210
211 priv->error = 0;
212 priv->tx_buf = t->tx_buf;
213 priv->rx_buf = t->rx_buf;
214 priv->tx_bytes = priv->rx_bytes = t->len;
215
216 if (!priv->is_save_param || priv->mode != spi->mode) {
217 uniphier_spi_set_mode(spi);
218 priv->mode = spi->mode;
219 priv->is_save_param = false;
220 }
221
222 if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
223 uniphier_spi_set_transfer_size(spi, t->bits_per_word);
224 priv->bits_per_word = t->bits_per_word;
225 }
226
227 if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
228 uniphier_spi_set_baudrate(spi, t->speed_hz);
229 priv->speed_hz = t->speed_hz;
230 }
231
232 priv->is_save_param = true;
233
234 /* reset FIFOs */
235 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
236 writel(val, priv->base + SSI_FC);
237 }
238
239 static void uniphier_spi_send(struct uniphier_spi_priv *priv)
240 {
241 int wsize;
242 u32 val = 0;
243
244 wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
245 priv->tx_bytes -= wsize;
246
247 if (priv->tx_buf) {
248 switch (wsize) {
249 case 1:
250 val = *priv->tx_buf;
251 break;
252 case 2:
253 val = get_unaligned_le16(priv->tx_buf);
254 break;
255 case 4:
256 val = get_unaligned_le32(priv->tx_buf);
257 break;
258 }
259
260 priv->tx_buf += wsize;
261 }
262
263 writel(val, priv->base + SSI_TXDR);
264 }
265
266 static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
267 {
268 int rsize;
269 u32 val;
270
271 rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
272 priv->rx_bytes -= rsize;
273
274 val = readl(priv->base + SSI_RXDR);
275
276 if (priv->rx_buf) {
277 switch (rsize) {
278 case 1:
279 *priv->rx_buf = val;
280 break;
281 case 2:
282 put_unaligned_le16(val, priv->rx_buf);
283 break;
284 case 4:
285 put_unaligned_le32(val, priv->rx_buf);
286 break;
287 }
288
289 priv->rx_buf += rsize;
290 }
291 }
292
293 static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
294 {
295 unsigned int fifo_threshold, fill_bytes;
296 u32 val;
297
298 fifo_threshold = DIV_ROUND_UP(priv->rx_bytes,
299 bytes_per_word(priv->bits_per_word));
300 fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
301
302 fill_bytes = fifo_threshold - (priv->rx_bytes - priv->tx_bytes);
303
304 /* set fifo threshold */
305 val = readl(priv->base + SSI_FC);
306 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
307 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, fifo_threshold);
308 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, fifo_threshold);
309 writel(val, priv->base + SSI_FC);
310
311 while (fill_bytes--)
312 uniphier_spi_send(priv);
313 }
314
315 static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
316 {
317 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
318 u32 val;
319
320 val = readl(priv->base + SSI_FPS);
321
322 if (enable)
323 val |= SSI_FPS_FSPOL;
324 else
325 val &= ~SSI_FPS_FSPOL;
326
327 writel(val, priv->base + SSI_FPS);
328 }
329
330 static int uniphier_spi_transfer_one_irq(struct spi_master *master,
331 struct spi_device *spi,
332 struct spi_transfer *t)
333 {
334 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
335 struct device *dev = master->dev.parent;
336 unsigned long time_left;
337
338 reinit_completion(&priv->xfer_done);
339
340 uniphier_spi_fill_tx_fifo(priv);
341
342 uniphier_spi_irq_enable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
343
344 time_left = wait_for_completion_timeout(&priv->xfer_done,
345 msecs_to_jiffies(SSI_TIMEOUT_MS));
346
347 uniphier_spi_irq_disable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
348
349 if (!time_left) {
350 dev_err(dev, "transfer timeout.\n");
351 return -ETIMEDOUT;
352 }
353
354 return priv->error;
355 }
356
357 static int uniphier_spi_transfer_one_poll(struct spi_master *master,
358 struct spi_device *spi,
359 struct spi_transfer *t)
360 {
361 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
362 int loop = SSI_POLL_TIMEOUT_US * 10;
363
364 while (priv->tx_bytes) {
365 uniphier_spi_fill_tx_fifo(priv);
366
367 while ((priv->rx_bytes - priv->tx_bytes) > 0) {
368 while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
369 && loop--)
370 ndelay(100);
371
372 if (loop == -1)
373 goto irq_transfer;
374
375 uniphier_spi_recv(priv);
376 }
377 }
378
379 return 0;
380
381 irq_transfer:
382 return uniphier_spi_transfer_one_irq(master, spi, t);
383 }
384
385 static int uniphier_spi_transfer_one(struct spi_master *master,
386 struct spi_device *spi,
387 struct spi_transfer *t)
388 {
389 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
390 unsigned long threshold;
391
392 /* Terminate and return success for 0 byte length transfer */
393 if (!t->len)
394 return 0;
395
396 uniphier_spi_setup_transfer(spi, t);
397
398 /*
399 * If the transfer operation will take longer than
400 * SSI_POLL_TIMEOUT_US, it should use irq.
401 */
402 threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
403 USEC_PER_SEC * BITS_PER_BYTE);
404 if (t->len > threshold)
405 return uniphier_spi_transfer_one_irq(master, spi, t);
406 else
407 return uniphier_spi_transfer_one_poll(master, spi, t);
408 }
409
410 static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
411 {
412 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
413
414 writel(SSI_CTL_EN, priv->base + SSI_CTL);
415
416 return 0;
417 }
418
419 static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
420 {
421 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
422
423 writel(0, priv->base + SSI_CTL);
424
425 return 0;
426 }
427
428 static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
429 {
430 struct uniphier_spi_priv *priv = dev_id;
431 u32 val, stat;
432
433 stat = readl(priv->base + SSI_IS);
434 val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
435 writel(val, priv->base + SSI_IC);
436
437 /* rx fifo overrun */
438 if (stat & SSI_IS_RORID) {
439 priv->error = -EIO;
440 goto done;
441 }
442
443 /* rx complete */
444 if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
445 while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
446 (priv->rx_bytes - priv->tx_bytes) > 0)
447 uniphier_spi_recv(priv);
448
449 if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
450 (priv->rx_bytes != priv->tx_bytes)) {
451 priv->error = -EIO;
452 goto done;
453 } else if (priv->rx_bytes == 0)
454 goto done;
455
456 /* next tx transfer */
457 uniphier_spi_fill_tx_fifo(priv);
458
459 return IRQ_HANDLED;
460 }
461
462 return IRQ_NONE;
463
464 done:
465 complete(&priv->xfer_done);
466 return IRQ_HANDLED;
467 }
468
469 static int uniphier_spi_probe(struct platform_device *pdev)
470 {
471 struct uniphier_spi_priv *priv;
472 struct spi_master *master;
473 unsigned long clk_rate;
474 int irq;
475 int ret;
476
477 master = spi_alloc_master(&pdev->dev, sizeof(*priv));
478 if (!master)
479 return -ENOMEM;
480
481 platform_set_drvdata(pdev, master);
482
483 priv = spi_master_get_devdata(master);
484 priv->master = master;
485 priv->is_save_param = false;
486
487 priv->base = devm_platform_ioremap_resource(pdev, 0);
488 if (IS_ERR(priv->base)) {
489 ret = PTR_ERR(priv->base);
490 goto out_master_put;
491 }
492
493 priv->clk = devm_clk_get(&pdev->dev, NULL);
494 if (IS_ERR(priv->clk)) {
495 dev_err(&pdev->dev, "failed to get clock\n");
496 ret = PTR_ERR(priv->clk);
497 goto out_master_put;
498 }
499
500 ret = clk_prepare_enable(priv->clk);
501 if (ret)
502 goto out_master_put;
503
504 irq = platform_get_irq(pdev, 0);
505 if (irq < 0) {
506 ret = irq;
507 goto out_disable_clk;
508 }
509
510 ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
511 0, "uniphier-spi", priv);
512 if (ret) {
513 dev_err(&pdev->dev, "failed to request IRQ\n");
514 goto out_disable_clk;
515 }
516
517 init_completion(&priv->xfer_done);
518
519 clk_rate = clk_get_rate(priv->clk);
520
521 master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
522 master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
523 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
524 master->dev.of_node = pdev->dev.of_node;
525 master->bus_num = pdev->id;
526 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
527
528 master->set_cs = uniphier_spi_set_cs;
529 master->transfer_one = uniphier_spi_transfer_one;
530 master->prepare_transfer_hardware
531 = uniphier_spi_prepare_transfer_hardware;
532 master->unprepare_transfer_hardware
533 = uniphier_spi_unprepare_transfer_hardware;
534 master->num_chipselect = 1;
535
536 ret = devm_spi_register_master(&pdev->dev, master);
537 if (ret)
538 goto out_disable_clk;
539
540 return 0;
541
542 out_disable_clk:
543 clk_disable_unprepare(priv->clk);
544
545 out_master_put:
546 spi_master_put(master);
547 return ret;
548 }
549
550 static int uniphier_spi_remove(struct platform_device *pdev)
551 {
552 struct uniphier_spi_priv *priv = platform_get_drvdata(pdev);
553
554 clk_disable_unprepare(priv->clk);
555
556 return 0;
557 }
558
559 static const struct of_device_id uniphier_spi_match[] = {
560 { .compatible = "socionext,uniphier-scssi" },
561 { /* sentinel */ }
562 };
563 MODULE_DEVICE_TABLE(of, uniphier_spi_match);
564
565 static struct platform_driver uniphier_spi_driver = {
566 .probe = uniphier_spi_probe,
567 .remove = uniphier_spi_remove,
568 .driver = {
569 .name = "uniphier-spi",
570 .of_match_table = uniphier_spi_match,
571 },
572 };
573 module_platform_driver(uniphier_spi_driver);
574
575 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
576 MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
577 MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
578 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support