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iwlwifi: mvm: fix pending frame counter calculation
[linux/fpc-iii.git] / drivers / scsi / qla4xxx / ql4_nx.h
blob337d9fcf64175d155cdede50d58fa45f68c1f31e
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_NX_H
8 #define __QLA_NX_H
9
10 /*
11 * Following are the states of the Phantom. Phantom will set them and
12 * Host will read to check if the fields are correct.
13 */
14 #define PHAN_INITIALIZE_FAILED 0xffff
15 #define PHAN_INITIALIZE_COMPLETE 0xff01
16
17 /* Host writes the following to notify that it has done the init-handshake */
18 #define PHAN_INITIALIZE_ACK 0xf00f
19 #define PHAN_PEG_RCV_INITIALIZED 0xff01
20
21 /*CRB_RELATED*/
22 #define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))
23 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
24 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
25 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
26 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
27 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
28 #define CRB_CMDPEG_CHECK_RETRY_COUNT 60
29 #define CRB_CMDPEG_CHECK_DELAY 500
30
31 #define qla82xx_get_temp_val(x) ((x) >> 16)
32 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
33 #define qla82xx_encode_temp(val, state) (((val) << 16) | (state))
34
35 /*
36 * Temperature control.
37 */
38 enum {
39 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
40 QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */
41 QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */
42 };
43
44 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
45 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
46
47 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
48 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
49 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
50 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
51 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
52 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
53 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
54
55 /* Hub 0 */
56 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
57 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
58
59 /* Hub 1 */
60 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
61 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
62 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
63 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
64 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
65 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
66 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
67 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
68 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
69 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
70 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
71 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
72 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
73 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
74 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
75
76 /* Hub 2 */
77 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
78 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
79 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
80
81 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
82 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
83 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
84 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
85 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
86 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
87 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
88 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
89 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
90 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
91 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
92 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
93 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
94
95 /* Hub 3 */
96 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
97 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
98 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
99 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
100
101 /* Hub 4 */
102 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
103 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
104 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
105 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
106 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
107 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
108 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
109 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
110 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
111 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
112 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
113 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
114
115 /* Hub 5 */
116 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
117 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
118 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
119 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
120
121 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
122 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
123 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
124
125 /* Hub 6 */
126 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
127 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
128 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
129 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
130 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
131 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
132 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
133 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
134 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
135
136 /* This field defines PCI/X adr [25:20] of agents on the CRB */
137 /* */
138 #define QLA82XX_HW_PX_MAP_CRB_PH 0
139 #define QLA82XX_HW_PX_MAP_CRB_PS 1
140 #define QLA82XX_HW_PX_MAP_CRB_MN 2
141 #define QLA82XX_HW_PX_MAP_CRB_MS 3
142 #define QLA82XX_HW_PX_MAP_CRB_SRE 5
143 #define QLA82XX_HW_PX_MAP_CRB_NIU 6
144 #define QLA82XX_HW_PX_MAP_CRB_QMN 7
145 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
146 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
147 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
148 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
149 #define QLA82XX_HW_PX_MAP_CRB_QMS 12
150 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
151 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
152 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
153 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
154 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
155 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
156 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
157 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
158 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
159 #define QLA82XX_HW_PX_MAP_CRB_PGND 21
160 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
161 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
162 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
163 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
164 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
165 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
166 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
167 #define QLA82XX_HW_PX_MAP_CRB_SN 29
168 #define QLA82XX_HW_PX_MAP_CRB_EG 31
169 #define QLA82XX_HW_PX_MAP_CRB_PH2 32
170 #define QLA82XX_HW_PX_MAP_CRB_PS2 33
171 #define QLA82XX_HW_PX_MAP_CRB_CAM 34
172 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
173 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
174 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
175 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
176 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
177 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
178 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
179 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
180 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
181 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
182 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
183 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
184 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
185 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
186 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
187 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
188 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
189 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
190 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
191 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
192 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
193 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
194 #define QLA82XX_HW_PX_MAP_CRB_SMB 58
195 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
196 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
197 #define QLA82XX_HW_PX_MAP_CRB_LPC 61
198 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
199 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
200 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
201 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
202 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
203
204 /* This field defines CRB adr [31:20] of the agents */
205 /* */
206
207 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
208 QLA82XX_HW_MN_CRB_AGT_ADR)
209 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
210 QLA82XX_HW_PH_CRB_AGT_ADR)
211 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
212 QLA82XX_HW_MS_CRB_AGT_ADR)
213 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
214 QLA82XX_HW_PS_CRB_AGT_ADR)
215 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
216 QLA82XX_HW_SS_CRB_AGT_ADR)
217 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
218 QLA82XX_HW_RPMX3_CRB_AGT_ADR)
219 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
220 QLA82XX_HW_QMS_CRB_AGT_ADR)
221 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
222 QLA82XX_HW_SQGS0_CRB_AGT_ADR)
223 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
224 QLA82XX_HW_SQGS1_CRB_AGT_ADR)
225 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
226 QLA82XX_HW_SQGS2_CRB_AGT_ADR)
227 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
228 QLA82XX_HW_SQGS3_CRB_AGT_ADR)
229 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
230 QLA82XX_HW_C2C0_CRB_AGT_ADR)
231 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
232 QLA82XX_HW_C2C1_CRB_AGT_ADR)
233 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
234 QLA82XX_HW_RPMX2_CRB_AGT_ADR)
235 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
236 QLA82XX_HW_RPMX4_CRB_AGT_ADR)
237 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
238 QLA82XX_HW_RPMX7_CRB_AGT_ADR)
239 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
240 QLA82XX_HW_RPMX9_CRB_AGT_ADR)
241 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
242 QLA82XX_HW_SMB_CRB_AGT_ADR)
243
244 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
245 QLA82XX_HW_NIU_CRB_AGT_ADR)
246 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
247 QLA82XX_HW_I2C0_CRB_AGT_ADR)
248 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
249 QLA82XX_HW_I2C1_CRB_AGT_ADR)
250
251 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
252 QLA82XX_HW_SRE_CRB_AGT_ADR)
253 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
254 QLA82XX_HW_EG_CRB_AGT_ADR)
255 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
256 QLA82XX_HW_RPMX0_CRB_AGT_ADR)
257 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
258 QLA82XX_HW_QM_CRB_AGT_ADR)
259 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
260 QLA82XX_HW_SQG0_CRB_AGT_ADR)
261 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
262 QLA82XX_HW_SQG1_CRB_AGT_ADR)
263 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
264 QLA82XX_HW_SQG2_CRB_AGT_ADR)
265 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
266 QLA82XX_HW_SQG3_CRB_AGT_ADR)
267 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
268 QLA82XX_HW_RPMX1_CRB_AGT_ADR)
269 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
270 QLA82XX_HW_RPMX5_CRB_AGT_ADR)
271 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
272 QLA82XX_HW_RPMX6_CRB_AGT_ADR)
273 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
274 QLA82XX_HW_RPMX8_CRB_AGT_ADR)
275 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
276 QLA82XX_HW_CAS0_CRB_AGT_ADR)
277 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
278 QLA82XX_HW_CAS1_CRB_AGT_ADR)
279 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
280 QLA82XX_HW_CAS2_CRB_AGT_ADR)
281 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
282 QLA82XX_HW_CAS3_CRB_AGT_ADR)
283
284 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
285 QLA82XX_HW_PEGNI_CRB_AGT_ADR)
286 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
287 QLA82XX_HW_PEGND_CRB_AGT_ADR)
288 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
289 QLA82XX_HW_PEGN0_CRB_AGT_ADR)
290 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
291 QLA82XX_HW_PEGN1_CRB_AGT_ADR)
292 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
293 QLA82XX_HW_PEGN2_CRB_AGT_ADR)
294 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
295 QLA82XX_HW_PEGN3_CRB_AGT_ADR)
296 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
297 QLA82XX_HW_PEGN4_CRB_AGT_ADR)
298
299 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
300 QLA82XX_HW_PEGNC_CRB_AGT_ADR)
301 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
302 QLA82XX_HW_PEGR0_CRB_AGT_ADR)
303 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
304 QLA82XX_HW_PEGR1_CRB_AGT_ADR)
305 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
306 QLA82XX_HW_PEGR2_CRB_AGT_ADR)
307 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
308 QLA82XX_HW_PEGR3_CRB_AGT_ADR)
309
310 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
311 QLA82XX_HW_PEGSI_CRB_AGT_ADR)
312 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
313 QLA82XX_HW_PEGSD_CRB_AGT_ADR)
314 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
315 QLA82XX_HW_PEGS0_CRB_AGT_ADR)
316 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
317 QLA82XX_HW_PEGS1_CRB_AGT_ADR)
318 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
319 QLA82XX_HW_PEGS2_CRB_AGT_ADR)
320 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
321 QLA82XX_HW_PEGS3_CRB_AGT_ADR)
322 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
323 QLA82XX_HW_PEGSC_CRB_AGT_ADR)
324
325 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
326 QLA82XX_HW_NCM_CRB_AGT_ADR)
327 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
328 QLA82XX_HW_TMR_CRB_AGT_ADR)
329 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
330 QLA82XX_HW_XDMA_CRB_AGT_ADR)
331 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
332 QLA82XX_HW_SN_CRB_AGT_ADR)
333 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
334 QLA82XX_HW_I2Q_CRB_AGT_ADR)
335 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
336 QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
337 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
338 QLA82XX_HW_OCM0_CRB_AGT_ADR)
339 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
340 QLA82XX_HW_OCM1_CRB_AGT_ADR)
341 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
342 QLA82XX_HW_LPC_CRB_AGT_ADR)
343
344 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
345 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
346 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
347 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
348 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
349 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
350 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
351 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
352 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
353
354 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
355 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
356 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
357
358 /* Lock IDs for ROM lock */
359 #define ROM_LOCK_DRIVER 0x0d417340
360
361 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
362 #define QLA82XX_PCI_CRB_WINDOW(A) (QLA82XX_PCI_CRBSPACE + \
363 (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
364
365 #define QLA82XX_CRB_C2C_0 \
366 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
367 #define QLA82XX_CRB_C2C_1 \
368 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
369 #define QLA82XX_CRB_C2C_2 \
370 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
371 #define QLA82XX_CRB_CAM \
372 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
373 #define QLA82XX_CRB_CASPER \
374 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
375 #define QLA82XX_CRB_CASPER_0 \
376 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
377 #define QLA82XX_CRB_CASPER_1 \
378 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
379 #define QLA82XX_CRB_CASPER_2 \
380 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
381 #define QLA82XX_CRB_DDR_MD \
382 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
383 #define QLA82XX_CRB_DDR_NET \
384 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
385 #define QLA82XX_CRB_EPG \
386 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
387 #define QLA82XX_CRB_I2Q \
388 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
389 #define QLA82XX_CRB_NIU \
390 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
391 /* HACK upon HACK upon HACK (for PCIE builds) */
392 #define QLA82XX_CRB_PCIX_HOST \
393 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
394 #define QLA82XX_CRB_PCIX_HOST2 \
395 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
396 #define QLA82XX_CRB_PCIX_MD \
397 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
398 #define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD
399 /* window 1 pcie slot */
400 #define QLA82XX_CRB_PCIE2 \
401 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
402
403 #define QLA82XX_CRB_PEG_MD_0 \
404 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
405 #define QLA82XX_CRB_PEG_MD_1 \
406 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
407 #define QLA82XX_CRB_PEG_MD_2 \
408 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
409 #define QLA82XX_CRB_PEG_MD_3 \
410 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
411 #define QLA82XX_CRB_PEG_MD_3 \
412 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
413 #define QLA82XX_CRB_PEG_MD_D \
414 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
415 #define QLA82XX_CRB_PEG_MD_I \
416 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
417 #define QLA82XX_CRB_PEG_NET_0 \
418 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
419 #define QLA82XX_CRB_PEG_NET_1 \
420 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
421 #define QLA82XX_CRB_PEG_NET_2 \
422 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
423 #define QLA82XX_CRB_PEG_NET_3 \
424 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
425 #define QLA82XX_CRB_PEG_NET_4 \
426 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
427 #define QLA82XX_CRB_PEG_NET_D \
428 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
429 #define QLA82XX_CRB_PEG_NET_I \
430 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
431 #define QLA82XX_CRB_PQM_MD \
432 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
433 #define QLA82XX_CRB_PQM_NET \
434 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
435 #define QLA82XX_CRB_QDR_MD \
436 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
437 #define QLA82XX_CRB_QDR_NET \
438 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
439 #define QLA82XX_CRB_ROMUSB \
440 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
441 #define QLA82XX_CRB_RPMX_0 \
442 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
443 #define QLA82XX_CRB_RPMX_1 \
444 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
445 #define QLA82XX_CRB_RPMX_2 \
446 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
447 #define QLA82XX_CRB_RPMX_3 \
448 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
449 #define QLA82XX_CRB_RPMX_4 \
450 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
451 #define QLA82XX_CRB_RPMX_5 \
452 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
453 #define QLA82XX_CRB_RPMX_6 \
454 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
455 #define QLA82XX_CRB_RPMX_7 \
456 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
457 #define QLA82XX_CRB_SQM_MD_0 \
458 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
459 #define QLA82XX_CRB_SQM_MD_1 \
460 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
461 #define QLA82XX_CRB_SQM_MD_2 \
462 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
463 #define QLA82XX_CRB_SQM_MD_3 \
464 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
465 #define QLA82XX_CRB_SQM_NET_0 \
466 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
467 #define QLA82XX_CRB_SQM_NET_1 \
468 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
469 #define QLA82XX_CRB_SQM_NET_2 \
470 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
471 #define QLA82XX_CRB_SQM_NET_3 \
472 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
473 #define QLA82XX_CRB_SRE \
474 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
475 #define QLA82XX_CRB_TIMER \
476 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
477 #define QLA82XX_CRB_XDMA \
478 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
479 #define QLA82XX_CRB_I2C0 \
480 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
481 #define QLA82XX_CRB_I2C1 \
482 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
483 #define QLA82XX_CRB_OCM0 \
484 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
485 #define QLA82XX_CRB_SMB \
486 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
487
488 #define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64)
489
490 /*
491 * ====================== BASE ADDRESSES ON-CHIP ======================
492 * Base addresses of major components on-chip.
493 * ====================== BASE ADDRESSES ON-CHIP ======================
494 */
495 #define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)
496 #define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
497
498 /* Imbus address bit used to indicate a host address. This bit is
499 * eliminated by the pcie bar and bar select before presentation
500 * over pcie. */
501 /* host memory via IMBUS */
502 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
503 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
504 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
505 #define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)
506 #define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)
507 #define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)
508 #define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)
509 #define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)
510
511 #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
512 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
513 #define QLA8XXX_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
514
515 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
516 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
517 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
518 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
519 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
520 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
521 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
522
523 /* PCI Windowing for DDR regions. */
524 #define QLA8XXX_ADDR_IN_RANGE(addr, low, high) \
525 (((addr) <= (high)) && ((addr) >= (low)))
526
527 /*
528 * Register offsets for MN
529 */
530 #define MIU_CONTROL (0x000)
531 #define MIU_TAG (0x004)
532 #define MIU_TEST_AGT_CTRL (0x090)
533 #define MIU_TEST_AGT_ADDR_LO (0x094)
534 #define MIU_TEST_AGT_ADDR_HI (0x098)
535 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
536 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
537 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
538 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
539 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
540 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
541 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
542 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
543
544 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
545 #define MIU_TA_CTL_START 1
546 #define MIU_TA_CTL_ENABLE 2
547 #define MIU_TA_CTL_WRITE 4
548 #define MIU_TA_CTL_BUSY 8
549
550 #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
551 #define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE |\
552 MIU_TA_CTL_START)
553 #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
554
555 /*CAM RAM */
556 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
557 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
558
559 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
560 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
561 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
562 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
563 #define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))
564 #define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))
565
566 #define HALT_STATUS_UNRECOVERABLE 0x80000000
567 #define HALT_STATUS_RECOVERABLE 0x40000000
568
569
570 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
571 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
572 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
573 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
574 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
575 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
576
577 /* Driver Coexistence Defines */
578 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
579 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
580 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
581 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
582 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
583 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
584
585 enum qla_regs {
586 QLA8XXX_PEG_HALT_STATUS1 = 0,
587 QLA8XXX_PEG_HALT_STATUS2,
588 QLA8XXX_PEG_ALIVE_COUNTER,
589 QLA8XXX_CRB_DRV_ACTIVE,
590 QLA8XXX_CRB_DEV_STATE,
591 QLA8XXX_CRB_DRV_STATE,
592 QLA8XXX_CRB_DRV_SCRATCH,
593 QLA8XXX_CRB_DEV_PART_INFO,
594 QLA8XXX_CRB_DRV_IDC_VERSION,
595 QLA8XXX_FW_VERSION_MAJOR,
596 QLA8XXX_FW_VERSION_MINOR,
597 QLA8XXX_FW_VERSION_SUB,
598 QLA8XXX_CRB_CMDPEG_STATE,
599 QLA8XXX_CRB_TEMP_STATE,
600 };
601
602 static const uint32_t qla4_82xx_reg_tbl[] = {
603 QLA82XX_PEG_HALT_STATUS1,
604 QLA82XX_PEG_HALT_STATUS2,
605 QLA82XX_PEG_ALIVE_COUNTER,
606 QLA82XX_CRB_DRV_ACTIVE,
607 QLA82XX_CRB_DEV_STATE,
608 QLA82XX_CRB_DRV_STATE,
609 QLA82XX_CRB_DRV_SCRATCH,
610 QLA82XX_CRB_DEV_PART_INFO,
611 QLA82XX_CRB_DRV_IDC_VERSION,
612 QLA82XX_FW_VERSION_MAJOR,
613 QLA82XX_FW_VERSION_MINOR,
614 QLA82XX_FW_VERSION_SUB,
615 CRB_CMDPEG_STATE,
616 CRB_TEMP_STATE,
617 };
618
619 /* Every driver should use these Device State */
620 #define QLA8XXX_DEV_COLD 1
621 #define QLA8XXX_DEV_INITIALIZING 2
622 #define QLA8XXX_DEV_READY 3
623 #define QLA8XXX_DEV_NEED_RESET 4
624 #define QLA8XXX_DEV_NEED_QUIESCENT 5
625 #define QLA8XXX_DEV_FAILED 6
626 #define QLA8XXX_DEV_QUIESCENT 7
627 #define MAX_STATES 8 /* Increment if new state added */
628
629 #define QLA82XX_IDC_VERSION 0x1
630 #define ROM_DEV_INIT_TIMEOUT 30
631 #define ROM_DRV_RESET_ACK_TIMEOUT 10
632
633 #define PCIE_SETUP_FUNCTION (0x12040)
634 #define PCIE_SETUP_FUNCTION2 (0x12048)
635
636 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
637 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
638
639 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
640 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
641 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
642 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
643 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
644 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
645
646 /*
647 * The PCI VendorID and DeviceID for our board.
648 */
649 #define QLA82XX_MSIX_TBL_SPACE 8192
650 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
651 #define QLA82XX_PCI_MSIX_CONTROL 0x40
652
653 struct crb_128M_2M_sub_block_map {
654 unsigned valid;
655 unsigned start_128M;
656 unsigned end_128M;
657 unsigned start_2M;
658 };
659
660 struct crb_128M_2M_block_map {
661 struct crb_128M_2M_sub_block_map sub_block[16];
662 };
663
664 struct crb_addr_pair {
665 long addr;
666 long data;
667 };
668
669 #define ADDR_ERROR ((unsigned long) 0xffffffff)
670 #define MAX_CTL_CHECK 1000
671 #define QLA82XX_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)
672
673 /***************************************************************************
674 * PCI related defines.
675 **************************************************************************/
676
677 /*
678 * Interrupt related defines.
679 */
680 #define PCIX_TARGET_STATUS (0x10118)
681 #define PCIX_TARGET_STATUS_F1 (0x10160)
682 #define PCIX_TARGET_STATUS_F2 (0x10164)
683 #define PCIX_TARGET_STATUS_F3 (0x10168)
684 #define PCIX_TARGET_STATUS_F4 (0x10360)
685 #define PCIX_TARGET_STATUS_F5 (0x10364)
686 #define PCIX_TARGET_STATUS_F6 (0x10368)
687 #define PCIX_TARGET_STATUS_F7 (0x1036c)
688
689 #define PCIX_TARGET_MASK (0x10128)
690 #define PCIX_TARGET_MASK_F1 (0x10170)
691 #define PCIX_TARGET_MASK_F2 (0x10174)
692 #define PCIX_TARGET_MASK_F3 (0x10178)
693 #define PCIX_TARGET_MASK_F4 (0x10370)
694 #define PCIX_TARGET_MASK_F5 (0x10374)
695 #define PCIX_TARGET_MASK_F6 (0x10378)
696 #define PCIX_TARGET_MASK_F7 (0x1037c)
697
698 /*
699 * Message Signaled Interrupts
700 */
701 #define PCIX_MSI_F0 (0x13000)
702 #define PCIX_MSI_F1 (0x13004)
703 #define PCIX_MSI_F2 (0x13008)
704 #define PCIX_MSI_F3 (0x1300c)
705 #define PCIX_MSI_F4 (0x13010)
706 #define PCIX_MSI_F5 (0x13014)
707 #define PCIX_MSI_F6 (0x13018)
708 #define PCIX_MSI_F7 (0x1301c)
709 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
710
711 /*
712 *
713 */
714 #define PCIX_INT_VECTOR (0x10100)
715 #define PCIX_INT_MASK (0x10104)
716
717 /*
718 * Interrupt state machine and other bits.
719 */
720 #define PCIE_MISCCFG_RC (0x1206c)
721
722
723 #define ISR_INT_TARGET_STATUS \
724 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
725 #define ISR_INT_TARGET_STATUS_F1 \
726 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
727 #define ISR_INT_TARGET_STATUS_F2 \
728 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
729 #define ISR_INT_TARGET_STATUS_F3 \
730 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
731 #define ISR_INT_TARGET_STATUS_F4 \
732 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
733 #define ISR_INT_TARGET_STATUS_F5 \
734 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
735 #define ISR_INT_TARGET_STATUS_F6 \
736 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
737 #define ISR_INT_TARGET_STATUS_F7 \
738 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
739
740 #define ISR_INT_TARGET_MASK \
741 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
742 #define ISR_INT_TARGET_MASK_F1 \
743 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
744 #define ISR_INT_TARGET_MASK_F2 \
745 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
746 #define ISR_INT_TARGET_MASK_F3 \
747 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
748 #define ISR_INT_TARGET_MASK_F4 \
749 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
750 #define ISR_INT_TARGET_MASK_F5 \
751 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
752 #define ISR_INT_TARGET_MASK_F6 \
753 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
754 #define ISR_INT_TARGET_MASK_F7 \
755 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
756
757 #define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
758 #define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
759 #define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
760
761 #define ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
762
763
764 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
765 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
766
767 /*
768 * PCI Interrupt Vector Values.
769 */
770 #define PCIX_INT_VECTOR_BIT_F0 0x0080
771 #define PCIX_INT_VECTOR_BIT_F1 0x0100
772 #define PCIX_INT_VECTOR_BIT_F2 0x0200
773 #define PCIX_INT_VECTOR_BIT_F3 0x0400
774 #define PCIX_INT_VECTOR_BIT_F4 0x0800
775 #define PCIX_INT_VECTOR_BIT_F5 0x1000
776 #define PCIX_INT_VECTOR_BIT_F6 0x2000
777 #define PCIX_INT_VECTOR_BIT_F7 0x4000
778
779 /* struct qla4_8xxx_legacy_intr_set defined in ql4_def.h */
780
781 #define QLA82XX_LEGACY_INTR_CONFIG \
782 { \
783 { \
784 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
785 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
786 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
787 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
788 \
789 { \
790 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
791 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
792 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
793 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
794 \
795 { \
796 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
797 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
798 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
799 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
800 \
801 { \
802 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
803 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
804 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
805 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
806 \
807 { \
808 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
809 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
810 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
811 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
812 \
813 { \
814 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
815 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
816 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
817 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
818 \
819 { \
820 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
821 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
822 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
823 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
824 \
825 { \
826 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
827 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
828 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
829 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
830 }
831
832 /* Magic number to let user know flash is programmed */
833 #define QLA82XX_BDINFO_MAGIC 0x12345678
834 #define FW_SIZE_OFFSET (0x3e840c)
835
836 /* QLA82XX additions */
837 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
838 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
839
840 /* Minidump related */
841
842 /* Entry Type Defines */
843 #define QLA8XXX_RDNOP 0
844 #define QLA8XXX_RDCRB 1
845 #define QLA8XXX_RDMUX 2
846 #define QLA8XXX_QUEUE 3
847 #define QLA8XXX_BOARD 4
848 #define QLA8XXX_RDOCM 6
849 #define QLA8XXX_PREGS 7
850 #define QLA8XXX_L1DTG 8
851 #define QLA8XXX_L1ITG 9
852 #define QLA8XXX_L1DAT 11
853 #define QLA8XXX_L1INS 12
854 #define QLA8XXX_L2DTG 21
855 #define QLA8XXX_L2ITG 22
856 #define QLA8XXX_L2DAT 23
857 #define QLA8XXX_L2INS 24
858 #define QLA83XX_POLLRD 35
859 #define QLA83XX_RDMUX2 36
860 #define QLA83XX_POLLRDMWR 37
861 #define QLA8044_RDDFE 38
862 #define QLA8044_RDMDIO 39
863 #define QLA8044_POLLWR 40
864 #define QLA8XXX_RDROM 71
865 #define QLA8XXX_RDMEM 72
866 #define QLA8XXX_CNTRL 98
867 #define QLA83XX_TLHDR 99
868 #define QLA8XXX_RDEND 255
869
870 /* Opcodes for Control Entries.
871 * These Flags are bit fields.
872 */
873 #define QLA8XXX_DBG_OPCODE_WR 0x01
874 #define QLA8XXX_DBG_OPCODE_RW 0x02
875 #define QLA8XXX_DBG_OPCODE_AND 0x04
876 #define QLA8XXX_DBG_OPCODE_OR 0x08
877 #define QLA8XXX_DBG_OPCODE_POLL 0x10
878 #define QLA8XXX_DBG_OPCODE_RDSTATE 0x20
879 #define QLA8XXX_DBG_OPCODE_WRSTATE 0x40
880 #define QLA8XXX_DBG_OPCODE_MDSTATE 0x80
881
882 /* Driver Flags */
883 #define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
884 #define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
885 * mismatch */
886
887 /* Driver_code is for driver to write some info about the entry
888 * currently not used.
889 */
890 struct qla8xxx_minidump_entry_hdr {
891 uint32_t entry_type;
892 uint32_t entry_size;
893 uint32_t entry_capture_size;
894 struct {
895 uint8_t entry_capture_mask;
896 uint8_t entry_code;
897 uint8_t driver_code;
898 uint8_t driver_flags;
899 } d_ctrl;
900 };
901
902 /* Read CRB entry header */
903 struct qla8xxx_minidump_entry_crb {
904 struct qla8xxx_minidump_entry_hdr h;
905 uint32_t addr;
906 struct {
907 uint8_t addr_stride;
908 uint8_t state_index_a;
909 uint16_t poll_timeout;
910 } crb_strd;
911 uint32_t data_size;
912 uint32_t op_count;
913
914 struct {
915 uint8_t opcode;
916 uint8_t state_index_v;
917 uint8_t shl;
918 uint8_t shr;
919 } crb_ctrl;
920
921 uint32_t value_1;
922 uint32_t value_2;
923 uint32_t value_3;
924 };
925
926 struct qla8xxx_minidump_entry_cache {
927 struct qla8xxx_minidump_entry_hdr h;
928 uint32_t tag_reg_addr;
929 struct {
930 uint16_t tag_value_stride;
931 uint16_t init_tag_value;
932 } addr_ctrl;
933 uint32_t data_size;
934 uint32_t op_count;
935 uint32_t control_addr;
936 struct {
937 uint16_t write_value;
938 uint8_t poll_mask;
939 uint8_t poll_wait;
940 } cache_ctrl;
941 uint32_t read_addr;
942 struct {
943 uint8_t read_addr_stride;
944 uint8_t read_addr_cnt;
945 uint16_t rsvd_1;
946 } read_ctrl;
947 };
948
949 /* Read OCM */
950 struct qla8xxx_minidump_entry_rdocm {
951 struct qla8xxx_minidump_entry_hdr h;
952 uint32_t rsvd_0;
953 uint32_t rsvd_1;
954 uint32_t data_size;
955 uint32_t op_count;
956 uint32_t rsvd_2;
957 uint32_t rsvd_3;
958 uint32_t read_addr;
959 uint32_t read_addr_stride;
960 };
961
962 /* Read Memory */
963 struct qla8xxx_minidump_entry_rdmem {
964 struct qla8xxx_minidump_entry_hdr h;
965 uint32_t rsvd[6];
966 uint32_t read_addr;
967 uint32_t read_data_size;
968 };
969
970 /* Read ROM */
971 struct qla8xxx_minidump_entry_rdrom {
972 struct qla8xxx_minidump_entry_hdr h;
973 uint32_t rsvd[6];
974 uint32_t read_addr;
975 uint32_t read_data_size;
976 };
977
978 /* Mux entry */
979 struct qla8xxx_minidump_entry_mux {
980 struct qla8xxx_minidump_entry_hdr h;
981 uint32_t select_addr;
982 uint32_t rsvd_0;
983 uint32_t data_size;
984 uint32_t op_count;
985 uint32_t select_value;
986 uint32_t select_value_stride;
987 uint32_t read_addr;
988 uint32_t rsvd_1;
989 };
990
991 /* Queue entry */
992 struct qla8xxx_minidump_entry_queue {
993 struct qla8xxx_minidump_entry_hdr h;
994 uint32_t select_addr;
995 struct {
996 uint16_t queue_id_stride;
997 uint16_t rsvd_0;
998 } q_strd;
999 uint32_t data_size;
1000 uint32_t op_count;
1001 uint32_t rsvd_1;
1002 uint32_t rsvd_2;
1003 uint32_t read_addr;
1004 struct {
1005 uint8_t read_addr_stride;
1006 uint8_t read_addr_cnt;
1007 uint16_t rsvd_3;
1008 } rd_strd;
1009 };
1010
1011 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
1012 #define RQST_TMPLT_SIZE 0x0
1013 #define RQST_TMPLT 0x1
1014 #define MD_DIRECT_ROM_WINDOW 0x42110030
1015 #define MD_DIRECT_ROM_READ_BASE 0x42150000
1016 #define MD_MIU_TEST_AGT_CTRL 0x41000090
1017 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1018 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1019
1020 #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
1021 #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
1022 #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
1023 #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
1024
1025 #define MD_MIU_TEST_AGT_RDDATA_LO 0x410000A8
1026 #define MD_MIU_TEST_AGT_RDDATA_HI 0x410000AC
1027 #define MD_MIU_TEST_AGT_RDDATA_ULO 0x410000B8
1028 #define MD_MIU_TEST_AGT_RDDATA_UHI 0x410000BC
1029
1030 static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8,
1031 0x410000AC, 0x410000B8, 0x410000BC };
1032 #endif
Linux with added FPC-III support