sound/soc/codecs/mt6351.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * mt6351.h  --  mt6351 ALSA SoC audio codec driver
   4  *
   5  * Copyright (c) 2018 MediaTek Inc.
   6  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
   7  */
   8
   9 #ifndef __MT6351_H__
  10 #define __MT6351_H__
  11
  12 #define MT6351_AFE_UL_DL_CON0               (0x2000 + 0x0000)
  13 #define MT6351_AFE_DL_SRC2_CON0_H           (0x2000 + 0x0002)
  14 #define MT6351_AFE_DL_SRC2_CON0_L           (0x2000 + 0x0004)
  15 #define MT6351_AFE_DL_SDM_CON0              (0x2000 + 0x0006)
  16 #define MT6351_AFE_DL_SDM_CON1              (0x2000 + 0x0008)
  17 #define MT6351_AFE_UL_SRC_CON0_H            (0x2000 + 0x000a)
  18 #define MT6351_AFE_UL_SRC_CON0_L            (0x2000 + 0x000c)
  19 #define MT6351_AFE_UL_SRC_CON1_H            (0x2000 + 0x000e)
  20 #define MT6351_AFE_UL_SRC_CON1_L            (0x2000 + 0x0010)
  21 #define MT6351_AFE_TOP_CON0                 (0x2000 + 0x0012)
  22 #define MT6351_AUDIO_TOP_CON0               (0x2000 + 0x0014)
  23 #define MT6351_AFE_DL_SRC_MON0              (0x2000 + 0x0016)
  24 #define MT6351_AFE_DL_SDM_TEST0             (0x2000 + 0x0018)
  25 #define MT6351_AFE_MON_DEBUG0               (0x2000 + 0x001a)
  26 #define MT6351_AFUNC_AUD_CON0               (0x2000 + 0x001c)
  27 #define MT6351_AFUNC_AUD_CON1               (0x2000 + 0x001e)
  28 #define MT6351_AFUNC_AUD_CON2               (0x2000 + 0x0020)
  29 #define MT6351_AFUNC_AUD_CON3               (0x2000 + 0x0022)
  30 #define MT6351_AFUNC_AUD_CON4               (0x2000 + 0x0024)
  31 #define MT6351_AFUNC_AUD_MON0               (0x2000 + 0x0026)
  32 #define MT6351_AFUNC_AUD_MON1               (0x2000 + 0x0028)
  33 #define MT6351_AFE_UP8X_FIFO_CFG0           (0x2000 + 0x002c)
  34 #define MT6351_AFE_UP8X_FIFO_LOG_MON0       (0x2000 + 0x002e)
  35 #define MT6351_AFE_UP8X_FIFO_LOG_MON1       (0x2000 + 0x0030)
  36 #define MT6351_AFE_DL_DC_COMP_CFG0          (0x2000 + 0x0032)
  37 #define MT6351_AFE_DL_DC_COMP_CFG1          (0x2000 + 0x0034)
  38 #define MT6351_AFE_DL_DC_COMP_CFG2          (0x2000 + 0x0036)
  39 #define MT6351_AFE_PMIC_NEWIF_CFG0          (0x2000 + 0x0038)
  40 #define MT6351_AFE_PMIC_NEWIF_CFG1          (0x2000 + 0x003a)
  41 #define MT6351_AFE_PMIC_NEWIF_CFG2          (0x2000 + 0x003c)
  42 #define MT6351_AFE_PMIC_NEWIF_CFG3          (0x2000 + 0x003e)
  43 #define MT6351_AFE_SGEN_CFG0                (0x2000 + 0x0040)
  44 #define MT6351_AFE_SGEN_CFG1                (0x2000 + 0x0042)
  45 #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON0 (0x2000 + 0x004c)
  46 #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON1 (0x2000 + 0x004e)
  47 #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG0    (0x2000 + 0x0050)
  48 #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG1    (0x2000 + 0x0052)
  49 #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG2    (0x2000 + 0x0054)
  50 #define MT6351_AFE_DCCLK_CFG0               (0x2000 + 0x0090)
  51 #define MT6351_AFE_DCCLK_CFG1               (0x2000 + 0x0092)
  52 #define MT6351_AFE_HPANC_CFG0               (0x2000 + 0x0094)
  53 #define MT6351_AFE_NCP_CFG0                 (0x2000 + 0x0096)
  54 #define MT6351_AFE_NCP_CFG1                 (0x2000 + 0x0098)
  55
  56 #define MT6351_TOP_CKPDN_CON0      0x023A
  57 #define MT6351_TOP_CKPDN_CON0_SET  0x023C
  58 #define MT6351_TOP_CKPDN_CON0_CLR  0x023E
  59
  60 #define MT6351_TOP_CLKSQ           0x029A
  61 #define MT6351_TOP_CLKSQ_SET       0x029C
  62 #define MT6351_TOP_CLKSQ_CLR       0x029E
  63
  64 #define MT6351_ZCD_CON0            0x0800
  65 #define MT6351_ZCD_CON1            0x0802
  66 #define MT6351_ZCD_CON2            0x0804
  67 #define MT6351_ZCD_CON3            0x0806
  68 #define MT6351_ZCD_CON4            0x0808
  69 #define MT6351_ZCD_CON5            0x080A
  70
  71 #define MT6351_LDO_VA18_CON0       0x0A00
  72 #define MT6351_LDO_VA18_CON1       0x0A02
  73 #define MT6351_LDO_VUSB33_CON0     0x0A16
  74 #define MT6351_LDO_VUSB33_CON1     0x0A18
  75
  76 #define MT6351_AUDDEC_ANA_CON0     0x0CF2
  77 #define MT6351_AUDDEC_ANA_CON1     0x0CF4
  78 #define MT6351_AUDDEC_ANA_CON2     0x0CF6
  79 #define MT6351_AUDDEC_ANA_CON3     0x0CF8
  80 #define MT6351_AUDDEC_ANA_CON4     0x0CFA
  81 #define MT6351_AUDDEC_ANA_CON5     0x0CFC
  82 #define MT6351_AUDDEC_ANA_CON6     0x0CFE
  83 #define MT6351_AUDDEC_ANA_CON7     0x0D00
  84 #define MT6351_AUDDEC_ANA_CON8     0x0D02
  85 #define MT6351_AUDDEC_ANA_CON9     0x0D04
  86 #define MT6351_AUDDEC_ANA_CON10    0x0D06
  87
  88 #define MT6351_AUDENC_ANA_CON0     0x0D08
  89 #define MT6351_AUDENC_ANA_CON1     0x0D0A
  90 #define MT6351_AUDENC_ANA_CON2     0x0D0C
  91 #define MT6351_AUDENC_ANA_CON3     0x0D0E
  92 #define MT6351_AUDENC_ANA_CON4     0x0D10
  93 #define MT6351_AUDENC_ANA_CON5     0x0D12
  94 #define MT6351_AUDENC_ANA_CON6     0x0D14
  95 #define MT6351_AUDENC_ANA_CON7     0x0D16
  96 #define MT6351_AUDENC_ANA_CON8     0x0D18
  97 #define MT6351_AUDENC_ANA_CON9     0x0D1A
  98 #define MT6351_AUDENC_ANA_CON10    0x0D1C
  99 #define MT6351_AUDENC_ANA_CON11    0x0D1E
 100 #define MT6351_AUDENC_ANA_CON12    0x0D20
 101 #define MT6351_AUDENC_ANA_CON13    0x0D22
 102 #define MT6351_AUDENC_ANA_CON14    0x0D24
 103 #define MT6351_AUDENC_ANA_CON15    0x0D26
 104 #define MT6351_AUDENC_ANA_CON16    0x0D28
 105 #endif