sound/soc/codecs/nau8540.c

   1 /*
   2  * NAU85L40 ALSA SoC audio driver
   3  *
   4  * Copyright 2016 Nuvoton Technology Corp.
   5  * Author: John Hsu <KCHSU0@nuvoton.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/pm.h>
  17 #include <linux/i2c.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22 #include <linux/of_device.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30 #include "nau8540.h"
  31
  32
  33 #define NAU_FREF_MAX 13500000
  34 #define NAU_FVCO_MAX 100000000
  35 #define NAU_FVCO_MIN 90000000
  36
  37 /* the maximum frequency of CLK_ADC */
  38 #define CLK_ADC_MAX 6144000
  39
  40 /* scaling for mclk from sysclk_src output */
  41 static const struct nau8540_fll_attr mclk_src_scaling[] = {
  42         { 1, 0x0 },
  43         { 2, 0x2 },
  44         { 4, 0x3 },
  45         { 8, 0x4 },
  46         { 16, 0x5 },
  47         { 32, 0x6 },
  48         { 3, 0x7 },
  49         { 6, 0xa },
  50         { 12, 0xb },
  51         { 24, 0xc },
  52 };
  53
  54 /* ratio for input clk freq */
  55 static const struct nau8540_fll_attr fll_ratio[] = {
  56         { 512000, 0x01 },
  57         { 256000, 0x02 },
  58         { 128000, 0x04 },
  59         { 64000, 0x08 },
  60         { 32000, 0x10 },
  61         { 8000, 0x20 },
  62         { 4000, 0x40 },
  63 };
  64
  65 static const struct nau8540_fll_attr fll_pre_scalar[] = {
  66         { 1, 0x0 },
  67         { 2, 0x1 },
  68         { 4, 0x2 },
  69         { 8, 0x3 },
  70 };
  71
  72 /* over sampling rate */
  73 static const struct nau8540_osr_attr osr_adc_sel[] = {
  74         { 32, 3 },      /* OSR 32, SRC 1/8 */
  75         { 64, 2 },      /* OSR 64, SRC 1/4 */
  76         { 128, 1 },     /* OSR 128, SRC 1/2 */
  77         { 256, 0 },     /* OSR 256, SRC 1 */
  78 };
  79
  80 static const struct reg_default nau8540_reg_defaults[] = {
  81         {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
  82         {NAU8540_REG_CLOCK_CTRL, 0x0000},
  83         {NAU8540_REG_CLOCK_SRC, 0x0000},
  84         {NAU8540_REG_FLL1, 0x0001},
  85         {NAU8540_REG_FLL2, 0x3126},
  86         {NAU8540_REG_FLL3, 0x0008},
  87         {NAU8540_REG_FLL4, 0x0010},
  88         {NAU8540_REG_FLL5, 0xC000},
  89         {NAU8540_REG_FLL6, 0x6000},
  90         {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
  91         {NAU8540_REG_PCM_CTRL0, 0x000B},
  92         {NAU8540_REG_PCM_CTRL1, 0x3010},
  93         {NAU8540_REG_PCM_CTRL2, 0x0800},
  94         {NAU8540_REG_PCM_CTRL3, 0x0000},
  95         {NAU8540_REG_PCM_CTRL4, 0x000F},
  96         {NAU8540_REG_ALC_CONTROL_1, 0x0000},
  97         {NAU8540_REG_ALC_CONTROL_2, 0x700B},
  98         {NAU8540_REG_ALC_CONTROL_3, 0x0022},
  99         {NAU8540_REG_ALC_CONTROL_4, 0x1010},
 100         {NAU8540_REG_ALC_CONTROL_5, 0x1010},
 101         {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
 102         {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
 103         {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
 104         {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
 105         {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
 106         {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
 107         {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
 108         {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
 109         {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
 110         {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
 111         {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
 112         {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
 113         {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
 114         {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
 115         {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
 116         {NAU8540_REG_DIGITAL_MUX, 0x00E4},
 117         {NAU8540_REG_GPIO_CTRL, 0x0000},
 118         {NAU8540_REG_MISC_CTRL, 0x0000},
 119         {NAU8540_REG_I2C_CTRL, 0xEFFF},
 120         {NAU8540_REG_VMID_CTRL, 0x0000},
 121         {NAU8540_REG_MUTE, 0x0000},
 122         {NAU8540_REG_ANALOG_ADC1, 0x0011},
 123         {NAU8540_REG_ANALOG_ADC2, 0x0020},
 124         {NAU8540_REG_ANALOG_PWR, 0x0000},
 125         {NAU8540_REG_MIC_BIAS, 0x0004},
 126         {NAU8540_REG_REFERENCE, 0x0000},
 127         {NAU8540_REG_FEPGA1, 0x0000},
 128         {NAU8540_REG_FEPGA2, 0x0000},
 129         {NAU8540_REG_FEPGA3, 0x0101},
 130         {NAU8540_REG_FEPGA4, 0x0101},
 131         {NAU8540_REG_PWR, 0x0000},
 132 };
 133
 134 static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
 135 {
 136         switch (reg) {
 137         case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
 138         case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
 139         case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
 140         case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
 141         case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
 142         case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
 143         case NAU8540_REG_I2C_DEVICE_ID:
 144         case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
 145         case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
 146                 return true;
 147         default:
 148                 return false;
 149         }
 150
 151 }
 152
 153 static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
 154 {
 155         switch (reg) {
 156         case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
 157         case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
 158         case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
 159         case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
 160         case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
 161         case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
 162         case NAU8540_REG_RST:
 163         case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
 164         case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
 165                 return true;
 166         default:
 167                 return false;
 168         }
 169 }
 170
 171 static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
 172 {
 173         switch (reg) {
 174         case NAU8540_REG_SW_RESET:
 175         case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
 176         case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
 177         case NAU8540_REG_I2C_DEVICE_ID:
 178         case NAU8540_REG_RST:
 179                 return true;
 180         default:
 181                 return false;
 182         }
 183 }
 184
 185
 186 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
 187 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
 188
 189 static const struct snd_kcontrol_new nau8540_snd_controls[] = {
 190         SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
 191                 0, 0x520, 0, adc_vol_tlv),
 192         SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
 193                 0, 0x520, 0, adc_vol_tlv),
 194         SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
 195                 0, 0x520, 0, adc_vol_tlv),
 196         SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
 197                 0, 0x520, 0, adc_vol_tlv),
 198
 199         SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
 200                 0, 0x25, 0, fepga_gain_tlv),
 201         SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
 202                 8, 0x25, 0, fepga_gain_tlv),
 203         SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
 204                 0, 0x25, 0, fepga_gain_tlv),
 205         SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
 206                 8, 0x25, 0, fepga_gain_tlv),
 207 };
 208
 209 static const char * const adc_channel[] = {
 210         "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
 211 };
 212 static SOC_ENUM_SINGLE_DECL(
 213         digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
 214
 215 static const struct snd_kcontrol_new digital_ch4_mux =
 216         SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
 217
 218 static SOC_ENUM_SINGLE_DECL(
 219         digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
 220
 221 static const struct snd_kcontrol_new digital_ch3_mux =
 222         SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
 223
 224 static SOC_ENUM_SINGLE_DECL(
 225         digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
 226
 227 static const struct snd_kcontrol_new digital_ch2_mux =
 228         SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
 229
 230 static SOC_ENUM_SINGLE_DECL(
 231         digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
 232
 233 static const struct snd_kcontrol_new digital_ch1_mux =
 234         SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
 235
 236 static int adc_power_control(struct snd_soc_dapm_widget *w,
 237                 struct snd_kcontrol *k, int  event)
 238 {
 239         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 240         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 241
 242         if (SND_SOC_DAPM_EVENT_ON(event)) {
 243                 msleep(300);
 244                 /* DO12 and DO34 pad output enable */
 245                 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
 246                         NAU8540_I2S_DO12_TRI, 0);
 247                 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
 248                         NAU8540_I2S_DO34_TRI, 0);
 249         } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
 250                 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
 251                         NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
 252                 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
 253                         NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
 254         }
 255         return 0;
 256 }
 257
 258 static int aiftx_power_control(struct snd_soc_dapm_widget *w,
 259                 struct snd_kcontrol *k, int  event)
 260 {
 261         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 262         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 263
 264         if (SND_SOC_DAPM_EVENT_OFF(event)) {
 265                 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
 266                 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
 267         }
 268         return 0;
 269 }
 270
 271 static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
 272         SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
 273         SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
 274
 275         SND_SOC_DAPM_INPUT("MIC1"),
 276         SND_SOC_DAPM_INPUT("MIC2"),
 277         SND_SOC_DAPM_INPUT("MIC3"),
 278         SND_SOC_DAPM_INPUT("MIC4"),
 279
 280         SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
 281         SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
 282         SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
 283         SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
 284
 285         SND_SOC_DAPM_ADC_E("ADC1", NULL,
 286                 NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
 287                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 288         SND_SOC_DAPM_ADC_E("ADC2", NULL,
 289                 NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
 290                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 291         SND_SOC_DAPM_ADC_E("ADC3", NULL,
 292                 NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
 293                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 294         SND_SOC_DAPM_ADC_E("ADC4", NULL,
 295                 NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
 296                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 297
 298         SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
 299         SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
 300         SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
 301         SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
 302
 303         SND_SOC_DAPM_MUX("Digital CH4 Mux",
 304                 SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
 305         SND_SOC_DAPM_MUX("Digital CH3 Mux",
 306                 SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
 307         SND_SOC_DAPM_MUX("Digital CH2 Mux",
 308                 SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
 309         SND_SOC_DAPM_MUX("Digital CH1 Mux",
 310                 SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
 311
 312         SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
 313                 aiftx_power_control, SND_SOC_DAPM_POST_PMD),
 314 };
 315
 316 static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
 317         {"Frontend PGA1", NULL, "MIC1"},
 318         {"Frontend PGA2", NULL, "MIC2"},
 319         {"Frontend PGA3", NULL, "MIC3"},
 320         {"Frontend PGA4", NULL, "MIC4"},
 321
 322         {"ADC1", NULL, "Frontend PGA1"},
 323         {"ADC2", NULL, "Frontend PGA2"},
 324         {"ADC3", NULL, "Frontend PGA3"},
 325         {"ADC4", NULL, "Frontend PGA4"},
 326
 327         {"ADC CH1", NULL, "ADC1"},
 328         {"ADC CH2", NULL, "ADC2"},
 329         {"ADC CH3", NULL, "ADC3"},
 330         {"ADC CH4", NULL, "ADC4"},
 331
 332         {"ADC1", NULL, "MICBIAS1"},
 333         {"ADC2", NULL, "MICBIAS1"},
 334         {"ADC3", NULL, "MICBIAS2"},
 335         {"ADC4", NULL, "MICBIAS2"},
 336
 337         {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
 338         {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
 339         {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
 340         {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
 341
 342         {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
 343         {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
 344         {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
 345         {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
 346
 347         {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
 348         {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
 349         {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
 350         {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
 351
 352         {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
 353         {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
 354         {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
 355         {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
 356
 357         {"AIFTX", NULL, "Digital CH1 Mux"},
 358         {"AIFTX", NULL, "Digital CH2 Mux"},
 359         {"AIFTX", NULL, "Digital CH3 Mux"},
 360         {"AIFTX", NULL, "Digital CH4 Mux"},
 361 };
 362
 363 static int nau8540_clock_check(struct nau8540 *nau8540, int rate, int osr)
 364 {
 365         int osrate;
 366
 367         if (osr >= ARRAY_SIZE(osr_adc_sel))
 368                 return -EINVAL;
 369         osrate = osr_adc_sel[osr].osr;
 370
 371         if (rate * osr > CLK_ADC_MAX) {
 372                 dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n");
 373                 return -EINVAL;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int nau8540_hw_params(struct snd_pcm_substream *substream,
 380         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 381 {
 382         struct snd_soc_component *component = dai->component;
 383         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 384         unsigned int val_len = 0, osr;
 385
 386         /* CLK_ADC = OSR * FS
 387          * ADC clock frequency is defined as Over Sampling Rate (OSR)
 388          * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
 389          * values must be selected such that the maximum frequency is less
 390          * than 6.144 MHz.
 391          */
 392         regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
 393         osr &= NAU8540_ADC_OSR_MASK;
 394         if (nau8540_clock_check(nau8540, params_rate(params), osr))
 395                 return -EINVAL;
 396         regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
 397                 NAU8540_CLK_ADC_SRC_MASK,
 398                 osr_adc_sel[osr].clk_src << NAU8540_CLK_ADC_SRC_SFT);
 399
 400         switch (params_width(params)) {
 401         case 16:
 402                 val_len |= NAU8540_I2S_DL_16;
 403                 break;
 404         case 20:
 405                 val_len |= NAU8540_I2S_DL_20;
 406                 break;
 407         case 24:
 408                 val_len |= NAU8540_I2S_DL_24;
 409                 break;
 410         case 32:
 411                 val_len |= NAU8540_I2S_DL_32;
 412                 break;
 413         default:
 414                 return -EINVAL;
 415         }
 416
 417         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
 418                 NAU8540_I2S_DL_MASK, val_len);
 419
 420         return 0;
 421 }
 422
 423 static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 424 {
 425         struct snd_soc_component *component = dai->component;
 426         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 427         unsigned int ctrl1_val = 0, ctrl2_val = 0;
 428
 429         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 430         case SND_SOC_DAIFMT_CBM_CFM:
 431                 ctrl2_val |= NAU8540_I2S_MS_MASTER;
 432                 break;
 433         case SND_SOC_DAIFMT_CBS_CFS:
 434                 break;
 435         default:
 436                 return -EINVAL;
 437         }
 438
 439         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 440         case SND_SOC_DAIFMT_NB_NF:
 441                 break;
 442         case SND_SOC_DAIFMT_IB_NF:
 443                 ctrl1_val |= NAU8540_I2S_BP_INV;
 444                 break;
 445         default:
 446                 return -EINVAL;
 447         }
 448
 449         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 450         case SND_SOC_DAIFMT_I2S:
 451                 ctrl1_val |= NAU8540_I2S_DF_I2S;
 452                 break;
 453         case SND_SOC_DAIFMT_LEFT_J:
 454                 ctrl1_val |= NAU8540_I2S_DF_LEFT;
 455                 break;
 456         case SND_SOC_DAIFMT_RIGHT_J:
 457                 ctrl1_val |= NAU8540_I2S_DF_RIGTH;
 458                 break;
 459         case SND_SOC_DAIFMT_DSP_A:
 460                 ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
 461                 break;
 462         case SND_SOC_DAIFMT_DSP_B:
 463                 ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
 464                 ctrl1_val |= NAU8540_I2S_PCMB_EN;
 465                 break;
 466         default:
 467                 return -EINVAL;
 468         }
 469
 470         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
 471                 NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
 472                 NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
 473         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
 474                 NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
 475         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
 476                 NAU8540_I2S_DO34_OE, 0);
 477
 478         return 0;
 479 }
 480
 481 /**
 482  * nau8540_set_tdm_slot - configure DAI TX TDM.
 483  * @dai: DAI
 484  * @tx_mask: bitmask representing active TX slots. Ex.
 485  *                 0xf for normal 4 channel TDM.
 486  *                 0xf0 for shifted 4 channel TDM
 487  * @rx_mask: no used.
 488  * @slots: Number of slots in use.
 489  * @slot_width: Width in bits for each slot.
 490  *
 491  * Configures a DAI for TDM operation. Only support 4 slots TDM.
 492  */
 493 static int nau8540_set_tdm_slot(struct snd_soc_dai *dai,
 494         unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
 495 {
 496         struct snd_soc_component *component = dai->component;
 497         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 498         unsigned int ctrl2_val = 0, ctrl4_val = 0;
 499
 500         if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
 501                 return -EINVAL;
 502
 503         ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
 504         if (tx_mask & 0xf0) {
 505                 ctrl2_val = 4 * slot_width;
 506                 ctrl4_val |= (tx_mask >> 4);
 507         } else {
 508                 ctrl4_val |= tx_mask;
 509         }
 510         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
 511                 NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
 512                 NAU8540_TDM_TX_MASK, ctrl4_val);
 513         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
 514                 NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
 515         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
 516                 NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
 517                 NAU8540_I2S_DO34_OE | ctrl2_val);
 518
 519         return 0;
 520 }
 521
 522
 523 static const struct snd_soc_dai_ops nau8540_dai_ops = {
 524         .hw_params = nau8540_hw_params,
 525         .set_fmt = nau8540_set_fmt,
 526         .set_tdm_slot = nau8540_set_tdm_slot,
 527 };
 528
 529 #define NAU8540_RATES SNDRV_PCM_RATE_8000_48000
 530 #define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 531          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 532
 533 static struct snd_soc_dai_driver nau8540_dai = {
 534         .name = "nau8540-hifi",
 535         .capture = {
 536                 .stream_name = "Capture",
 537                 .channels_min = 1,
 538                 .channels_max = 4,
 539                 .rates = NAU8540_RATES,
 540                 .formats = NAU8540_FORMATS,
 541         },
 542         .ops = &nau8540_dai_ops,
 543 };
 544
 545 /**
 546  * nau8540_calc_fll_param - Calculate FLL parameters.
 547  * @fll_in: external clock provided to codec.
 548  * @fs: sampling rate.
 549  * @fll_param: Pointer to structure of FLL parameters.
 550  *
 551  * Calculate FLL parameters to configure codec.
 552  *
 553  * Returns 0 for success or negative error code.
 554  */
 555 static int nau8540_calc_fll_param(unsigned int fll_in,
 556         unsigned int fs, struct nau8540_fll *fll_param)
 557 {
 558         u64 fvco, fvco_max;
 559         unsigned int fref, i, fvco_sel;
 560
 561         /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
 562          * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
 563          * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
 564          */
 565         for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
 566                 fref = fll_in / fll_pre_scalar[i].param;
 567                 if (fref <= NAU_FREF_MAX)
 568                         break;
 569         }
 570         if (i == ARRAY_SIZE(fll_pre_scalar))
 571                 return -EINVAL;
 572         fll_param->clk_ref_div = fll_pre_scalar[i].val;
 573
 574         /* Choose the FLL ratio based on FREF */
 575         for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
 576                 if (fref >= fll_ratio[i].param)
 577                         break;
 578         }
 579         if (i == ARRAY_SIZE(fll_ratio))
 580                 return -EINVAL;
 581         fll_param->ratio = fll_ratio[i].val;
 582
 583         /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
 584          * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
 585          * guaranteed across the full range of operation.
 586          * FDCO = freq_out * 2 * mclk_src_scaling
 587          */
 588         fvco_max = 0;
 589         fvco_sel = ARRAY_SIZE(mclk_src_scaling);
 590         for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
 591                 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
 592                 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
 593                         fvco_max < fvco) {
 594                         fvco_max = fvco;
 595                         fvco_sel = i;
 596                 }
 597         }
 598         if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
 599                 return -EINVAL;
 600         fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
 601
 602         /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
 603          * input based on FDCO, FREF and FLL ratio.
 604          */
 605         fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
 606         fll_param->fll_int = (fvco >> 16) & 0x3FF;
 607         fll_param->fll_frac = fvco & 0xFFFF;
 608         return 0;
 609 }
 610
 611 static void nau8540_fll_apply(struct regmap *regmap,
 612         struct nau8540_fll *fll_param)
 613 {
 614         regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
 615                 NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
 616                 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
 617         regmap_update_bits(regmap, NAU8540_REG_FLL1,
 618                 NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
 619                 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
 620         /* FLL 16-bit fractional input */
 621         regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
 622         /* FLL 10-bit integer input */
 623         regmap_update_bits(regmap, NAU8540_REG_FLL3,
 624                 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
 625         /* FLL pre-scaler */
 626         regmap_update_bits(regmap, NAU8540_REG_FLL4,
 627                 NAU8540_FLL_REF_DIV_MASK,
 628                 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
 629         regmap_update_bits(regmap, NAU8540_REG_FLL5,
 630                 NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
 631         regmap_update_bits(regmap,
 632                 NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
 633         if (fll_param->fll_frac) {
 634                 regmap_update_bits(regmap, NAU8540_REG_FLL5,
 635                         NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
 636                         NAU8540_FLL_FTR_SW_MASK,
 637                         NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
 638                         NAU8540_FLL_FTR_SW_FILTER);
 639                 regmap_update_bits(regmap, NAU8540_REG_FLL6,
 640                         NAU8540_SDM_EN | NAU8540_CUTOFF500,
 641                         NAU8540_SDM_EN | NAU8540_CUTOFF500);
 642         } else {
 643                 regmap_update_bits(regmap, NAU8540_REG_FLL5,
 644                         NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
 645                         NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
 646                 regmap_update_bits(regmap, NAU8540_REG_FLL6,
 647                         NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
 648         }
 649 }
 650
 651 /* freq_out must be 256*Fs in order to achieve the best performance */
 652 static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source,
 653                 unsigned int freq_in, unsigned int freq_out)
 654 {
 655         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 656         struct nau8540_fll fll_param;
 657         int ret, fs;
 658
 659         switch (pll_id) {
 660         case NAU8540_CLK_FLL_MCLK:
 661                 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
 662                         NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
 663                         NAU8540_FLL_CLK_SRC_MCLK | 0);
 664                 break;
 665
 666         case NAU8540_CLK_FLL_BLK:
 667                 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
 668                         NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
 669                         NAU8540_FLL_CLK_SRC_BLK |
 670                         (0xf << NAU8540_GAIN_ERR_SFT));
 671                 break;
 672
 673         case NAU8540_CLK_FLL_FS:
 674                 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
 675                         NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
 676                         NAU8540_FLL_CLK_SRC_FS |
 677                         (0xf << NAU8540_GAIN_ERR_SFT));
 678                 break;
 679
 680         default:
 681                 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
 682                 return -EINVAL;
 683         }
 684         dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
 685                 freq_out, pll_id);
 686
 687         fs = freq_out / 256;
 688         ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
 689         if (ret < 0) {
 690                 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
 691                 return ret;
 692         }
 693         dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
 694                 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
 695                 fll_param.fll_int, fll_param.clk_ref_div);
 696
 697         nau8540_fll_apply(nau8540->regmap, &fll_param);
 698         mdelay(2);
 699         regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
 700                 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
 701
 702         return 0;
 703 }
 704
 705 static int nau8540_set_sysclk(struct snd_soc_component *component,
 706         int clk_id, int source, unsigned int freq, int dir)
 707 {
 708         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 709
 710         switch (clk_id) {
 711         case NAU8540_CLK_DIS:
 712         case NAU8540_CLK_MCLK:
 713                 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
 714                         NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
 715                 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
 716                         NAU8540_DCO_EN, 0);
 717                 break;
 718
 719         case NAU8540_CLK_INTERNAL:
 720                 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
 721                         NAU8540_DCO_EN, NAU8540_DCO_EN);
 722                 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
 723                         NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
 724                 break;
 725
 726         default:
 727                 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
 728                 return -EINVAL;
 729         }
 730
 731         dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
 732                 freq, clk_id);
 733
 734         return 0;
 735 }
 736
 737 static void nau8540_reset_chip(struct regmap *regmap)
 738 {
 739         regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
 740         regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
 741 }
 742
 743 static void nau8540_init_regs(struct nau8540 *nau8540)
 744 {
 745         struct regmap *regmap = nau8540->regmap;
 746
 747         /* Enable Bias/VMID/VMID Tieoff */
 748         regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
 749                 NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
 750                 NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
 751         regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
 752                 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
 753                 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
 754         mdelay(2);
 755         regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
 756                 NAU8540_PU_PRE, NAU8540_PU_PRE);
 757         regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
 758                 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
 759                 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
 760         /* ADC OSR selection, CLK_ADC = Fs * OSR;
 761          * Channel time alignment enable.
 762          */
 763         regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
 764                 NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
 765                 NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
 766         /* PGA input mode selection */
 767         regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
 768                 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
 769                 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
 770         regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
 771                 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
 772                 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
 773         /* DO12 and DO34 pad output disable */
 774         regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
 775                 NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
 776         regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
 777                 NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
 778 }
 779
 780 static int __maybe_unused nau8540_suspend(struct snd_soc_component *component)
 781 {
 782         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 783
 784         regcache_cache_only(nau8540->regmap, true);
 785         regcache_mark_dirty(nau8540->regmap);
 786
 787         return 0;
 788 }
 789
 790 static int __maybe_unused nau8540_resume(struct snd_soc_component *component)
 791 {
 792         struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
 793
 794         regcache_cache_only(nau8540->regmap, false);
 795         regcache_sync(nau8540->regmap);
 796
 797         return 0;
 798 }
 799
 800 static const struct snd_soc_component_driver nau8540_component_driver = {
 801         .set_sysclk             = nau8540_set_sysclk,
 802         .set_pll                = nau8540_set_pll,
 803         .suspend                = nau8540_suspend,
 804         .resume                 = nau8540_resume,
 805         .controls               = nau8540_snd_controls,
 806         .num_controls           = ARRAY_SIZE(nau8540_snd_controls),
 807         .dapm_widgets           = nau8540_dapm_widgets,
 808         .num_dapm_widgets       = ARRAY_SIZE(nau8540_dapm_widgets),
 809         .dapm_routes            = nau8540_dapm_routes,
 810         .num_dapm_routes        = ARRAY_SIZE(nau8540_dapm_routes),
 811         .suspend_bias_off       = 1,
 812         .idle_bias_on           = 1,
 813         .use_pmdown_time        = 1,
 814         .endianness             = 1,
 815         .non_legacy_dai_naming  = 1,
 816 };
 817
 818 static const struct regmap_config nau8540_regmap_config = {
 819         .val_bits = 16,
 820         .reg_bits = 16,
 821
 822         .max_register = NAU8540_REG_MAX,
 823         .readable_reg = nau8540_readable_reg,
 824         .writeable_reg = nau8540_writeable_reg,
 825         .volatile_reg = nau8540_volatile_reg,
 826
 827         .cache_type = REGCACHE_RBTREE,
 828         .reg_defaults = nau8540_reg_defaults,
 829         .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
 830 };
 831
 832 static int nau8540_i2c_probe(struct i2c_client *i2c,
 833         const struct i2c_device_id *id)
 834 {
 835         struct device *dev = &i2c->dev;
 836         struct nau8540 *nau8540 = dev_get_platdata(dev);
 837         int ret, value;
 838
 839         if (!nau8540) {
 840                 nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
 841                 if (!nau8540)
 842                         return -ENOMEM;
 843         }
 844         i2c_set_clientdata(i2c, nau8540);
 845
 846         nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
 847         if (IS_ERR(nau8540->regmap))
 848                 return PTR_ERR(nau8540->regmap);
 849         ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
 850         if (ret < 0) {
 851                 dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
 852                         ret);
 853                 return ret;
 854         }
 855
 856         nau8540->dev = dev;
 857         nau8540_reset_chip(nau8540->regmap);
 858         nau8540_init_regs(nau8540);
 859
 860         return devm_snd_soc_register_component(dev,
 861                 &nau8540_component_driver, &nau8540_dai, 1);
 862 }
 863
 864 static const struct i2c_device_id nau8540_i2c_ids[] = {
 865         { "nau8540", 0 },
 866         { }
 867 };
 868 MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
 869
 870 #ifdef CONFIG_OF
 871 static const struct of_device_id nau8540_of_ids[] = {
 872         { .compatible = "nuvoton,nau8540", },
 873         {}
 874 };
 875 MODULE_DEVICE_TABLE(of, nau8540_of_ids);
 876 #endif
 877
 878 static struct i2c_driver nau8540_i2c_driver = {
 879         .driver = {
 880                 .name = "nau8540",
 881                 .of_match_table = of_match_ptr(nau8540_of_ids),
 882         },
 883         .probe = nau8540_i2c_probe,
 884         .id_table = nau8540_i2c_ids,
 885 };
 886 module_i2c_driver(nau8540_i2c_driver);
 887
 888 MODULE_DESCRIPTION("ASoC NAU85L40 driver");
 889 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
 890 MODULE_LICENSE("GPL v2");