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media: v4l: rcar_fdp1: Change platform dependency to ARCH_RENESAS
[linux/fpc-iii.git] / sound / soc / codecs / rt286.c
blob0b0f748bffbe7015430b25c9333d734a4488537c
1 /*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dmi.h>
21 #include <linux/acpi.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/jack.h>
30 #include <linux/workqueue.h>
31 #include <sound/rt286.h>
32
33 #include "rl6347a.h"
34 #include "rt286.h"
35
36 #define RT286_VENDOR_ID 0x10ec0286
37 #define RT288_VENDOR_ID 0x10ec0288
38
39 struct rt286_priv {
40 struct reg_default *index_cache;
41 int index_cache_size;
42 struct regmap *regmap;
43 struct snd_soc_component *component;
44 struct rt286_platform_data pdata;
45 struct i2c_client *i2c;
46 struct snd_soc_jack *jack;
47 struct delayed_work jack_detect_work;
48 int sys_clk;
49 int clk_id;
50 };
51
52 static const struct reg_default rt286_index_def[] = {
53 { 0x01, 0xaaaa },
54 { 0x02, 0x8aaa },
55 { 0x03, 0x0002 },
56 { 0x04, 0xaf01 },
57 { 0x08, 0x000d },
58 { 0x09, 0xd810 },
59 { 0x0a, 0x0120 },
60 { 0x0b, 0x0000 },
61 { 0x0d, 0x2800 },
62 { 0x0f, 0x0000 },
63 { 0x19, 0x0a17 },
64 { 0x20, 0x0020 },
65 { 0x33, 0x0208 },
66 { 0x49, 0x0004 },
67 { 0x4f, 0x50e9 },
68 { 0x50, 0x2000 },
69 { 0x63, 0x2902 },
70 { 0x67, 0x1111 },
71 { 0x68, 0x1016 },
72 { 0x69, 0x273f },
73 };
74 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
75
76 static const struct reg_default rt286_reg[] = {
77 { 0x00170500, 0x00000400 },
78 { 0x00220000, 0x00000031 },
79 { 0x00239000, 0x0000007f },
80 { 0x0023a000, 0x0000007f },
81 { 0x00270500, 0x00000400 },
82 { 0x00370500, 0x00000400 },
83 { 0x00870500, 0x00000400 },
84 { 0x00920000, 0x00000031 },
85 { 0x00935000, 0x000000c3 },
86 { 0x00936000, 0x000000c3 },
87 { 0x00970500, 0x00000400 },
88 { 0x00b37000, 0x00000097 },
89 { 0x00b37200, 0x00000097 },
90 { 0x00b37300, 0x00000097 },
91 { 0x00c37000, 0x00000000 },
92 { 0x00c37100, 0x00000080 },
93 { 0x01270500, 0x00000400 },
94 { 0x01370500, 0x00000400 },
95 { 0x01371f00, 0x411111f0 },
96 { 0x01439000, 0x00000080 },
97 { 0x0143a000, 0x00000080 },
98 { 0x01470700, 0x00000000 },
99 { 0x01470500, 0x00000400 },
100 { 0x01470c00, 0x00000000 },
101 { 0x01470100, 0x00000000 },
102 { 0x01837000, 0x00000000 },
103 { 0x01870500, 0x00000400 },
104 { 0x02050000, 0x00000000 },
105 { 0x02139000, 0x00000080 },
106 { 0x0213a000, 0x00000080 },
107 { 0x02170100, 0x00000000 },
108 { 0x02170500, 0x00000400 },
109 { 0x02170700, 0x00000000 },
110 { 0x02270100, 0x00000000 },
111 { 0x02370100, 0x00000000 },
112 { 0x01870700, 0x00000020 },
113 { 0x00830000, 0x000000c3 },
114 { 0x00930000, 0x000000c3 },
115 { 0x01270700, 0x00000000 },
116 };
117
118 static bool rt286_volatile_register(struct device *dev, unsigned int reg)
119 {
120 switch (reg) {
121 case 0 ... 0xff:
122 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
123 case RT286_GET_HP_SENSE:
124 case RT286_GET_MIC1_SENSE:
125 case RT286_PROC_COEF:
126 return true;
127 default:
128 return false;
129 }
130
131
132 }
133
134 static bool rt286_readable_register(struct device *dev, unsigned int reg)
135 {
136 switch (reg) {
137 case 0 ... 0xff:
138 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
139 case RT286_GET_HP_SENSE:
140 case RT286_GET_MIC1_SENSE:
141 case RT286_SET_AUDIO_POWER:
142 case RT286_SET_HPO_POWER:
143 case RT286_SET_SPK_POWER:
144 case RT286_SET_DMIC1_POWER:
145 case RT286_SPK_MUX:
146 case RT286_HPO_MUX:
147 case RT286_ADC0_MUX:
148 case RT286_ADC1_MUX:
149 case RT286_SET_MIC1:
150 case RT286_SET_PIN_HPO:
151 case RT286_SET_PIN_SPK:
152 case RT286_SET_PIN_DMIC1:
153 case RT286_SPK_EAPD:
154 case RT286_SET_AMP_GAIN_HPO:
155 case RT286_SET_DMIC2_DEFAULT:
156 case RT286_DACL_GAIN:
157 case RT286_DACR_GAIN:
158 case RT286_ADCL_GAIN:
159 case RT286_ADCR_GAIN:
160 case RT286_MIC_GAIN:
161 case RT286_SPOL_GAIN:
162 case RT286_SPOR_GAIN:
163 case RT286_HPOL_GAIN:
164 case RT286_HPOR_GAIN:
165 case RT286_F_DAC_SWITCH:
166 case RT286_F_RECMIX_SWITCH:
167 case RT286_REC_MIC_SWITCH:
168 case RT286_REC_I2S_SWITCH:
169 case RT286_REC_LINE_SWITCH:
170 case RT286_REC_BEEP_SWITCH:
171 case RT286_DAC_FORMAT:
172 case RT286_ADC_FORMAT:
173 case RT286_COEF_INDEX:
174 case RT286_PROC_COEF:
175 case RT286_SET_AMP_GAIN_ADC_IN1:
176 case RT286_SET_AMP_GAIN_ADC_IN2:
177 case RT286_SET_POWER(RT286_DAC_OUT1):
178 case RT286_SET_POWER(RT286_DAC_OUT2):
179 case RT286_SET_POWER(RT286_ADC_IN1):
180 case RT286_SET_POWER(RT286_ADC_IN2):
181 case RT286_SET_POWER(RT286_DMIC2):
182 case RT286_SET_POWER(RT286_MIC1):
183 return true;
184 default:
185 return false;
186 }
187 }
188
189 #ifdef CONFIG_PM
190 static void rt286_index_sync(struct snd_soc_component *component)
191 {
192 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
193 int i;
194
195 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
196 snd_soc_component_write(component, rt286->index_cache[i].reg,
197 rt286->index_cache[i].def);
198 }
199 }
200 #endif
201
202 static int rt286_support_power_controls[] = {
203 RT286_DAC_OUT1,
204 RT286_DAC_OUT2,
205 RT286_ADC_IN1,
206 RT286_ADC_IN2,
207 RT286_MIC1,
208 RT286_DMIC1,
209 RT286_DMIC2,
210 RT286_SPK_OUT,
211 RT286_HP_OUT,
212 };
213 #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
214
215 static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
216 {
217 struct snd_soc_dapm_context *dapm;
218 unsigned int val, buf;
219
220 *hp = false;
221 *mic = false;
222
223 if (!rt286->component)
224 return -EINVAL;
225
226 dapm = snd_soc_component_get_dapm(rt286->component);
227
228 if (rt286->pdata.cbj_en) {
229 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
230 *hp = buf & 0x80000000;
231 if (*hp) {
232 /* power on HV,VERF */
233 regmap_update_bits(rt286->regmap,
234 RT286_DC_GAIN, 0x200, 0x200);
235
236 snd_soc_dapm_force_enable_pin(dapm, "HV");
237 snd_soc_dapm_force_enable_pin(dapm, "VREF");
238 /* power LDO1 */
239 snd_soc_dapm_force_enable_pin(dapm, "LDO1");
240 snd_soc_dapm_sync(dapm);
241
242 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
243 msleep(50);
244
245 regmap_update_bits(rt286->regmap,
246 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
247 msleep(300);
248 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
249
250 if (0x0070 == (val & 0x0070)) {
251 *mic = true;
252 } else {
253 regmap_update_bits(rt286->regmap,
254 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
255 msleep(300);
256 regmap_read(rt286->regmap,
257 RT286_CBJ_CTRL2, &val);
258 if (0x0070 == (val & 0x0070))
259 *mic = true;
260 else
261 *mic = false;
262 }
263 regmap_update_bits(rt286->regmap,
264 RT286_DC_GAIN, 0x200, 0x0);
265
266 } else {
267 *mic = false;
268 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
269 regmap_update_bits(rt286->regmap,
270 RT286_CBJ_CTRL1, 0x0400, 0x0000);
271 }
272 } else {
273 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
274 *hp = buf & 0x80000000;
275 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
276 *mic = buf & 0x80000000;
277 }
278 if (!*mic) {
279 snd_soc_dapm_disable_pin(dapm, "HV");
280 snd_soc_dapm_disable_pin(dapm, "VREF");
281 }
282 if (!*hp)
283 snd_soc_dapm_disable_pin(dapm, "LDO1");
284 snd_soc_dapm_sync(dapm);
285
286 return 0;
287 }
288
289 static void rt286_jack_detect_work(struct work_struct *work)
290 {
291 struct rt286_priv *rt286 =
292 container_of(work, struct rt286_priv, jack_detect_work.work);
293 int status = 0;
294 bool hp = false;
295 bool mic = false;
296
297 rt286_jack_detect(rt286, &hp, &mic);
298
299 if (hp == true)
300 status |= SND_JACK_HEADPHONE;
301
302 if (mic == true)
303 status |= SND_JACK_MICROPHONE;
304
305 snd_soc_jack_report(rt286->jack, status,
306 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
307 }
308
309 int rt286_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
310 {
311 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
312 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
313
314 rt286->jack = jack;
315
316 if (jack) {
317 /* enable IRQ */
318 if (rt286->jack->status & SND_JACK_HEADPHONE)
319 snd_soc_dapm_force_enable_pin(dapm, "LDO1");
320 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
321 /* Send an initial empty report */
322 snd_soc_jack_report(rt286->jack, rt286->jack->status,
323 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
324 } else {
325 /* disable IRQ */
326 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
327 snd_soc_dapm_disable_pin(dapm, "LDO1");
328 }
329 snd_soc_dapm_sync(dapm);
330
331 return 0;
332 }
333 EXPORT_SYMBOL_GPL(rt286_mic_detect);
334
335 static int is_mclk_mode(struct snd_soc_dapm_widget *source,
336 struct snd_soc_dapm_widget *sink)
337 {
338 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
339 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
340
341 if (rt286->clk_id == RT286_SCLK_S_MCLK)
342 return 1;
343 else
344 return 0;
345 }
346
347 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
348 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
349
350 static const struct snd_kcontrol_new rt286_snd_controls[] = {
351 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
352 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
353 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
354 RT286_ADCR_GAIN, 7, 1, 1),
355 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
356 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
357 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
358 0, 0x3, 0, mic_vol_tlv),
359 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
360 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
361 };
362
363 /* Digital Mixer */
364 static const struct snd_kcontrol_new rt286_front_mix[] = {
365 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
366 RT286_MUTE_SFT, 1, 1),
367 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
368 RT286_MUTE_SFT, 1, 1),
369 };
370
371 /* Analog Input Mixer */
372 static const struct snd_kcontrol_new rt286_rec_mix[] = {
373 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
374 RT286_MUTE_SFT, 1, 1),
375 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
376 RT286_MUTE_SFT, 1, 1),
377 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
378 RT286_MUTE_SFT, 1, 1),
379 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
380 RT286_MUTE_SFT, 1, 1),
381 };
382
383 static const struct snd_kcontrol_new spo_enable_control =
384 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
385 RT286_SET_PIN_SFT, 1, 0);
386
387 static const struct snd_kcontrol_new hpol_enable_control =
388 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
389 RT286_MUTE_SFT, 1, 1);
390
391 static const struct snd_kcontrol_new hpor_enable_control =
392 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
393 RT286_MUTE_SFT, 1, 1);
394
395 /* ADC0 source */
396 static const char * const rt286_adc_src[] = {
397 "Mic", "RECMIX", "Dmic"
398 };
399
400 static const int rt286_adc_values[] = {
401 0, 4, 5,
402 };
403
404 static SOC_VALUE_ENUM_SINGLE_DECL(
405 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
406 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
407
408 static const struct snd_kcontrol_new rt286_adc0_mux =
409 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
410
411 static SOC_VALUE_ENUM_SINGLE_DECL(
412 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
413 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
414
415 static const struct snd_kcontrol_new rt286_adc1_mux =
416 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
417
418 static const char * const rt286_dac_src[] = {
419 "Front", "Surround"
420 };
421 /* HP-OUT source */
422 static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
423 0, rt286_dac_src);
424
425 static const struct snd_kcontrol_new rt286_hpo_mux =
426 SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
427
428 /* SPK-OUT source */
429 static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
430 0, rt286_dac_src);
431
432 static const struct snd_kcontrol_new rt286_spo_mux =
433 SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
434
435 static int rt286_spk_event(struct snd_soc_dapm_widget *w,
436 struct snd_kcontrol *kcontrol, int event)
437 {
438 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
439
440 switch (event) {
441 case SND_SOC_DAPM_POST_PMU:
442 snd_soc_component_write(component,
443 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
444 break;
445 case SND_SOC_DAPM_PRE_PMD:
446 snd_soc_component_write(component,
447 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
448 break;
449
450 default:
451 return 0;
452 }
453
454 return 0;
455 }
456
457 static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
458 struct snd_kcontrol *kcontrol, int event)
459 {
460 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
461
462 switch (event) {
463 case SND_SOC_DAPM_POST_PMU:
464 snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0x20);
465 break;
466 case SND_SOC_DAPM_PRE_PMD:
467 snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0);
468 break;
469 default:
470 return 0;
471 }
472
473 return 0;
474 }
475
476 static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
477 struct snd_kcontrol *kcontrol, int event)
478 {
479 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
480
481 switch (event) {
482 case SND_SOC_DAPM_POST_PMU:
483 snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x08);
484 break;
485 case SND_SOC_DAPM_PRE_PMD:
486 snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x30);
487 break;
488 default:
489 return 0;
490 }
491
492 return 0;
493 }
494
495 static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
496 struct snd_kcontrol *kcontrol, int event)
497 {
498 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
499
500 switch (event) {
501 case SND_SOC_DAPM_PRE_PMU:
502 snd_soc_component_update_bits(component,
503 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
504 snd_soc_component_update_bits(component,
505 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
506 break;
507 case SND_SOC_DAPM_POST_PMD:
508 snd_soc_component_update_bits(component,
509 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
510 snd_soc_component_update_bits(component,
511 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
512 break;
513 default:
514 return 0;
515 }
516
517 return 0;
518 }
519
520 static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
521 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
522 12, 1, NULL, 0),
523 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
524 0, 1, NULL, 0),
525 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
526 2, 0, NULL, 0),
527 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
528 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
529 SND_SOC_DAPM_POST_PMU),
530 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
531 5, 0, NULL, 0),
532 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
533 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
534 SND_SOC_DAPM_POST_PMD),
535
536 /* Input Lines */
537 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
538 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
539 SND_SOC_DAPM_INPUT("MIC1"),
540 SND_SOC_DAPM_INPUT("LINE1"),
541 SND_SOC_DAPM_INPUT("Beep"),
542
543 /* DMIC */
544 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
545 NULL, 0, rt286_set_dmic1_event,
546 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
547 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
548 NULL, 0),
549 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
550 0, 0, NULL, 0),
551
552 /* REC Mixer */
553 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
554 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
555
556 /* ADCs */
557 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
558 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
559
560 /* ADC Mux */
561 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
562 &rt286_adc0_mux),
563 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
564 &rt286_adc1_mux),
565
566 /* Audio Interface */
567 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
568 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
569 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
570 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
571
572 /* Output Side */
573 /* DACs */
574 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
575 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
576
577 /* Output Mux */
578 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
579 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
580
581 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
582 RT286_SET_PIN_SFT, 0, NULL, 0),
583
584 /* Output Mixer */
585 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
586 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
587 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
588 NULL, 0),
589
590 /* Output Pga */
591 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
592 &spo_enable_control, rt286_spk_event,
593 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
594 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
595 &hpol_enable_control),
596 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
597 &hpor_enable_control),
598
599 /* Output Lines */
600 SND_SOC_DAPM_OUTPUT("SPOL"),
601 SND_SOC_DAPM_OUTPUT("SPOR"),
602 SND_SOC_DAPM_OUTPUT("HPO Pin"),
603 SND_SOC_DAPM_OUTPUT("SPDIF"),
604 };
605
606 static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
607 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
608 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
609 {"Front", NULL, "MCLK MODE", is_mclk_mode},
610 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
611
612 {"HP Power", NULL, "LDO1"},
613 {"HP Power", NULL, "LDO2"},
614
615 {"MIC1", NULL, "LDO1"},
616 {"MIC1", NULL, "LDO2"},
617 {"MIC1", NULL, "HV"},
618 {"MIC1", NULL, "VREF"},
619 {"MIC1", NULL, "MIC1 Input Buffer"},
620
621 {"SPO", NULL, "LDO1"},
622 {"SPO", NULL, "LDO2"},
623 {"SPO", NULL, "HV"},
624 {"SPO", NULL, "VREF"},
625
626 {"DMIC1", NULL, "DMIC1 Pin"},
627 {"DMIC2", NULL, "DMIC2 Pin"},
628 {"DMIC1", NULL, "DMIC Receiver"},
629 {"DMIC2", NULL, "DMIC Receiver"},
630
631 {"RECMIX", "Beep Switch", "Beep"},
632 {"RECMIX", "Line1 Switch", "LINE1"},
633 {"RECMIX", "Mic1 Switch", "MIC1"},
634
635 {"ADC 0 Mux", "Dmic", "DMIC1"},
636 {"ADC 0 Mux", "RECMIX", "RECMIX"},
637 {"ADC 0 Mux", "Mic", "MIC1"},
638 {"ADC 1 Mux", "Dmic", "DMIC2"},
639 {"ADC 1 Mux", "RECMIX", "RECMIX"},
640 {"ADC 1 Mux", "Mic", "MIC1"},
641
642 {"ADC 0", NULL, "ADC 0 Mux"},
643 {"ADC 1", NULL, "ADC 1 Mux"},
644
645 {"AIF1TX", NULL, "ADC 0"},
646 {"AIF2TX", NULL, "ADC 1"},
647
648 {"DAC 0", NULL, "AIF1RX"},
649 {"DAC 1", NULL, "AIF2RX"},
650
651 {"Front", "DAC Switch", "DAC 0"},
652 {"Front", "RECMIX Switch", "RECMIX"},
653
654 {"Surround", NULL, "DAC 1"},
655
656 {"SPK Mux", "Front", "Front"},
657 {"SPK Mux", "Surround", "Surround"},
658
659 {"HPO Mux", "Front", "Front"},
660 {"HPO Mux", "Surround", "Surround"},
661
662 {"SPO", "Switch", "SPK Mux"},
663 {"HPO L", "Switch", "HPO Mux"},
664 {"HPO R", "Switch", "HPO Mux"},
665 {"HPO L", NULL, "HP Power"},
666 {"HPO R", NULL, "HP Power"},
667
668 {"SPOL", NULL, "SPO"},
669 {"SPOR", NULL, "SPO"},
670 {"HPO Pin", NULL, "HPO L"},
671 {"HPO Pin", NULL, "HPO R"},
672 };
673
674 static int rt286_hw_params(struct snd_pcm_substream *substream,
675 struct snd_pcm_hw_params *params,
676 struct snd_soc_dai *dai)
677 {
678 struct snd_soc_component *component = dai->component;
679 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
680 unsigned int val = 0;
681 int d_len_code;
682
683 switch (params_rate(params)) {
684 /* bit 14 0:48K 1:44.1K */
685 case 44100:
686 val |= 0x4000;
687 break;
688 case 48000:
689 break;
690 default:
691 dev_err(component->dev, "Unsupported sample rate %d\n",
692 params_rate(params));
693 return -EINVAL;
694 }
695 switch (rt286->sys_clk) {
696 case 12288000:
697 case 24576000:
698 if (params_rate(params) != 48000) {
699 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
700 params_rate(params), rt286->sys_clk);
701 return -EINVAL;
702 }
703 break;
704 case 11289600:
705 case 22579200:
706 if (params_rate(params) != 44100) {
707 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
708 params_rate(params), rt286->sys_clk);
709 return -EINVAL;
710 }
711 break;
712 }
713
714 if (params_channels(params) <= 16) {
715 /* bit 3:0 Number of Channel */
716 val |= (params_channels(params) - 1);
717 } else {
718 dev_err(component->dev, "Unsupported channels %d\n",
719 params_channels(params));
720 return -EINVAL;
721 }
722
723 d_len_code = 0;
724 switch (params_width(params)) {
725 /* bit 6:4 Bits per Sample */
726 case 16:
727 d_len_code = 0;
728 val |= (0x1 << 4);
729 break;
730 case 32:
731 d_len_code = 2;
732 val |= (0x4 << 4);
733 break;
734 case 20:
735 d_len_code = 1;
736 val |= (0x2 << 4);
737 break;
738 case 24:
739 d_len_code = 2;
740 val |= (0x3 << 4);
741 break;
742 case 8:
743 d_len_code = 3;
744 break;
745 default:
746 return -EINVAL;
747 }
748
749 snd_soc_component_update_bits(component,
750 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
751 dev_dbg(component->dev, "format val = 0x%x\n", val);
752
753 snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val);
754 snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val);
755
756 return 0;
757 }
758
759 static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
760 {
761 struct snd_soc_component *component = dai->component;
762
763 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
764 case SND_SOC_DAIFMT_CBM_CFM:
765 snd_soc_component_update_bits(component,
766 RT286_I2S_CTRL1, 0x800, 0x800);
767 break;
768 case SND_SOC_DAIFMT_CBS_CFS:
769 snd_soc_component_update_bits(component,
770 RT286_I2S_CTRL1, 0x800, 0x0);
771 break;
772 default:
773 return -EINVAL;
774 }
775
776 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
777 case SND_SOC_DAIFMT_I2S:
778 snd_soc_component_update_bits(component,
779 RT286_I2S_CTRL1, 0x300, 0x0);
780 break;
781 case SND_SOC_DAIFMT_LEFT_J:
782 snd_soc_component_update_bits(component,
783 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
784 break;
785 case SND_SOC_DAIFMT_DSP_A:
786 snd_soc_component_update_bits(component,
787 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
788 break;
789 case SND_SOC_DAIFMT_DSP_B:
790 snd_soc_component_update_bits(component,
791 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
792 break;
793 default:
794 return -EINVAL;
795 }
796 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
797 snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x8000, 0);
798 snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x8000, 0);
799
800 return 0;
801 }
802
803 static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
804 int clk_id, unsigned int freq, int dir)
805 {
806 struct snd_soc_component *component = dai->component;
807 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
808
809 dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
810
811 if (RT286_SCLK_S_MCLK == clk_id) {
812 snd_soc_component_update_bits(component,
813 RT286_I2S_CTRL2, 0x0100, 0x0);
814 snd_soc_component_update_bits(component,
815 RT286_PLL_CTRL1, 0x20, 0x20);
816 } else {
817 snd_soc_component_update_bits(component,
818 RT286_I2S_CTRL2, 0x0100, 0x0100);
819 snd_soc_component_update_bits(component,
820 RT286_PLL_CTRL, 0x4, 0x4);
821 snd_soc_component_update_bits(component,
822 RT286_PLL_CTRL1, 0x20, 0x0);
823 }
824
825 switch (freq) {
826 case 19200000:
827 if (RT286_SCLK_S_MCLK == clk_id) {
828 dev_err(component->dev, "Should not use MCLK\n");
829 return -EINVAL;
830 }
831 snd_soc_component_update_bits(component,
832 RT286_I2S_CTRL2, 0x40, 0x40);
833 break;
834 case 24000000:
835 if (RT286_SCLK_S_MCLK == clk_id) {
836 dev_err(component->dev, "Should not use MCLK\n");
837 return -EINVAL;
838 }
839 snd_soc_component_update_bits(component,
840 RT286_I2S_CTRL2, 0x40, 0x0);
841 break;
842 case 12288000:
843 case 11289600:
844 snd_soc_component_update_bits(component,
845 RT286_I2S_CTRL2, 0x8, 0x0);
846 snd_soc_component_update_bits(component,
847 RT286_CLK_DIV, 0xfc1e, 0x0004);
848 break;
849 case 24576000:
850 case 22579200:
851 snd_soc_component_update_bits(component,
852 RT286_I2S_CTRL2, 0x8, 0x8);
853 snd_soc_component_update_bits(component,
854 RT286_CLK_DIV, 0xfc1e, 0x5406);
855 break;
856 default:
857 dev_err(component->dev, "Unsupported system clock\n");
858 return -EINVAL;
859 }
860
861 rt286->sys_clk = freq;
862 rt286->clk_id = clk_id;
863
864 return 0;
865 }
866
867 static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
868 {
869 struct snd_soc_component *component = dai->component;
870
871 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
872 if (50 == ratio)
873 snd_soc_component_update_bits(component,
874 RT286_I2S_CTRL1, 0x1000, 0x1000);
875 else
876 snd_soc_component_update_bits(component,
877 RT286_I2S_CTRL1, 0x1000, 0x0);
878
879
880 return 0;
881 }
882
883 static int rt286_set_bias_level(struct snd_soc_component *component,
884 enum snd_soc_bias_level level)
885 {
886 switch (level) {
887 case SND_SOC_BIAS_PREPARE:
888 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
889 snd_soc_component_write(component,
890 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
891 snd_soc_component_update_bits(component,
892 RT286_DC_GAIN, 0x200, 0x200);
893 }
894 break;
895
896 case SND_SOC_BIAS_ON:
897 mdelay(10);
898 snd_soc_component_update_bits(component,
899 RT286_DC_GAIN, 0x200, 0x0);
900
901 break;
902
903 case SND_SOC_BIAS_STANDBY:
904 snd_soc_component_write(component,
905 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
906 break;
907
908 default:
909 break;
910 }
911
912 return 0;
913 }
914
915 static irqreturn_t rt286_irq(int irq, void *data)
916 {
917 struct rt286_priv *rt286 = data;
918 bool hp = false;
919 bool mic = false;
920 int status = 0;
921
922 rt286_jack_detect(rt286, &hp, &mic);
923
924 /* Clear IRQ */
925 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
926
927 if (hp == true)
928 status |= SND_JACK_HEADPHONE;
929
930 if (mic == true)
931 status |= SND_JACK_MICROPHONE;
932
933 snd_soc_jack_report(rt286->jack, status,
934 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
935
936 pm_wakeup_event(&rt286->i2c->dev, 300);
937
938 return IRQ_HANDLED;
939 }
940
941 static int rt286_probe(struct snd_soc_component *component)
942 {
943 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
944
945 rt286->component = component;
946
947 if (rt286->i2c->irq) {
948 regmap_update_bits(rt286->regmap,
949 RT286_IRQ_CTRL, 0x2, 0x2);
950
951 INIT_DELAYED_WORK(&rt286->jack_detect_work,
952 rt286_jack_detect_work);
953 schedule_delayed_work(&rt286->jack_detect_work,
954 msecs_to_jiffies(1250));
955 }
956
957 return 0;
958 }
959
960 static void rt286_remove(struct snd_soc_component *component)
961 {
962 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
963
964 cancel_delayed_work_sync(&rt286->jack_detect_work);
965 }
966
967 #ifdef CONFIG_PM
968 static int rt286_suspend(struct snd_soc_component *component)
969 {
970 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
971
972 regcache_cache_only(rt286->regmap, true);
973 regcache_mark_dirty(rt286->regmap);
974
975 return 0;
976 }
977
978 static int rt286_resume(struct snd_soc_component *component)
979 {
980 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
981
982 regcache_cache_only(rt286->regmap, false);
983 rt286_index_sync(component);
984 regcache_sync(rt286->regmap);
985
986 return 0;
987 }
988 #else
989 #define rt286_suspend NULL
990 #define rt286_resume NULL
991 #endif
992
993 #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
994 #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
995 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
996
997 static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
998 .hw_params = rt286_hw_params,
999 .set_fmt = rt286_set_dai_fmt,
1000 .set_sysclk = rt286_set_dai_sysclk,
1001 .set_bclk_ratio = rt286_set_bclk_ratio,
1002 };
1003
1004 static struct snd_soc_dai_driver rt286_dai[] = {
1005 {
1006 .name = "rt286-aif1",
1007 .id = RT286_AIF1,
1008 .playback = {
1009 .stream_name = "AIF1 Playback",
1010 .channels_min = 1,
1011 .channels_max = 2,
1012 .rates = RT286_STEREO_RATES,
1013 .formats = RT286_FORMATS,
1014 },
1015 .capture = {
1016 .stream_name = "AIF1 Capture",
1017 .channels_min = 1,
1018 .channels_max = 2,
1019 .rates = RT286_STEREO_RATES,
1020 .formats = RT286_FORMATS,
1021 },
1022 .ops = &rt286_aif_dai_ops,
1023 .symmetric_rates = 1,
1024 },
1025 {
1026 .name = "rt286-aif2",
1027 .id = RT286_AIF2,
1028 .playback = {
1029 .stream_name = "AIF2 Playback",
1030 .channels_min = 1,
1031 .channels_max = 2,
1032 .rates = RT286_STEREO_RATES,
1033 .formats = RT286_FORMATS,
1034 },
1035 .capture = {
1036 .stream_name = "AIF2 Capture",
1037 .channels_min = 1,
1038 .channels_max = 2,
1039 .rates = RT286_STEREO_RATES,
1040 .formats = RT286_FORMATS,
1041 },
1042 .ops = &rt286_aif_dai_ops,
1043 .symmetric_rates = 1,
1044 },
1045
1046 };
1047
1048 static const struct snd_soc_component_driver soc_component_dev_rt286 = {
1049 .probe = rt286_probe,
1050 .remove = rt286_remove,
1051 .suspend = rt286_suspend,
1052 .resume = rt286_resume,
1053 .set_bias_level = rt286_set_bias_level,
1054 .controls = rt286_snd_controls,
1055 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1056 .dapm_widgets = rt286_dapm_widgets,
1057 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1058 .dapm_routes = rt286_dapm_routes,
1059 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1060 .use_pmdown_time = 1,
1061 .endianness = 1,
1062 .non_legacy_dai_naming = 1,
1063 };
1064
1065 static const struct regmap_config rt286_regmap = {
1066 .reg_bits = 32,
1067 .val_bits = 32,
1068 .max_register = 0x02370100,
1069 .volatile_reg = rt286_volatile_register,
1070 .readable_reg = rt286_readable_register,
1071 .reg_write = rl6347a_hw_write,
1072 .reg_read = rl6347a_hw_read,
1073 .cache_type = REGCACHE_RBTREE,
1074 .reg_defaults = rt286_reg,
1075 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1076 };
1077
1078 static const struct i2c_device_id rt286_i2c_id[] = {
1079 {"rt286", 0},
1080 {"rt288", 0},
1081 {}
1082 };
1083 MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1084
1085 static const struct acpi_device_id rt286_acpi_match[] = {
1086 { "INT343A", 0 },
1087 {},
1088 };
1089 MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1090
1091 static const struct dmi_system_id force_combo_jack_table[] = {
1092 {
1093 .ident = "Intel Wilson Beach",
1094 .matches = {
1095 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1096 }
1097 },
1098 {
1099 .ident = "Intel Skylake RVP",
1100 .matches = {
1101 DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
1102 }
1103 },
1104 {
1105 .ident = "Intel Kabylake RVP",
1106 .matches = {
1107 DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
1108 }
1109 },
1110 {
1111 .ident = "Thinkpad Helix 2nd",
1112 .matches = {
1113 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1114 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
1115 }
1116 },
1117
1118 { }
1119 };
1120
1121 static const struct dmi_system_id dmi_dell_dino[] = {
1122 {
1123 .ident = "Dell Dino",
1124 .matches = {
1125 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1126 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343")
1127 }
1128 },
1129 { }
1130 };
1131
1132 static int rt286_i2c_probe(struct i2c_client *i2c,
1133 const struct i2c_device_id *id)
1134 {
1135 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1136 struct rt286_priv *rt286;
1137 int i, ret, val;
1138
1139 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1140 GFP_KERNEL);
1141 if (NULL == rt286)
1142 return -ENOMEM;
1143
1144 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1145 if (IS_ERR(rt286->regmap)) {
1146 ret = PTR_ERR(rt286->regmap);
1147 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1148 ret);
1149 return ret;
1150 }
1151
1152 ret = regmap_read(rt286->regmap,
1153 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1154 if (ret != 0) {
1155 dev_err(&i2c->dev, "I2C error %d\n", ret);
1156 return ret;
1157 }
1158 if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) {
1159 dev_err(&i2c->dev,
1160 "Device with ID register %#x is not rt286\n", val);
1161 return -ENODEV;
1162 }
1163
1164 rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
1165 sizeof(rt286_index_def), GFP_KERNEL);
1166 if (!rt286->index_cache)
1167 return -ENOMEM;
1168
1169 rt286->index_cache_size = INDEX_CACHE_SIZE;
1170 rt286->i2c = i2c;
1171 i2c_set_clientdata(i2c, rt286);
1172
1173 /* restore codec default */
1174 for (i = 0; i < INDEX_CACHE_SIZE; i++)
1175 regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1176 rt286->index_cache[i].def);
1177 for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1178 regmap_write(rt286->regmap, rt286_reg[i].reg,
1179 rt286_reg[i].def);
1180
1181 if (pdata)
1182 rt286->pdata = *pdata;
1183
1184 if (dmi_check_system(force_combo_jack_table) ||
1185 dmi_check_system(dmi_dell_dino))
1186 rt286->pdata.cbj_en = true;
1187
1188 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1189
1190 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1191 regmap_write(rt286->regmap,
1192 RT286_SET_POWER(rt286_support_power_controls[i]),
1193 AC_PWRST_D1);
1194
1195 if (!rt286->pdata.cbj_en) {
1196 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1197 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1198 regmap_update_bits(rt286->regmap,
1199 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1200 } else {
1201 regmap_update_bits(rt286->regmap,
1202 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1203 }
1204
1205 mdelay(10);
1206
1207 if (!rt286->pdata.gpio2_en)
1208 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1209 else
1210 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1211
1212 mdelay(10);
1213
1214 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1215 /* Power down LDO, VREF */
1216 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1217 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1218
1219 /* Set depop parameter */
1220 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1221 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1222 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1223
1224 if (dmi_check_system(dmi_dell_dino)) {
1225 regmap_update_bits(rt286->regmap,
1226 RT286_SET_GPIO_MASK, 0x40, 0x40);
1227 regmap_update_bits(rt286->regmap,
1228 RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1229 regmap_update_bits(rt286->regmap,
1230 RT286_SET_GPIO_DATA, 0x40, 0x40);
1231 regmap_update_bits(rt286->regmap,
1232 RT286_GPIO_CTRL, 0xc, 0x8);
1233 }
1234
1235 if (rt286->i2c->irq) {
1236 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1237 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1238 if (ret != 0) {
1239 dev_err(&i2c->dev,
1240 "Failed to reguest IRQ: %d\n", ret);
1241 return ret;
1242 }
1243 }
1244
1245 ret = devm_snd_soc_register_component(&i2c->dev,
1246 &soc_component_dev_rt286,
1247 rt286_dai, ARRAY_SIZE(rt286_dai));
1248
1249 return ret;
1250 }
1251
1252 static int rt286_i2c_remove(struct i2c_client *i2c)
1253 {
1254 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1255
1256 if (i2c->irq)
1257 free_irq(i2c->irq, rt286);
1258
1259 return 0;
1260 }
1261
1262
1263 static struct i2c_driver rt286_i2c_driver = {
1264 .driver = {
1265 .name = "rt286",
1266 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1267 },
1268 .probe = rt286_i2c_probe,
1269 .remove = rt286_i2c_remove,
1270 .id_table = rt286_i2c_id,
1271 };
1272
1273 module_i2c_driver(rt286_i2c_driver);
1274
1275 MODULE_DESCRIPTION("ASoC RT286 driver");
1276 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1277 MODULE_LICENSE("GPL");
Linux with added FPC-III support