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Merge tag 'riscv-for-linus-4.15-rc4-riscv_fixes' of git://git.kernel.org/pub/scm...
[linux/fpc-iii.git] / drivers / mmc / host / mtk-sd.c
blob6457a7d8880f058a75598cdf1431933fdf740d30
1 /*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
32
33 #include <linux/mmc/card.h>
34 #include <linux/mmc/core.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/sd.h>
38 #include <linux/mmc/sdio.h>
39 #include <linux/mmc/slot-gpio.h>
40
41 #define MAX_BD_NUM 1024
42
43 /*--------------------------------------------------------------------------*/
44 /* Common Definition */
45 /*--------------------------------------------------------------------------*/
46 #define MSDC_BUS_1BITS 0x0
47 #define MSDC_BUS_4BITS 0x1
48 #define MSDC_BUS_8BITS 0x2
49
50 #define MSDC_BURST_64B 0x6
51
52 /*--------------------------------------------------------------------------*/
53 /* Register Offset */
54 /*--------------------------------------------------------------------------*/
55 #define MSDC_CFG 0x0
56 #define MSDC_IOCON 0x04
57 #define MSDC_PS 0x08
58 #define MSDC_INT 0x0c
59 #define MSDC_INTEN 0x10
60 #define MSDC_FIFOCS 0x14
61 #define SDC_CFG 0x30
62 #define SDC_CMD 0x34
63 #define SDC_ARG 0x38
64 #define SDC_STS 0x3c
65 #define SDC_RESP0 0x40
66 #define SDC_RESP1 0x44
67 #define SDC_RESP2 0x48
68 #define SDC_RESP3 0x4c
69 #define SDC_BLK_NUM 0x50
70 #define SDC_ADV_CFG0 0x64
71 #define EMMC_IOCON 0x7c
72 #define SDC_ACMD_RESP 0x80
73 #define MSDC_DMA_SA 0x90
74 #define MSDC_DMA_CTRL 0x98
75 #define MSDC_DMA_CFG 0x9c
76 #define MSDC_PATCH_BIT 0xb0
77 #define MSDC_PATCH_BIT1 0xb4
78 #define MSDC_PATCH_BIT2 0xb8
79 #define MSDC_PAD_TUNE 0xec
80 #define MSDC_PAD_TUNE0 0xf0
81 #define PAD_DS_TUNE 0x188
82 #define PAD_CMD_TUNE 0x18c
83 #define EMMC50_CFG0 0x208
84 #define EMMC50_CFG3 0x220
85 #define SDC_FIFO_CFG 0x228
86
87 /*--------------------------------------------------------------------------*/
88 /* Register Mask */
89 /*--------------------------------------------------------------------------*/
90
91 /* MSDC_CFG mask */
92 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
93 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
94 #define MSDC_CFG_RST (0x1 << 2) /* RW */
95 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
96 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
97 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
98 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
99 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
100 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
101 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
102 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
103 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
104 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
105 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
106
107 /* MSDC_IOCON mask */
108 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
109 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
110 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
111 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
112 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
113 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
114 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
115 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
116 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
117 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
118 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
119 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
120 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
121 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
122 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
123 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
124
125 /* MSDC_PS mask */
126 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
127 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
128 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
129 #define MSDC_PS_DAT (0xff << 16) /* R */
130 #define MSDC_PS_CMD (0x1 << 24) /* R */
131 #define MSDC_PS_WP (0x1 << 31) /* R */
132
133 /* MSDC_INT mask */
134 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
135 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
136 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
137 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
138 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
139 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
140 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
141 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
142 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
143 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
144 #define MSDC_INT_CSTA (0x1 << 11) /* R */
145 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
146 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
147 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
148 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
149 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
150 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
151 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
152 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
153
154 /* MSDC_INTEN mask */
155 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
156 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
157 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
158 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
159 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
160 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
161 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
162 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
163 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
164 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
165 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
166 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
167 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
168 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
169 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
170 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
171 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
172 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
173 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
174
175 /* MSDC_FIFOCS mask */
176 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
177 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
178 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
179
180 /* SDC_CFG mask */
181 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
182 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
183 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
184 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
185 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
186 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
187 #define SDC_CFG_DTOC (0xff << 24) /* RW */
188
189 /* SDC_STS mask */
190 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
191 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
192 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
193
194 /* SDC_ADV_CFG0 mask */
195 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
196
197 /* MSDC_DMA_CTRL mask */
198 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
199 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
200 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
201 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
202 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
203 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
204
205 /* MSDC_DMA_CFG mask */
206 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
207 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
208 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
209 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
210 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
211
212 /* MSDC_PATCH_BIT mask */
213 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
214 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
215 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
216 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
217 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
218 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
219 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
220 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
221 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
222 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
223 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
224 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
225
226 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
227
228 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
229 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
230 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
231 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
232 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
233
234 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
235 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
236 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
237 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
238 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
239 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
240 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
241 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
242
243 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
244 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
245 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
246
247 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
248
249 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
250 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
251 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
252
253 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
254
255 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
256 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
257
258 #define REQ_CMD_EIO (0x1 << 0)
259 #define REQ_CMD_TMO (0x1 << 1)
260 #define REQ_DAT_ERR (0x1 << 2)
261 #define REQ_STOP_EIO (0x1 << 3)
262 #define REQ_STOP_TMO (0x1 << 4)
263 #define REQ_CMD_BUSY (0x1 << 5)
264
265 #define MSDC_PREPARE_FLAG (0x1 << 0)
266 #define MSDC_ASYNC_FLAG (0x1 << 1)
267 #define MSDC_MMAP_FLAG (0x1 << 2)
268
269 #define MTK_MMC_AUTOSUSPEND_DELAY 50
270 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
271 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
272
273 #define PAD_DELAY_MAX 32 /* PAD delay cells */
274 /*--------------------------------------------------------------------------*/
275 /* Descriptor Structure */
276 /*--------------------------------------------------------------------------*/
277 struct mt_gpdma_desc {
278 u32 gpd_info;
279 #define GPDMA_DESC_HWO (0x1 << 0)
280 #define GPDMA_DESC_BDP (0x1 << 1)
281 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
282 #define GPDMA_DESC_INT (0x1 << 16)
283 u32 next;
284 u32 ptr;
285 u32 gpd_data_len;
286 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
287 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
288 u32 arg;
289 u32 blknum;
290 u32 cmd;
291 };
292
293 struct mt_bdma_desc {
294 u32 bd_info;
295 #define BDMA_DESC_EOL (0x1 << 0)
296 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
297 #define BDMA_DESC_BLKPAD (0x1 << 17)
298 #define BDMA_DESC_DWPAD (0x1 << 18)
299 u32 next;
300 u32 ptr;
301 u32 bd_data_len;
302 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
303 };
304
305 struct msdc_dma {
306 struct scatterlist *sg; /* I/O scatter list */
307 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
308 struct mt_bdma_desc *bd; /* pointer to bd array */
309 dma_addr_t gpd_addr; /* the physical address of gpd array */
310 dma_addr_t bd_addr; /* the physical address of bd array */
311 };
312
313 struct msdc_save_para {
314 u32 msdc_cfg;
315 u32 iocon;
316 u32 sdc_cfg;
317 u32 pad_tune;
318 u32 patch_bit0;
319 u32 patch_bit1;
320 u32 patch_bit2;
321 u32 pad_ds_tune;
322 u32 pad_cmd_tune;
323 u32 emmc50_cfg0;
324 u32 emmc50_cfg3;
325 u32 sdc_fifo_cfg;
326 };
327
328 struct mtk_mmc_compatible {
329 u8 clk_div_bits;
330 bool hs400_tune; /* only used for MT8173 */
331 u32 pad_tune_reg;
332 bool async_fifo;
333 bool data_tune;
334 bool busy_check;
335 bool stop_clk_fix;
336 bool enhance_rx;
337 };
338
339 struct msdc_tune_para {
340 u32 iocon;
341 u32 pad_tune;
342 u32 pad_cmd_tune;
343 };
344
345 struct msdc_delay_phase {
346 u8 maxlen;
347 u8 start;
348 u8 final_phase;
349 };
350
351 struct msdc_host {
352 struct device *dev;
353 const struct mtk_mmc_compatible *dev_comp;
354 struct mmc_host *mmc; /* mmc structure */
355 int cmd_rsp;
356
357 spinlock_t lock;
358 struct mmc_request *mrq;
359 struct mmc_command *cmd;
360 struct mmc_data *data;
361 int error;
362
363 void __iomem *base; /* host base address */
364
365 struct msdc_dma dma; /* dma channel */
366 u64 dma_mask;
367
368 u32 timeout_ns; /* data timeout ns */
369 u32 timeout_clks; /* data timeout clks */
370
371 struct pinctrl *pinctrl;
372 struct pinctrl_state *pins_default;
373 struct pinctrl_state *pins_uhs;
374 struct delayed_work req_timeout;
375 int irq; /* host interrupt */
376
377 struct clk *src_clk; /* msdc source clock */
378 struct clk *h_clk; /* msdc h_clk */
379 struct clk *src_clk_cg; /* msdc source clock control gate */
380 u32 mclk; /* mmc subsystem clock frequency */
381 u32 src_clk_freq; /* source clock frequency */
382 u32 sclk; /* SD/MS bus clock frequency */
383 unsigned char timing;
384 bool vqmmc_enabled;
385 u32 latch_ck;
386 u32 hs400_ds_delay;
387 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
388 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
389 bool hs400_cmd_resp_sel_rising;
390 /* cmd response sample selection for HS400 */
391 bool hs400_mode; /* current eMMC will run at hs400 mode */
392 struct msdc_save_para save_para; /* used when gate HCLK */
393 struct msdc_tune_para def_tune_para; /* default tune setting */
394 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
395 };
396
397 static const struct mtk_mmc_compatible mt8135_compat = {
398 .clk_div_bits = 8,
399 .hs400_tune = false,
400 .pad_tune_reg = MSDC_PAD_TUNE,
401 .async_fifo = false,
402 .data_tune = false,
403 .busy_check = false,
404 .stop_clk_fix = false,
405 .enhance_rx = false,
406 };
407
408 static const struct mtk_mmc_compatible mt8173_compat = {
409 .clk_div_bits = 8,
410 .hs400_tune = true,
411 .pad_tune_reg = MSDC_PAD_TUNE,
412 .async_fifo = false,
413 .data_tune = false,
414 .busy_check = false,
415 .stop_clk_fix = false,
416 .enhance_rx = false,
417 };
418
419 static const struct mtk_mmc_compatible mt2701_compat = {
420 .clk_div_bits = 12,
421 .hs400_tune = false,
422 .pad_tune_reg = MSDC_PAD_TUNE0,
423 .async_fifo = true,
424 .data_tune = true,
425 .busy_check = false,
426 .stop_clk_fix = false,
427 .enhance_rx = false,
428 };
429
430 static const struct mtk_mmc_compatible mt2712_compat = {
431 .clk_div_bits = 12,
432 .hs400_tune = false,
433 .pad_tune_reg = MSDC_PAD_TUNE0,
434 .async_fifo = true,
435 .data_tune = true,
436 .busy_check = true,
437 .stop_clk_fix = true,
438 .enhance_rx = true,
439 };
440
441 static const struct of_device_id msdc_of_ids[] = {
442 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
443 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
444 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
445 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
446 {}
447 };
448 MODULE_DEVICE_TABLE(of, msdc_of_ids);
449
450 static void sdr_set_bits(void __iomem *reg, u32 bs)
451 {
452 u32 val = readl(reg);
453
454 val |= bs;
455 writel(val, reg);
456 }
457
458 static void sdr_clr_bits(void __iomem *reg, u32 bs)
459 {
460 u32 val = readl(reg);
461
462 val &= ~bs;
463 writel(val, reg);
464 }
465
466 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
467 {
468 unsigned int tv = readl(reg);
469
470 tv &= ~field;
471 tv |= ((val) << (ffs((unsigned int)field) - 1));
472 writel(tv, reg);
473 }
474
475 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
476 {
477 unsigned int tv = readl(reg);
478
479 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
480 }
481
482 static void msdc_reset_hw(struct msdc_host *host)
483 {
484 u32 val;
485
486 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
487 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
488 cpu_relax();
489
490 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
491 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
492 cpu_relax();
493
494 val = readl(host->base + MSDC_INT);
495 writel(val, host->base + MSDC_INT);
496 }
497
498 static void msdc_cmd_next(struct msdc_host *host,
499 struct mmc_request *mrq, struct mmc_command *cmd);
500
501 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
502 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
503 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
504 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
505 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
506 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
507
508 static u8 msdc_dma_calcs(u8 *buf, u32 len)
509 {
510 u32 i, sum = 0;
511
512 for (i = 0; i < len; i++)
513 sum += buf[i];
514 return 0xff - (u8) sum;
515 }
516
517 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
518 struct mmc_data *data)
519 {
520 unsigned int j, dma_len;
521 dma_addr_t dma_address;
522 u32 dma_ctrl;
523 struct scatterlist *sg;
524 struct mt_gpdma_desc *gpd;
525 struct mt_bdma_desc *bd;
526
527 sg = data->sg;
528
529 gpd = dma->gpd;
530 bd = dma->bd;
531
532 /* modify gpd */
533 gpd->gpd_info |= GPDMA_DESC_HWO;
534 gpd->gpd_info |= GPDMA_DESC_BDP;
535 /* need to clear first. use these bits to calc checksum */
536 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
537 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
538
539 /* modify bd */
540 for_each_sg(data->sg, sg, data->sg_count, j) {
541 dma_address = sg_dma_address(sg);
542 dma_len = sg_dma_len(sg);
543
544 /* init bd */
545 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
546 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
547 bd[j].ptr = (u32)dma_address;
548 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
549 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
550
551 if (j == data->sg_count - 1) /* the last bd */
552 bd[j].bd_info |= BDMA_DESC_EOL;
553 else
554 bd[j].bd_info &= ~BDMA_DESC_EOL;
555
556 /* checksume need to clear first */
557 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
558 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
559 }
560
561 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
562 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
563 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
564 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
565 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
566 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
567 }
568
569 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
570 {
571 struct mmc_data *data = mrq->data;
572
573 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
574 data->host_cookie |= MSDC_PREPARE_FLAG;
575 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
576 mmc_get_dma_dir(data));
577 }
578 }
579
580 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
581 {
582 struct mmc_data *data = mrq->data;
583
584 if (data->host_cookie & MSDC_ASYNC_FLAG)
585 return;
586
587 if (data->host_cookie & MSDC_PREPARE_FLAG) {
588 dma_unmap_sg(host->dev, data->sg, data->sg_len,
589 mmc_get_dma_dir(data));
590 data->host_cookie &= ~MSDC_PREPARE_FLAG;
591 }
592 }
593
594 /* clock control primitives */
595 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
596 {
597 u32 timeout, clk_ns;
598 u32 mode = 0;
599
600 host->timeout_ns = ns;
601 host->timeout_clks = clks;
602 if (host->sclk == 0) {
603 timeout = 0;
604 } else {
605 clk_ns = 1000000000UL / host->sclk;
606 timeout = (ns + clk_ns - 1) / clk_ns + clks;
607 /* in 1048576 sclk cycle unit */
608 timeout = (timeout + (0x1 << 20) - 1) >> 20;
609 if (host->dev_comp->clk_div_bits == 8)
610 sdr_get_field(host->base + MSDC_CFG,
611 MSDC_CFG_CKMOD, &mode);
612 else
613 sdr_get_field(host->base + MSDC_CFG,
614 MSDC_CFG_CKMOD_EXTRA, &mode);
615 /*DDR mode will double the clk cycles for data timeout */
616 timeout = mode >= 2 ? timeout * 2 : timeout;
617 timeout = timeout > 1 ? timeout - 1 : 0;
618 timeout = timeout > 255 ? 255 : timeout;
619 }
620 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
621 }
622
623 static void msdc_gate_clock(struct msdc_host *host)
624 {
625 clk_disable_unprepare(host->src_clk_cg);
626 clk_disable_unprepare(host->src_clk);
627 clk_disable_unprepare(host->h_clk);
628 }
629
630 static void msdc_ungate_clock(struct msdc_host *host)
631 {
632 clk_prepare_enable(host->h_clk);
633 clk_prepare_enable(host->src_clk);
634 clk_prepare_enable(host->src_clk_cg);
635 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
636 cpu_relax();
637 }
638
639 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
640 {
641 u32 mode;
642 u32 flags;
643 u32 div;
644 u32 sclk;
645 u32 tune_reg = host->dev_comp->pad_tune_reg;
646
647 if (!hz) {
648 dev_dbg(host->dev, "set mclk to 0\n");
649 host->mclk = 0;
650 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
651 return;
652 }
653
654 flags = readl(host->base + MSDC_INTEN);
655 sdr_clr_bits(host->base + MSDC_INTEN, flags);
656 if (host->dev_comp->clk_div_bits == 8)
657 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
658 else
659 sdr_clr_bits(host->base + MSDC_CFG,
660 MSDC_CFG_HS400_CK_MODE_EXTRA);
661 if (timing == MMC_TIMING_UHS_DDR50 ||
662 timing == MMC_TIMING_MMC_DDR52 ||
663 timing == MMC_TIMING_MMC_HS400) {
664 if (timing == MMC_TIMING_MMC_HS400)
665 mode = 0x3;
666 else
667 mode = 0x2; /* ddr mode and use divisor */
668
669 if (hz >= (host->src_clk_freq >> 2)) {
670 div = 0; /* mean div = 1/4 */
671 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
672 } else {
673 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
674 sclk = (host->src_clk_freq >> 2) / div;
675 div = (div >> 1);
676 }
677
678 if (timing == MMC_TIMING_MMC_HS400 &&
679 hz >= (host->src_clk_freq >> 1)) {
680 if (host->dev_comp->clk_div_bits == 8)
681 sdr_set_bits(host->base + MSDC_CFG,
682 MSDC_CFG_HS400_CK_MODE);
683 else
684 sdr_set_bits(host->base + MSDC_CFG,
685 MSDC_CFG_HS400_CK_MODE_EXTRA);
686 sclk = host->src_clk_freq >> 1;
687 div = 0; /* div is ignore when bit18 is set */
688 }
689 } else if (hz >= host->src_clk_freq) {
690 mode = 0x1; /* no divisor */
691 div = 0;
692 sclk = host->src_clk_freq;
693 } else {
694 mode = 0x0; /* use divisor */
695 if (hz >= (host->src_clk_freq >> 1)) {
696 div = 0; /* mean div = 1/2 */
697 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
698 } else {
699 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
700 sclk = (host->src_clk_freq >> 2) / div;
701 }
702 }
703 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
704 /*
705 * As src_clk/HCLK use the same bit to gate/ungate,
706 * So if want to only gate src_clk, need gate its parent(mux).
707 */
708 if (host->src_clk_cg)
709 clk_disable_unprepare(host->src_clk_cg);
710 else
711 clk_disable_unprepare(clk_get_parent(host->src_clk));
712 if (host->dev_comp->clk_div_bits == 8)
713 sdr_set_field(host->base + MSDC_CFG,
714 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
715 (mode << 8) | div);
716 else
717 sdr_set_field(host->base + MSDC_CFG,
718 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
719 (mode << 12) | div);
720 if (host->src_clk_cg)
721 clk_prepare_enable(host->src_clk_cg);
722 else
723 clk_prepare_enable(clk_get_parent(host->src_clk));
724
725 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
726 cpu_relax();
727 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
728 host->sclk = sclk;
729 host->mclk = hz;
730 host->timing = timing;
731 /* need because clk changed. */
732 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
733 sdr_set_bits(host->base + MSDC_INTEN, flags);
734
735 /*
736 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
737 * tune result of hs200/200Mhz is not suitable for 50Mhz
738 */
739 if (host->sclk <= 52000000) {
740 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
741 writel(host->def_tune_para.pad_tune, host->base + tune_reg);
742 } else {
743 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
744 writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
745 writel(host->saved_tune_para.pad_cmd_tune,
746 host->base + PAD_CMD_TUNE);
747 }
748
749 if (timing == MMC_TIMING_MMC_HS400 &&
750 host->dev_comp->hs400_tune)
751 sdr_set_field(host->base + PAD_CMD_TUNE,
752 MSDC_PAD_TUNE_CMDRRDLY,
753 host->hs400_cmd_int_delay);
754 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
755 }
756
757 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
758 struct mmc_request *mrq, struct mmc_command *cmd)
759 {
760 u32 resp;
761
762 switch (mmc_resp_type(cmd)) {
763 /* Actually, R1, R5, R6, R7 are the same */
764 case MMC_RSP_R1:
765 resp = 0x1;
766 break;
767 case MMC_RSP_R1B:
768 resp = 0x7;
769 break;
770 case MMC_RSP_R2:
771 resp = 0x2;
772 break;
773 case MMC_RSP_R3:
774 resp = 0x3;
775 break;
776 case MMC_RSP_NONE:
777 default:
778 resp = 0x0;
779 break;
780 }
781
782 return resp;
783 }
784
785 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
786 struct mmc_request *mrq, struct mmc_command *cmd)
787 {
788 /* rawcmd :
789 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
790 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
791 */
792 u32 opcode = cmd->opcode;
793 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
794 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
795
796 host->cmd_rsp = resp;
797
798 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
799 opcode == MMC_STOP_TRANSMISSION)
800 rawcmd |= (0x1 << 14);
801 else if (opcode == SD_SWITCH_VOLTAGE)
802 rawcmd |= (0x1 << 30);
803 else if (opcode == SD_APP_SEND_SCR ||
804 opcode == SD_APP_SEND_NUM_WR_BLKS ||
805 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
806 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
807 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
808 rawcmd |= (0x1 << 11);
809
810 if (cmd->data) {
811 struct mmc_data *data = cmd->data;
812
813 if (mmc_op_multi(opcode)) {
814 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
815 !(mrq->sbc->arg & 0xFFFF0000))
816 rawcmd |= 0x2 << 28; /* AutoCMD23 */
817 }
818
819 rawcmd |= ((data->blksz & 0xFFF) << 16);
820 if (data->flags & MMC_DATA_WRITE)
821 rawcmd |= (0x1 << 13);
822 if (data->blocks > 1)
823 rawcmd |= (0x2 << 11);
824 else
825 rawcmd |= (0x1 << 11);
826 /* Always use dma mode */
827 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
828
829 if (host->timeout_ns != data->timeout_ns ||
830 host->timeout_clks != data->timeout_clks)
831 msdc_set_timeout(host, data->timeout_ns,
832 data->timeout_clks);
833
834 writel(data->blocks, host->base + SDC_BLK_NUM);
835 }
836 return rawcmd;
837 }
838
839 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
840 struct mmc_command *cmd, struct mmc_data *data)
841 {
842 bool read;
843
844 WARN_ON(host->data);
845 host->data = data;
846 read = data->flags & MMC_DATA_READ;
847
848 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
849 msdc_dma_setup(host, &host->dma, data);
850 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
851 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
852 dev_dbg(host->dev, "DMA start\n");
853 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
854 __func__, cmd->opcode, data->blocks, read);
855 }
856
857 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
858 struct mmc_command *cmd)
859 {
860 u32 *rsp = cmd->resp;
861
862 rsp[0] = readl(host->base + SDC_ACMD_RESP);
863
864 if (events & MSDC_INT_ACMDRDY) {
865 cmd->error = 0;
866 } else {
867 msdc_reset_hw(host);
868 if (events & MSDC_INT_ACMDCRCERR) {
869 cmd->error = -EILSEQ;
870 host->error |= REQ_STOP_EIO;
871 } else if (events & MSDC_INT_ACMDTMO) {
872 cmd->error = -ETIMEDOUT;
873 host->error |= REQ_STOP_TMO;
874 }
875 dev_err(host->dev,
876 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
877 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
878 }
879 return cmd->error;
880 }
881
882 static void msdc_track_cmd_data(struct msdc_host *host,
883 struct mmc_command *cmd, struct mmc_data *data)
884 {
885 if (host->error)
886 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
887 __func__, cmd->opcode, cmd->arg, host->error);
888 }
889
890 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
891 {
892 unsigned long flags;
893 bool ret;
894
895 ret = cancel_delayed_work(&host->req_timeout);
896 if (!ret) {
897 /* delay work already running */
898 return;
899 }
900 spin_lock_irqsave(&host->lock, flags);
901 host->mrq = NULL;
902 spin_unlock_irqrestore(&host->lock, flags);
903
904 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
905 if (mrq->data)
906 msdc_unprepare_data(host, mrq);
907 mmc_request_done(host->mmc, mrq);
908 }
909
910 /* returns true if command is fully handled; returns false otherwise */
911 static bool msdc_cmd_done(struct msdc_host *host, int events,
912 struct mmc_request *mrq, struct mmc_command *cmd)
913 {
914 bool done = false;
915 bool sbc_error;
916 unsigned long flags;
917 u32 *rsp = cmd->resp;
918
919 if (mrq->sbc && cmd == mrq->cmd &&
920 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
921 | MSDC_INT_ACMDTMO)))
922 msdc_auto_cmd_done(host, events, mrq->sbc);
923
924 sbc_error = mrq->sbc && mrq->sbc->error;
925
926 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
927 | MSDC_INT_RSPCRCERR
928 | MSDC_INT_CMDTMO)))
929 return done;
930
931 spin_lock_irqsave(&host->lock, flags);
932 done = !host->cmd;
933 host->cmd = NULL;
934 spin_unlock_irqrestore(&host->lock, flags);
935
936 if (done)
937 return true;
938
939 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
940
941 if (cmd->flags & MMC_RSP_PRESENT) {
942 if (cmd->flags & MMC_RSP_136) {
943 rsp[0] = readl(host->base + SDC_RESP3);
944 rsp[1] = readl(host->base + SDC_RESP2);
945 rsp[2] = readl(host->base + SDC_RESP1);
946 rsp[3] = readl(host->base + SDC_RESP0);
947 } else {
948 rsp[0] = readl(host->base + SDC_RESP0);
949 }
950 }
951
952 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
953 if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
954 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
955 /*
956 * should not clear fifo/interrupt as the tune data
957 * may have alreay come.
958 */
959 msdc_reset_hw(host);
960 if (events & MSDC_INT_RSPCRCERR) {
961 cmd->error = -EILSEQ;
962 host->error |= REQ_CMD_EIO;
963 } else if (events & MSDC_INT_CMDTMO) {
964 cmd->error = -ETIMEDOUT;
965 host->error |= REQ_CMD_TMO;
966 }
967 }
968 if (cmd->error)
969 dev_dbg(host->dev,
970 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
971 __func__, cmd->opcode, cmd->arg, rsp[0],
972 cmd->error);
973
974 msdc_cmd_next(host, mrq, cmd);
975 return true;
976 }
977
978 /* It is the core layer's responsibility to ensure card status
979 * is correct before issue a request. but host design do below
980 * checks recommended.
981 */
982 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
983 struct mmc_request *mrq, struct mmc_command *cmd)
984 {
985 /* The max busy time we can endure is 20ms */
986 unsigned long tmo = jiffies + msecs_to_jiffies(20);
987
988 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
989 time_before(jiffies, tmo))
990 cpu_relax();
991 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
992 dev_err(host->dev, "CMD bus busy detected\n");
993 host->error |= REQ_CMD_BUSY;
994 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
995 return false;
996 }
997
998 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
999 tmo = jiffies + msecs_to_jiffies(20);
1000 /* R1B or with data, should check SDCBUSY */
1001 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1002 time_before(jiffies, tmo))
1003 cpu_relax();
1004 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1005 dev_err(host->dev, "Controller busy detected\n");
1006 host->error |= REQ_CMD_BUSY;
1007 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1008 return false;
1009 }
1010 }
1011 return true;
1012 }
1013
1014 static void msdc_start_command(struct msdc_host *host,
1015 struct mmc_request *mrq, struct mmc_command *cmd)
1016 {
1017 u32 rawcmd;
1018
1019 WARN_ON(host->cmd);
1020 host->cmd = cmd;
1021
1022 if (!msdc_cmd_is_ready(host, mrq, cmd))
1023 return;
1024
1025 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1026 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1027 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1028 msdc_reset_hw(host);
1029 }
1030
1031 cmd->error = 0;
1032 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1033 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1034
1035 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1036 writel(cmd->arg, host->base + SDC_ARG);
1037 writel(rawcmd, host->base + SDC_CMD);
1038 }
1039
1040 static void msdc_cmd_next(struct msdc_host *host,
1041 struct mmc_request *mrq, struct mmc_command *cmd)
1042 {
1043 if ((cmd->error &&
1044 !(cmd->error == -EILSEQ &&
1045 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1046 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
1047 (mrq->sbc && mrq->sbc->error))
1048 msdc_request_done(host, mrq);
1049 else if (cmd == mrq->sbc)
1050 msdc_start_command(host, mrq, mrq->cmd);
1051 else if (!cmd->data)
1052 msdc_request_done(host, mrq);
1053 else
1054 msdc_start_data(host, mrq, cmd, cmd->data);
1055 }
1056
1057 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1058 {
1059 struct msdc_host *host = mmc_priv(mmc);
1060
1061 host->error = 0;
1062 WARN_ON(host->mrq);
1063 host->mrq = mrq;
1064
1065 if (mrq->data)
1066 msdc_prepare_data(host, mrq);
1067
1068 /* if SBC is required, we have HW option and SW option.
1069 * if HW option is enabled, and SBC does not have "special" flags,
1070 * use HW option, otherwise use SW option
1071 */
1072 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1073 (mrq->sbc->arg & 0xFFFF0000)))
1074 msdc_start_command(host, mrq, mrq->sbc);
1075 else
1076 msdc_start_command(host, mrq, mrq->cmd);
1077 }
1078
1079 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1080 {
1081 struct msdc_host *host = mmc_priv(mmc);
1082 struct mmc_data *data = mrq->data;
1083
1084 if (!data)
1085 return;
1086
1087 msdc_prepare_data(host, mrq);
1088 data->host_cookie |= MSDC_ASYNC_FLAG;
1089 }
1090
1091 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1092 int err)
1093 {
1094 struct msdc_host *host = mmc_priv(mmc);
1095 struct mmc_data *data;
1096
1097 data = mrq->data;
1098 if (!data)
1099 return;
1100 if (data->host_cookie) {
1101 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1102 msdc_unprepare_data(host, mrq);
1103 }
1104 }
1105
1106 static void msdc_data_xfer_next(struct msdc_host *host,
1107 struct mmc_request *mrq, struct mmc_data *data)
1108 {
1109 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1110 !mrq->sbc)
1111 msdc_start_command(host, mrq, mrq->stop);
1112 else
1113 msdc_request_done(host, mrq);
1114 }
1115
1116 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1117 struct mmc_request *mrq, struct mmc_data *data)
1118 {
1119 struct mmc_command *stop = data->stop;
1120 unsigned long flags;
1121 bool done;
1122 unsigned int check_data = events &
1123 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1124 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1125 | MSDC_INT_DMA_PROTECT);
1126
1127 spin_lock_irqsave(&host->lock, flags);
1128 done = !host->data;
1129 if (check_data)
1130 host->data = NULL;
1131 spin_unlock_irqrestore(&host->lock, flags);
1132
1133 if (done)
1134 return true;
1135
1136 if (check_data || (stop && stop->error)) {
1137 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1138 readl(host->base + MSDC_DMA_CFG));
1139 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1140 1);
1141 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1142 cpu_relax();
1143 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1144 dev_dbg(host->dev, "DMA stop\n");
1145
1146 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1147 data->bytes_xfered = data->blocks * data->blksz;
1148 } else {
1149 dev_dbg(host->dev, "interrupt events: %x\n", events);
1150 msdc_reset_hw(host);
1151 host->error |= REQ_DAT_ERR;
1152 data->bytes_xfered = 0;
1153
1154 if (events & MSDC_INT_DATTMO)
1155 data->error = -ETIMEDOUT;
1156 else if (events & MSDC_INT_DATCRCERR)
1157 data->error = -EILSEQ;
1158
1159 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1160 __func__, mrq->cmd->opcode, data->blocks);
1161 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1162 (int)data->error, data->bytes_xfered);
1163 }
1164
1165 msdc_data_xfer_next(host, mrq, data);
1166 done = true;
1167 }
1168 return done;
1169 }
1170
1171 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1172 {
1173 u32 val = readl(host->base + SDC_CFG);
1174
1175 val &= ~SDC_CFG_BUSWIDTH;
1176
1177 switch (width) {
1178 default:
1179 case MMC_BUS_WIDTH_1:
1180 val |= (MSDC_BUS_1BITS << 16);
1181 break;
1182 case MMC_BUS_WIDTH_4:
1183 val |= (MSDC_BUS_4BITS << 16);
1184 break;
1185 case MMC_BUS_WIDTH_8:
1186 val |= (MSDC_BUS_8BITS << 16);
1187 break;
1188 }
1189
1190 writel(val, host->base + SDC_CFG);
1191 dev_dbg(host->dev, "Bus Width = %d", width);
1192 }
1193
1194 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1195 {
1196 struct msdc_host *host = mmc_priv(mmc);
1197 int ret = 0;
1198
1199 if (!IS_ERR(mmc->supply.vqmmc)) {
1200 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1201 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1202 dev_err(host->dev, "Unsupported signal voltage!\n");
1203 return -EINVAL;
1204 }
1205
1206 ret = mmc_regulator_set_vqmmc(mmc, ios);
1207 if (ret) {
1208 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1209 ret, ios->signal_voltage);
1210 } else {
1211 /* Apply different pinctrl settings for different signal voltage */
1212 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1213 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1214 else
1215 pinctrl_select_state(host->pinctrl, host->pins_default);
1216 }
1217 }
1218 return ret;
1219 }
1220
1221 static int msdc_card_busy(struct mmc_host *mmc)
1222 {
1223 struct msdc_host *host = mmc_priv(mmc);
1224 u32 status = readl(host->base + MSDC_PS);
1225
1226 /* only check if data0 is low */
1227 return !(status & BIT(16));
1228 }
1229
1230 static void msdc_request_timeout(struct work_struct *work)
1231 {
1232 struct msdc_host *host = container_of(work, struct msdc_host,
1233 req_timeout.work);
1234
1235 /* simulate HW timeout status */
1236 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1237 if (host->mrq) {
1238 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1239 host->mrq, host->mrq->cmd->opcode);
1240 if (host->cmd) {
1241 dev_err(host->dev, "%s: aborting cmd=%d\n",
1242 __func__, host->cmd->opcode);
1243 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1244 host->cmd);
1245 } else if (host->data) {
1246 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1247 __func__, host->mrq->cmd->opcode,
1248 host->data->blocks);
1249 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1250 host->data);
1251 }
1252 }
1253 }
1254
1255 static irqreturn_t msdc_irq(int irq, void *dev_id)
1256 {
1257 struct msdc_host *host = (struct msdc_host *) dev_id;
1258
1259 while (true) {
1260 unsigned long flags;
1261 struct mmc_request *mrq;
1262 struct mmc_command *cmd;
1263 struct mmc_data *data;
1264 u32 events, event_mask;
1265
1266 spin_lock_irqsave(&host->lock, flags);
1267 events = readl(host->base + MSDC_INT);
1268 event_mask = readl(host->base + MSDC_INTEN);
1269 /* clear interrupts */
1270 writel(events & event_mask, host->base + MSDC_INT);
1271
1272 mrq = host->mrq;
1273 cmd = host->cmd;
1274 data = host->data;
1275 spin_unlock_irqrestore(&host->lock, flags);
1276
1277 if (!(events & event_mask))
1278 break;
1279
1280 if (!mrq) {
1281 dev_err(host->dev,
1282 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1283 __func__, events, event_mask);
1284 WARN_ON(1);
1285 break;
1286 }
1287
1288 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1289
1290 if (cmd)
1291 msdc_cmd_done(host, events, mrq, cmd);
1292 else if (data)
1293 msdc_data_xfer_done(host, events, mrq, data);
1294 }
1295
1296 return IRQ_HANDLED;
1297 }
1298
1299 static void msdc_init_hw(struct msdc_host *host)
1300 {
1301 u32 val;
1302 u32 tune_reg = host->dev_comp->pad_tune_reg;
1303
1304 /* Configure to MMC/SD mode, clock free running */
1305 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1306
1307 /* Reset */
1308 msdc_reset_hw(host);
1309
1310 /* Disable card detection */
1311 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1312
1313 /* Disable and clear all interrupts */
1314 writel(0, host->base + MSDC_INTEN);
1315 val = readl(host->base + MSDC_INT);
1316 writel(val, host->base + MSDC_INT);
1317
1318 writel(0, host->base + tune_reg);
1319 writel(0, host->base + MSDC_IOCON);
1320 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1321 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1322 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1323 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1324 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1325
1326 if (host->dev_comp->stop_clk_fix) {
1327 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1328 MSDC_PATCH_BIT1_STOP_DLY, 3);
1329 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1330 SDC_FIFO_CFG_WRVALIDSEL);
1331 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1332 SDC_FIFO_CFG_RDVALIDSEL);
1333 }
1334
1335 if (host->dev_comp->busy_check)
1336 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1337
1338 if (host->dev_comp->async_fifo) {
1339 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1340 MSDC_PB2_RESPWAIT, 3);
1341 if (host->dev_comp->enhance_rx) {
1342 sdr_set_bits(host->base + SDC_ADV_CFG0,
1343 SDC_RX_ENHANCE_EN);
1344 } else {
1345 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1346 MSDC_PB2_RESPSTSENSEL, 2);
1347 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1348 MSDC_PB2_CRCSTSENSEL, 2);
1349 }
1350 /* use async fifo, then no need tune internal delay */
1351 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1352 MSDC_PATCH_BIT2_CFGRESP);
1353 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1354 MSDC_PATCH_BIT2_CFGCRCSTS);
1355 }
1356
1357 if (host->dev_comp->data_tune) {
1358 sdr_set_bits(host->base + tune_reg,
1359 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1360 } else {
1361 /* choose clock tune */
1362 sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1363 }
1364
1365 /* Configure to enable SDIO mode.
1366 * it's must otherwise sdio cmd5 failed
1367 */
1368 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1369
1370 /* disable detect SDIO device interrupt function */
1371 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1372
1373 /* Configure to default data timeout */
1374 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1375
1376 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1377 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1378 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1379 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1380 dev_dbg(host->dev, "init hardware done!");
1381 }
1382
1383 static void msdc_deinit_hw(struct msdc_host *host)
1384 {
1385 u32 val;
1386 /* Disable and clear all interrupts */
1387 writel(0, host->base + MSDC_INTEN);
1388
1389 val = readl(host->base + MSDC_INT);
1390 writel(val, host->base + MSDC_INT);
1391 }
1392
1393 /* init gpd and bd list in msdc_drv_probe */
1394 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1395 {
1396 struct mt_gpdma_desc *gpd = dma->gpd;
1397 struct mt_bdma_desc *bd = dma->bd;
1398 int i;
1399
1400 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1401
1402 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1403 gpd->ptr = (u32)dma->bd_addr; /* physical address */
1404 /* gpd->next is must set for desc DMA
1405 * That's why must alloc 2 gpd structure.
1406 */
1407 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1408 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1409 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1410 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1411 }
1412
1413 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1414 {
1415 struct msdc_host *host = mmc_priv(mmc);
1416 int ret;
1417
1418 msdc_set_buswidth(host, ios->bus_width);
1419
1420 /* Suspend/Resume will do power off/on */
1421 switch (ios->power_mode) {
1422 case MMC_POWER_UP:
1423 if (!IS_ERR(mmc->supply.vmmc)) {
1424 msdc_init_hw(host);
1425 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1426 ios->vdd);
1427 if (ret) {
1428 dev_err(host->dev, "Failed to set vmmc power!\n");
1429 return;
1430 }
1431 }
1432 break;
1433 case MMC_POWER_ON:
1434 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1435 ret = regulator_enable(mmc->supply.vqmmc);
1436 if (ret)
1437 dev_err(host->dev, "Failed to set vqmmc power!\n");
1438 else
1439 host->vqmmc_enabled = true;
1440 }
1441 break;
1442 case MMC_POWER_OFF:
1443 if (!IS_ERR(mmc->supply.vmmc))
1444 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1445
1446 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1447 regulator_disable(mmc->supply.vqmmc);
1448 host->vqmmc_enabled = false;
1449 }
1450 break;
1451 default:
1452 break;
1453 }
1454
1455 if (host->mclk != ios->clock || host->timing != ios->timing)
1456 msdc_set_mclk(host, ios->timing, ios->clock);
1457 }
1458
1459 static u32 test_delay_bit(u32 delay, u32 bit)
1460 {
1461 bit %= PAD_DELAY_MAX;
1462 return delay & (1 << bit);
1463 }
1464
1465 static int get_delay_len(u32 delay, u32 start_bit)
1466 {
1467 int i;
1468
1469 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1470 if (test_delay_bit(delay, start_bit + i) == 0)
1471 return i;
1472 }
1473 return PAD_DELAY_MAX - start_bit;
1474 }
1475
1476 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1477 {
1478 int start = 0, len = 0;
1479 int start_final = 0, len_final = 0;
1480 u8 final_phase = 0xff;
1481 struct msdc_delay_phase delay_phase = { 0, };
1482
1483 if (delay == 0) {
1484 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1485 delay_phase.final_phase = final_phase;
1486 return delay_phase;
1487 }
1488
1489 while (start < PAD_DELAY_MAX) {
1490 len = get_delay_len(delay, start);
1491 if (len_final < len) {
1492 start_final = start;
1493 len_final = len;
1494 }
1495 start += len ? len : 1;
1496 if (len >= 12 && start_final < 4)
1497 break;
1498 }
1499
1500 /* The rule is that to find the smallest delay cell */
1501 if (start_final == 0)
1502 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1503 else
1504 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1505 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1506 delay, len_final, final_phase);
1507
1508 delay_phase.maxlen = len_final;
1509 delay_phase.start = start_final;
1510 delay_phase.final_phase = final_phase;
1511 return delay_phase;
1512 }
1513
1514 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1515 {
1516 struct msdc_host *host = mmc_priv(mmc);
1517 u32 rise_delay = 0, fall_delay = 0;
1518 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1519 struct msdc_delay_phase internal_delay_phase;
1520 u8 final_delay, final_maxlen;
1521 u32 internal_delay = 0;
1522 u32 tune_reg = host->dev_comp->pad_tune_reg;
1523 int cmd_err;
1524 int i, j;
1525
1526 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1527 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1528 sdr_set_field(host->base + tune_reg,
1529 MSDC_PAD_TUNE_CMDRRDLY,
1530 host->hs200_cmd_int_delay);
1531
1532 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1533 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1534 sdr_set_field(host->base + tune_reg,
1535 MSDC_PAD_TUNE_CMDRDLY, i);
1536 /*
1537 * Using the same parameters, it may sometimes pass the test,
1538 * but sometimes it may fail. To make sure the parameters are
1539 * more stable, we test each set of parameters 3 times.
1540 */
1541 for (j = 0; j < 3; j++) {
1542 mmc_send_tuning(mmc, opcode, &cmd_err);
1543 if (!cmd_err) {
1544 rise_delay |= (1 << i);
1545 } else {
1546 rise_delay &= ~(1 << i);
1547 break;
1548 }
1549 }
1550 }
1551 final_rise_delay = get_best_delay(host, rise_delay);
1552 /* if rising edge has enough margin, then do not scan falling edge */
1553 if (final_rise_delay.maxlen >= 12 ||
1554 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1555 goto skip_fall;
1556
1557 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1558 for (i = 0; i < PAD_DELAY_MAX; i++) {
1559 sdr_set_field(host->base + tune_reg,
1560 MSDC_PAD_TUNE_CMDRDLY, i);
1561 /*
1562 * Using the same parameters, it may sometimes pass the test,
1563 * but sometimes it may fail. To make sure the parameters are
1564 * more stable, we test each set of parameters 3 times.
1565 */
1566 for (j = 0; j < 3; j++) {
1567 mmc_send_tuning(mmc, opcode, &cmd_err);
1568 if (!cmd_err) {
1569 fall_delay |= (1 << i);
1570 } else {
1571 fall_delay &= ~(1 << i);
1572 break;
1573 }
1574 }
1575 }
1576 final_fall_delay = get_best_delay(host, fall_delay);
1577
1578 skip_fall:
1579 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1580 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1581 final_maxlen = final_fall_delay.maxlen;
1582 if (final_maxlen == final_rise_delay.maxlen) {
1583 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1584 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1585 final_rise_delay.final_phase);
1586 final_delay = final_rise_delay.final_phase;
1587 } else {
1588 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1589 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1590 final_fall_delay.final_phase);
1591 final_delay = final_fall_delay.final_phase;
1592 }
1593 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1594 goto skip_internal;
1595
1596 for (i = 0; i < PAD_DELAY_MAX; i++) {
1597 sdr_set_field(host->base + tune_reg,
1598 MSDC_PAD_TUNE_CMDRRDLY, i);
1599 mmc_send_tuning(mmc, opcode, &cmd_err);
1600 if (!cmd_err)
1601 internal_delay |= (1 << i);
1602 }
1603 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1604 internal_delay_phase = get_best_delay(host, internal_delay);
1605 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
1606 internal_delay_phase.final_phase);
1607 skip_internal:
1608 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1609 return final_delay == 0xff ? -EIO : 0;
1610 }
1611
1612 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1613 {
1614 struct msdc_host *host = mmc_priv(mmc);
1615 u32 cmd_delay = 0;
1616 struct msdc_delay_phase final_cmd_delay = { 0,};
1617 u8 final_delay;
1618 int cmd_err;
1619 int i, j;
1620
1621 /* select EMMC50 PAD CMD tune */
1622 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1623
1624 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1625 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1626 sdr_set_field(host->base + MSDC_PAD_TUNE,
1627 MSDC_PAD_TUNE_CMDRRDLY,
1628 host->hs200_cmd_int_delay);
1629
1630 if (host->hs400_cmd_resp_sel_rising)
1631 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1632 else
1633 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1634 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1635 sdr_set_field(host->base + PAD_CMD_TUNE,
1636 PAD_CMD_TUNE_RX_DLY3, i);
1637 /*
1638 * Using the same parameters, it may sometimes pass the test,
1639 * but sometimes it may fail. To make sure the parameters are
1640 * more stable, we test each set of parameters 3 times.
1641 */
1642 for (j = 0; j < 3; j++) {
1643 mmc_send_tuning(mmc, opcode, &cmd_err);
1644 if (!cmd_err) {
1645 cmd_delay |= (1 << i);
1646 } else {
1647 cmd_delay &= ~(1 << i);
1648 break;
1649 }
1650 }
1651 }
1652 final_cmd_delay = get_best_delay(host, cmd_delay);
1653 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1654 final_cmd_delay.final_phase);
1655 final_delay = final_cmd_delay.final_phase;
1656
1657 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1658 return final_delay == 0xff ? -EIO : 0;
1659 }
1660
1661 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1662 {
1663 struct msdc_host *host = mmc_priv(mmc);
1664 u32 rise_delay = 0, fall_delay = 0;
1665 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1666 u8 final_delay, final_maxlen;
1667 u32 tune_reg = host->dev_comp->pad_tune_reg;
1668 int i, ret;
1669
1670 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1671 host->latch_ck);
1672 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1673 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1674 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1675 sdr_set_field(host->base + tune_reg,
1676 MSDC_PAD_TUNE_DATRRDLY, i);
1677 ret = mmc_send_tuning(mmc, opcode, NULL);
1678 if (!ret)
1679 rise_delay |= (1 << i);
1680 }
1681 final_rise_delay = get_best_delay(host, rise_delay);
1682 /* if rising edge has enough margin, then do not scan falling edge */
1683 if (final_rise_delay.maxlen >= 12 ||
1684 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1685 goto skip_fall;
1686
1687 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1688 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1689 for (i = 0; i < PAD_DELAY_MAX; i++) {
1690 sdr_set_field(host->base + tune_reg,
1691 MSDC_PAD_TUNE_DATRRDLY, i);
1692 ret = mmc_send_tuning(mmc, opcode, NULL);
1693 if (!ret)
1694 fall_delay |= (1 << i);
1695 }
1696 final_fall_delay = get_best_delay(host, fall_delay);
1697
1698 skip_fall:
1699 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1700 if (final_maxlen == final_rise_delay.maxlen) {
1701 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1702 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1703 sdr_set_field(host->base + tune_reg,
1704 MSDC_PAD_TUNE_DATRRDLY,
1705 final_rise_delay.final_phase);
1706 final_delay = final_rise_delay.final_phase;
1707 } else {
1708 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1709 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1710 sdr_set_field(host->base + tune_reg,
1711 MSDC_PAD_TUNE_DATRRDLY,
1712 final_fall_delay.final_phase);
1713 final_delay = final_fall_delay.final_phase;
1714 }
1715
1716 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1717 return final_delay == 0xff ? -EIO : 0;
1718 }
1719
1720 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1721 {
1722 struct msdc_host *host = mmc_priv(mmc);
1723 int ret;
1724 u32 tune_reg = host->dev_comp->pad_tune_reg;
1725
1726 if (host->hs400_mode &&
1727 host->dev_comp->hs400_tune)
1728 ret = hs400_tune_response(mmc, opcode);
1729 else
1730 ret = msdc_tune_response(mmc, opcode);
1731 if (ret == -EIO) {
1732 dev_err(host->dev, "Tune response fail!\n");
1733 return ret;
1734 }
1735 if (host->hs400_mode == false) {
1736 ret = msdc_tune_data(mmc, opcode);
1737 if (ret == -EIO)
1738 dev_err(host->dev, "Tune data fail!\n");
1739 }
1740
1741 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1742 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1743 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
1744 return ret;
1745 }
1746
1747 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1748 {
1749 struct msdc_host *host = mmc_priv(mmc);
1750 host->hs400_mode = true;
1751
1752 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1753 /* hs400 mode must set it to 0 */
1754 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
1755 /* to improve read performance, set outstanding to 2 */
1756 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
1757
1758 return 0;
1759 }
1760
1761 static void msdc_hw_reset(struct mmc_host *mmc)
1762 {
1763 struct msdc_host *host = mmc_priv(mmc);
1764
1765 sdr_set_bits(host->base + EMMC_IOCON, 1);
1766 udelay(10); /* 10us is enough */
1767 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1768 }
1769
1770 static const struct mmc_host_ops mt_msdc_ops = {
1771 .post_req = msdc_post_req,
1772 .pre_req = msdc_pre_req,
1773 .request = msdc_ops_request,
1774 .set_ios = msdc_ops_set_ios,
1775 .get_ro = mmc_gpio_get_ro,
1776 .get_cd = mmc_gpio_get_cd,
1777 .start_signal_voltage_switch = msdc_ops_switch_volt,
1778 .card_busy = msdc_card_busy,
1779 .execute_tuning = msdc_execute_tuning,
1780 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
1781 .hw_reset = msdc_hw_reset,
1782 };
1783
1784 static void msdc_of_property_parse(struct platform_device *pdev,
1785 struct msdc_host *host)
1786 {
1787 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
1788 &host->latch_ck);
1789
1790 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1791 &host->hs400_ds_delay);
1792
1793 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
1794 &host->hs200_cmd_int_delay);
1795
1796 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
1797 &host->hs400_cmd_int_delay);
1798
1799 if (of_property_read_bool(pdev->dev.of_node,
1800 "mediatek,hs400-cmd-resp-sel-rising"))
1801 host->hs400_cmd_resp_sel_rising = true;
1802 else
1803 host->hs400_cmd_resp_sel_rising = false;
1804 }
1805
1806 static int msdc_drv_probe(struct platform_device *pdev)
1807 {
1808 struct mmc_host *mmc;
1809 struct msdc_host *host;
1810 struct resource *res;
1811 const struct of_device_id *of_id;
1812 int ret;
1813
1814 if (!pdev->dev.of_node) {
1815 dev_err(&pdev->dev, "No DT found\n");
1816 return -EINVAL;
1817 }
1818
1819 of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
1820 if (!of_id)
1821 return -EINVAL;
1822 /* Allocate MMC host for this device */
1823 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1824 if (!mmc)
1825 return -ENOMEM;
1826
1827 host = mmc_priv(mmc);
1828 ret = mmc_of_parse(mmc);
1829 if (ret)
1830 goto host_free;
1831
1832 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1833 host->base = devm_ioremap_resource(&pdev->dev, res);
1834 if (IS_ERR(host->base)) {
1835 ret = PTR_ERR(host->base);
1836 goto host_free;
1837 }
1838
1839 ret = mmc_regulator_get_supply(mmc);
1840 if (ret)
1841 goto host_free;
1842
1843 host->src_clk = devm_clk_get(&pdev->dev, "source");
1844 if (IS_ERR(host->src_clk)) {
1845 ret = PTR_ERR(host->src_clk);
1846 goto host_free;
1847 }
1848
1849 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1850 if (IS_ERR(host->h_clk)) {
1851 ret = PTR_ERR(host->h_clk);
1852 goto host_free;
1853 }
1854
1855 /*source clock control gate is optional clock*/
1856 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
1857 if (IS_ERR(host->src_clk_cg))
1858 host->src_clk_cg = NULL;
1859
1860 host->irq = platform_get_irq(pdev, 0);
1861 if (host->irq < 0) {
1862 ret = -EINVAL;
1863 goto host_free;
1864 }
1865
1866 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1867 if (IS_ERR(host->pinctrl)) {
1868 ret = PTR_ERR(host->pinctrl);
1869 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1870 goto host_free;
1871 }
1872
1873 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1874 if (IS_ERR(host->pins_default)) {
1875 ret = PTR_ERR(host->pins_default);
1876 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1877 goto host_free;
1878 }
1879
1880 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1881 if (IS_ERR(host->pins_uhs)) {
1882 ret = PTR_ERR(host->pins_uhs);
1883 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1884 goto host_free;
1885 }
1886
1887 msdc_of_property_parse(pdev, host);
1888
1889 host->dev = &pdev->dev;
1890 host->dev_comp = of_id->data;
1891 host->mmc = mmc;
1892 host->src_clk_freq = clk_get_rate(host->src_clk);
1893 /* Set host parameters to mmc */
1894 mmc->ops = &mt_msdc_ops;
1895 if (host->dev_comp->clk_div_bits == 8)
1896 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
1897 else
1898 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
1899
1900 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1901 /* MMC core transfer sizes tunable parameters */
1902 mmc->max_segs = MAX_BD_NUM;
1903 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1904 mmc->max_blk_size = 2048;
1905 mmc->max_req_size = 512 * 1024;
1906 mmc->max_blk_count = mmc->max_req_size / 512;
1907 host->dma_mask = DMA_BIT_MASK(32);
1908 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1909
1910 host->timeout_clks = 3 * 1048576;
1911 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1912 2 * sizeof(struct mt_gpdma_desc),
1913 &host->dma.gpd_addr, GFP_KERNEL);
1914 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1915 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1916 &host->dma.bd_addr, GFP_KERNEL);
1917 if (!host->dma.gpd || !host->dma.bd) {
1918 ret = -ENOMEM;
1919 goto release_mem;
1920 }
1921 msdc_init_gpd_bd(host, &host->dma);
1922 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1923 spin_lock_init(&host->lock);
1924
1925 platform_set_drvdata(pdev, mmc);
1926 msdc_ungate_clock(host);
1927 msdc_init_hw(host);
1928
1929 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1930 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1931 if (ret)
1932 goto release;
1933
1934 pm_runtime_set_active(host->dev);
1935 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1936 pm_runtime_use_autosuspend(host->dev);
1937 pm_runtime_enable(host->dev);
1938 ret = mmc_add_host(mmc);
1939
1940 if (ret)
1941 goto end;
1942
1943 return 0;
1944 end:
1945 pm_runtime_disable(host->dev);
1946 release:
1947 platform_set_drvdata(pdev, NULL);
1948 msdc_deinit_hw(host);
1949 msdc_gate_clock(host);
1950 release_mem:
1951 if (host->dma.gpd)
1952 dma_free_coherent(&pdev->dev,
1953 2 * sizeof(struct mt_gpdma_desc),
1954 host->dma.gpd, host->dma.gpd_addr);
1955 if (host->dma.bd)
1956 dma_free_coherent(&pdev->dev,
1957 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1958 host->dma.bd, host->dma.bd_addr);
1959 host_free:
1960 mmc_free_host(mmc);
1961
1962 return ret;
1963 }
1964
1965 static int msdc_drv_remove(struct platform_device *pdev)
1966 {
1967 struct mmc_host *mmc;
1968 struct msdc_host *host;
1969
1970 mmc = platform_get_drvdata(pdev);
1971 host = mmc_priv(mmc);
1972
1973 pm_runtime_get_sync(host->dev);
1974
1975 platform_set_drvdata(pdev, NULL);
1976 mmc_remove_host(host->mmc);
1977 msdc_deinit_hw(host);
1978 msdc_gate_clock(host);
1979
1980 pm_runtime_disable(host->dev);
1981 pm_runtime_put_noidle(host->dev);
1982 dma_free_coherent(&pdev->dev,
1983 2 * sizeof(struct mt_gpdma_desc),
1984 host->dma.gpd, host->dma.gpd_addr);
1985 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1986 host->dma.bd, host->dma.bd_addr);
1987
1988 mmc_free_host(host->mmc);
1989
1990 return 0;
1991 }
1992
1993 #ifdef CONFIG_PM
1994 static void msdc_save_reg(struct msdc_host *host)
1995 {
1996 u32 tune_reg = host->dev_comp->pad_tune_reg;
1997
1998 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1999 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2000 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2001 host->save_para.pad_tune = readl(host->base + tune_reg);
2002 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2003 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2004 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2005 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2006 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2007 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2008 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2009 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2010 }
2011
2012 static void msdc_restore_reg(struct msdc_host *host)
2013 {
2014 u32 tune_reg = host->dev_comp->pad_tune_reg;
2015
2016 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2017 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2018 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2019 writel(host->save_para.pad_tune, host->base + tune_reg);
2020 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2021 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2022 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2023 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2024 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2025 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2026 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2027 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2028 }
2029
2030 static int msdc_runtime_suspend(struct device *dev)
2031 {
2032 struct mmc_host *mmc = dev_get_drvdata(dev);
2033 struct msdc_host *host = mmc_priv(mmc);
2034
2035 msdc_save_reg(host);
2036 msdc_gate_clock(host);
2037 return 0;
2038 }
2039
2040 static int msdc_runtime_resume(struct device *dev)
2041 {
2042 struct mmc_host *mmc = dev_get_drvdata(dev);
2043 struct msdc_host *host = mmc_priv(mmc);
2044
2045 msdc_ungate_clock(host);
2046 msdc_restore_reg(host);
2047 return 0;
2048 }
2049 #endif
2050
2051 static const struct dev_pm_ops msdc_dev_pm_ops = {
2052 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2053 pm_runtime_force_resume)
2054 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2055 };
2056
2057 static struct platform_driver mt_msdc_driver = {
2058 .probe = msdc_drv_probe,
2059 .remove = msdc_drv_remove,
2060 .driver = {
2061 .name = "mtk-msdc",
2062 .of_match_table = msdc_of_ids,
2063 .pm = &msdc_dev_pm_ops,
2064 },
2065 };
2066
2067 module_platform_driver(mt_msdc_driver);
2068 MODULE_LICENSE("GPL v2");
2069 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
Linux with added FPC-III support