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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / media / platform / omap3isp / isp.c
blob842e2235047d9c6327a65e1ab4fd9ea468fc015a
1 /*
2 * isp.c
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2006-2010 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * Contributors:
13 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 * Sakari Ailus <sakari.ailus@iki.fi>
15 * David Cohen <dacohen@gmail.com>
16 * Stanimir Varbanov <svarbanov@mm-sol.com>
17 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
18 * Tuukka Toivonen <tuukkat76@gmail.com>
19 * Sergio Aguirre <saaguirre@ti.com>
20 * Antti Koskipaa <akoskipa@gmail.com>
21 * Ivan T. Ivanov <iivanov@mm-sol.com>
22 * RaniSuneela <r-m@ti.com>
23 * Atanas Filipov <afilipov@mm-sol.com>
24 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
25 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
26 * Nayden Kanchev <nkanchev@mm-sol.com>
27 * Phil Carmody <ext-phil.2.carmody@nokia.com>
28 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
29 * Dominic Curran <dcurran@ti.com>
30 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
31 * Pallavi Kulkarni <p-kulkarni@ti.com>
32 * Vaibhav Hiremath <hvaibhav@ti.com>
33 * Mohit Jalori <mjalori@ti.com>
34 * Sameer Venkatraman <sameerv@ti.com>
35 * Senthilvadivu Guruswamy <svadivu@ti.com>
36 * Thara Gopinath <thara@ti.com>
37 * Toni Leinonen <toni.leinonen@nokia.com>
38 * Troy Laramy <t-laramy@ti.com>
39 *
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
43 */
44
45 #include <asm/cacheflush.h>
46
47 #include <linux/clk.h>
48 #include <linux/clkdev.h>
49 #include <linux/delay.h>
50 #include <linux/device.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/i2c.h>
53 #include <linux/interrupt.h>
54 #include <linux/mfd/syscon.h>
55 #include <linux/module.h>
56 #include <linux/omap-iommu.h>
57 #include <linux/platform_device.h>
58 #include <linux/property.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/slab.h>
61 #include <linux/sched.h>
62 #include <linux/vmalloc.h>
63
64 #ifdef CONFIG_ARM_DMA_USE_IOMMU
65 #include <asm/dma-iommu.h>
66 #endif
67
68 #include <media/v4l2-common.h>
69 #include <media/v4l2-fwnode.h>
70 #include <media/v4l2-device.h>
71 #include <media/v4l2-mc.h>
72
73 #include "isp.h"
74 #include "ispreg.h"
75 #include "ispccdc.h"
76 #include "isppreview.h"
77 #include "ispresizer.h"
78 #include "ispcsi2.h"
79 #include "ispccp2.h"
80 #include "isph3a.h"
81 #include "isphist.h"
82
83 static unsigned int autoidle;
84 module_param(autoidle, int, 0444);
85 MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
86
87 static void isp_save_ctx(struct isp_device *isp);
88
89 static void isp_restore_ctx(struct isp_device *isp);
90
91 static const struct isp_res_mapping isp_res_maps[] = {
92 {
93 .isp_rev = ISP_REVISION_2_0,
94 .offset = {
95 /* first MMIO area */
96 0x0000, /* base, len 0x0070 */
97 0x0400, /* ccp2, len 0x01f0 */
98 0x0600, /* ccdc, len 0x00a8 */
99 0x0a00, /* hist, len 0x0048 */
100 0x0c00, /* h3a, len 0x0060 */
101 0x0e00, /* preview, len 0x00a0 */
102 0x1000, /* resizer, len 0x00ac */
103 0x1200, /* sbl, len 0x00fc */
104 /* second MMIO area */
105 0x0000, /* csi2a, len 0x0170 */
106 0x0170, /* csiphy2, len 0x000c */
107 },
108 .phy_type = ISP_PHY_TYPE_3430,
109 },
110 {
111 .isp_rev = ISP_REVISION_15_0,
112 .offset = {
113 /* first MMIO area */
114 0x0000, /* base, len 0x0070 */
115 0x0400, /* ccp2, len 0x01f0 */
116 0x0600, /* ccdc, len 0x00a8 */
117 0x0a00, /* hist, len 0x0048 */
118 0x0c00, /* h3a, len 0x0060 */
119 0x0e00, /* preview, len 0x00a0 */
120 0x1000, /* resizer, len 0x00ac */
121 0x1200, /* sbl, len 0x00fc */
122 /* second MMIO area */
123 0x0000, /* csi2a, len 0x0170 (1st area) */
124 0x0170, /* csiphy2, len 0x000c */
125 0x01c0, /* csi2a, len 0x0040 (2nd area) */
126 0x0400, /* csi2c, len 0x0170 (1st area) */
127 0x0570, /* csiphy1, len 0x000c */
128 0x05c0, /* csi2c, len 0x0040 (2nd area) */
129 },
130 .phy_type = ISP_PHY_TYPE_3630,
131 },
132 };
133
134 /* Structure for saving/restoring ISP module registers */
135 static struct isp_reg isp_reg_list[] = {
136 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
137 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
138 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
139 {0, ISP_TOK_TERM, 0}
140 };
141
142 /*
143 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
144 * @isp: OMAP3 ISP device
145 *
146 * In order to force posting of pending writes, we need to write and
147 * readback the same register, in this case the revision register.
148 *
149 * See this link for reference:
150 * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
151 */
152 void omap3isp_flush(struct isp_device *isp)
153 {
154 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
155 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
156 }
157
158 /* -----------------------------------------------------------------------------
159 * XCLK
160 */
161
162 #define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw)
163
164 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
165 {
166 switch (xclk->id) {
167 case ISP_XCLK_A:
168 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
169 ISPTCTRL_CTRL_DIVA_MASK,
170 divider << ISPTCTRL_CTRL_DIVA_SHIFT);
171 break;
172 case ISP_XCLK_B:
173 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
174 ISPTCTRL_CTRL_DIVB_MASK,
175 divider << ISPTCTRL_CTRL_DIVB_SHIFT);
176 break;
177 }
178 }
179
180 static int isp_xclk_prepare(struct clk_hw *hw)
181 {
182 struct isp_xclk *xclk = to_isp_xclk(hw);
183
184 omap3isp_get(xclk->isp);
185
186 return 0;
187 }
188
189 static void isp_xclk_unprepare(struct clk_hw *hw)
190 {
191 struct isp_xclk *xclk = to_isp_xclk(hw);
192
193 omap3isp_put(xclk->isp);
194 }
195
196 static int isp_xclk_enable(struct clk_hw *hw)
197 {
198 struct isp_xclk *xclk = to_isp_xclk(hw);
199 unsigned long flags;
200
201 spin_lock_irqsave(&xclk->lock, flags);
202 isp_xclk_update(xclk, xclk->divider);
203 xclk->enabled = true;
204 spin_unlock_irqrestore(&xclk->lock, flags);
205
206 return 0;
207 }
208
209 static void isp_xclk_disable(struct clk_hw *hw)
210 {
211 struct isp_xclk *xclk = to_isp_xclk(hw);
212 unsigned long flags;
213
214 spin_lock_irqsave(&xclk->lock, flags);
215 isp_xclk_update(xclk, 0);
216 xclk->enabled = false;
217 spin_unlock_irqrestore(&xclk->lock, flags);
218 }
219
220 static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw,
221 unsigned long parent_rate)
222 {
223 struct isp_xclk *xclk = to_isp_xclk(hw);
224
225 return parent_rate / xclk->divider;
226 }
227
228 static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
229 {
230 u32 divider;
231
232 if (*rate >= parent_rate) {
233 *rate = parent_rate;
234 return ISPTCTRL_CTRL_DIV_BYPASS;
235 }
236
237 if (*rate == 0)
238 *rate = 1;
239
240 divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
241 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
242 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
243
244 *rate = parent_rate / divider;
245 return divider;
246 }
247
248 static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
249 unsigned long *parent_rate)
250 {
251 isp_xclk_calc_divider(&rate, *parent_rate);
252 return rate;
253 }
254
255 static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate,
256 unsigned long parent_rate)
257 {
258 struct isp_xclk *xclk = to_isp_xclk(hw);
259 unsigned long flags;
260 u32 divider;
261
262 divider = isp_xclk_calc_divider(&rate, parent_rate);
263
264 spin_lock_irqsave(&xclk->lock, flags);
265
266 xclk->divider = divider;
267 if (xclk->enabled)
268 isp_xclk_update(xclk, divider);
269
270 spin_unlock_irqrestore(&xclk->lock, flags);
271
272 dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n",
273 __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
274 return 0;
275 }
276
277 static const struct clk_ops isp_xclk_ops = {
278 .prepare = isp_xclk_prepare,
279 .unprepare = isp_xclk_unprepare,
280 .enable = isp_xclk_enable,
281 .disable = isp_xclk_disable,
282 .recalc_rate = isp_xclk_recalc_rate,
283 .round_rate = isp_xclk_round_rate,
284 .set_rate = isp_xclk_set_rate,
285 };
286
287 static const char *isp_xclk_parent_name = "cam_mclk";
288
289 static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data)
290 {
291 unsigned int idx = clkspec->args[0];
292 struct isp_device *isp = data;
293
294 if (idx >= ARRAY_SIZE(isp->xclks))
295 return ERR_PTR(-ENOENT);
296
297 return isp->xclks[idx].clk;
298 }
299
300 static int isp_xclk_init(struct isp_device *isp)
301 {
302 struct device_node *np = isp->dev->of_node;
303 struct clk_init_data init = {};
304 unsigned int i;
305
306 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i)
307 isp->xclks[i].clk = ERR_PTR(-EINVAL);
308
309 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
310 struct isp_xclk *xclk = &isp->xclks[i];
311
312 xclk->isp = isp;
313 xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B;
314 xclk->divider = 1;
315 spin_lock_init(&xclk->lock);
316
317 init.name = i == 0 ? "cam_xclka" : "cam_xclkb";
318 init.ops = &isp_xclk_ops;
319 init.parent_names = &isp_xclk_parent_name;
320 init.num_parents = 1;
321
322 xclk->hw.init = &init;
323 /*
324 * The first argument is NULL in order to avoid circular
325 * reference, as this driver takes reference on the
326 * sensor subdevice modules and the sensors would take
327 * reference on this module through clk_get().
328 */
329 xclk->clk = clk_register(NULL, &xclk->hw);
330 if (IS_ERR(xclk->clk))
331 return PTR_ERR(xclk->clk);
332 }
333
334 if (np)
335 of_clk_add_provider(np, isp_xclk_src_get, isp);
336
337 return 0;
338 }
339
340 static void isp_xclk_cleanup(struct isp_device *isp)
341 {
342 struct device_node *np = isp->dev->of_node;
343 unsigned int i;
344
345 if (np)
346 of_clk_del_provider(np);
347
348 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
349 struct isp_xclk *xclk = &isp->xclks[i];
350
351 if (!IS_ERR(xclk->clk))
352 clk_unregister(xclk->clk);
353 }
354 }
355
356 /* -----------------------------------------------------------------------------
357 * Interrupts
358 */
359
360 /*
361 * isp_enable_interrupts - Enable ISP interrupts.
362 * @isp: OMAP3 ISP device
363 */
364 static void isp_enable_interrupts(struct isp_device *isp)
365 {
366 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
367 | IRQ0ENABLE_CSIB_IRQ
368 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
369 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
370 | IRQ0ENABLE_CCDC_VD0_IRQ
371 | IRQ0ENABLE_CCDC_VD1_IRQ
372 | IRQ0ENABLE_HS_VS_IRQ
373 | IRQ0ENABLE_HIST_DONE_IRQ
374 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
375 | IRQ0ENABLE_H3A_AF_DONE_IRQ
376 | IRQ0ENABLE_PRV_DONE_IRQ
377 | IRQ0ENABLE_RSZ_DONE_IRQ;
378
379 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
380 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
381 }
382
383 /*
384 * isp_disable_interrupts - Disable ISP interrupts.
385 * @isp: OMAP3 ISP device
386 */
387 static void isp_disable_interrupts(struct isp_device *isp)
388 {
389 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
390 }
391
392 /*
393 * isp_core_init - ISP core settings
394 * @isp: OMAP3 ISP device
395 * @idle: Consider idle state.
396 *
397 * Set the power settings for the ISP and SBL bus and configure the HS/VS
398 * interrupt source.
399 *
400 * We need to configure the HS/VS interrupt source before interrupts get
401 * enabled, as the sensor might be free-running and the ISP default setting
402 * (HS edge) would put an unnecessary burden on the CPU.
403 */
404 static void isp_core_init(struct isp_device *isp, int idle)
405 {
406 isp_reg_writel(isp,
407 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
408 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
409 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
410 ((isp->revision == ISP_REVISION_15_0) ?
411 ISP_SYSCONFIG_AUTOIDLE : 0),
412 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
413
414 isp_reg_writel(isp,
415 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
416 ISPCTRL_SYNC_DETECT_VSRISE,
417 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
418 }
419
420 /*
421 * Configure the bridge and lane shifter. Valid inputs are
422 *
423 * CCDC_INPUT_PARALLEL: Parallel interface
424 * CCDC_INPUT_CSI2A: CSI2a receiver
425 * CCDC_INPUT_CCP2B: CCP2b receiver
426 * CCDC_INPUT_CSI2C: CSI2c receiver
427 *
428 * The bridge and lane shifter are configured according to the selected input
429 * and the ISP platform data.
430 */
431 void omap3isp_configure_bridge(struct isp_device *isp,
432 enum ccdc_input_entity input,
433 const struct isp_parallel_cfg *parcfg,
434 unsigned int shift, unsigned int bridge)
435 {
436 u32 ispctrl_val;
437
438 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
439 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
440 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
441 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
442 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
443 ispctrl_val |= bridge;
444
445 switch (input) {
446 case CCDC_INPUT_PARALLEL:
447 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
448 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
449 shift += parcfg->data_lane_shift;
450 break;
451
452 case CCDC_INPUT_CSI2A:
453 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
454 break;
455
456 case CCDC_INPUT_CCP2B:
457 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
458 break;
459
460 case CCDC_INPUT_CSI2C:
461 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
462 break;
463
464 default:
465 return;
466 }
467
468 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
469
470 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
471 }
472
473 void omap3isp_hist_dma_done(struct isp_device *isp)
474 {
475 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
476 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
477 /* Histogram cannot be enabled in this frame anymore */
478 atomic_set(&isp->isp_hist.buf_err, 1);
479 dev_dbg(isp->dev,
480 "hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
481 }
482 }
483
484 static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
485 {
486 static const char *name[] = {
487 "CSIA_IRQ",
488 "res1",
489 "res2",
490 "CSIB_LCM_IRQ",
491 "CSIB_IRQ",
492 "res5",
493 "res6",
494 "res7",
495 "CCDC_VD0_IRQ",
496 "CCDC_VD1_IRQ",
497 "CCDC_VD2_IRQ",
498 "CCDC_ERR_IRQ",
499 "H3A_AF_DONE_IRQ",
500 "H3A_AWB_DONE_IRQ",
501 "res14",
502 "res15",
503 "HIST_DONE_IRQ",
504 "CCDC_LSC_DONE",
505 "CCDC_LSC_PREFETCH_COMPLETED",
506 "CCDC_LSC_PREFETCH_ERROR",
507 "PRV_DONE_IRQ",
508 "CBUFF_IRQ",
509 "res22",
510 "res23",
511 "RSZ_DONE_IRQ",
512 "OVF_IRQ",
513 "res26",
514 "res27",
515 "MMU_ERR_IRQ",
516 "OCP_ERR_IRQ",
517 "SEC_ERR_IRQ",
518 "HS_VS_IRQ",
519 };
520 int i;
521
522 dev_dbg(isp->dev, "ISP IRQ: ");
523
524 for (i = 0; i < ARRAY_SIZE(name); i++) {
525 if ((1 << i) & irqstatus)
526 printk(KERN_CONT "%s ", name[i]);
527 }
528 printk(KERN_CONT "\n");
529 }
530
531 static void isp_isr_sbl(struct isp_device *isp)
532 {
533 struct device *dev = isp->dev;
534 struct isp_pipeline *pipe;
535 u32 sbl_pcr;
536
537 /*
538 * Handle shared buffer logic overflows for video buffers.
539 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
540 */
541 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
542 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
543 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
544
545 if (sbl_pcr)
546 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
547
548 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
549 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
550 if (pipe != NULL)
551 pipe->error = true;
552 }
553
554 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
555 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
556 if (pipe != NULL)
557 pipe->error = true;
558 }
559
560 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
561 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
562 if (pipe != NULL)
563 pipe->error = true;
564 }
565
566 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
567 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
568 if (pipe != NULL)
569 pipe->error = true;
570 }
571
572 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
573 | ISPSBL_PCR_RSZ2_WBL_OVF
574 | ISPSBL_PCR_RSZ3_WBL_OVF
575 | ISPSBL_PCR_RSZ4_WBL_OVF)) {
576 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
577 if (pipe != NULL)
578 pipe->error = true;
579 }
580
581 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
582 omap3isp_stat_sbl_overflow(&isp->isp_af);
583
584 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
585 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
586 }
587
588 /*
589 * isp_isr - Interrupt Service Routine for Camera ISP module.
590 * @irq: Not used currently.
591 * @_isp: Pointer to the OMAP3 ISP device
592 *
593 * Handles the corresponding callback if plugged in.
594 */
595 static irqreturn_t isp_isr(int irq, void *_isp)
596 {
597 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
598 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
599 IRQ0STATUS_CCDC_VD0_IRQ |
600 IRQ0STATUS_CCDC_VD1_IRQ |
601 IRQ0STATUS_HS_VS_IRQ;
602 struct isp_device *isp = _isp;
603 u32 irqstatus;
604
605 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
606 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
607
608 isp_isr_sbl(isp);
609
610 if (irqstatus & IRQ0STATUS_CSIA_IRQ)
611 omap3isp_csi2_isr(&isp->isp_csi2a);
612
613 if (irqstatus & IRQ0STATUS_CSIB_IRQ)
614 omap3isp_ccp2_isr(&isp->isp_ccp2);
615
616 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
617 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
618 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
619 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
620 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
621 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
622 omap3isp_stat_isr_frame_sync(&isp->isp_af);
623 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
624 }
625
626 if (irqstatus & ccdc_events)
627 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
628
629 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
630 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
631 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
632 omap3isp_preview_isr(&isp->isp_prev);
633 }
634
635 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
636 omap3isp_resizer_isr(&isp->isp_res);
637
638 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
639 omap3isp_stat_isr(&isp->isp_aewb);
640
641 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
642 omap3isp_stat_isr(&isp->isp_af);
643
644 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
645 omap3isp_stat_isr(&isp->isp_hist);
646
647 omap3isp_flush(isp);
648
649 #if defined(DEBUG) && defined(ISP_ISR_DEBUG)
650 isp_isr_dbg(isp, irqstatus);
651 #endif
652
653 return IRQ_HANDLED;
654 }
655
656 static const struct media_device_ops isp_media_ops = {
657 .link_notify = v4l2_pipeline_link_notify,
658 };
659
660 /* -----------------------------------------------------------------------------
661 * Pipeline stream management
662 */
663
664 /*
665 * isp_pipeline_enable - Enable streaming on a pipeline
666 * @pipe: ISP pipeline
667 * @mode: Stream mode (single shot or continuous)
668 *
669 * Walk the entities chain starting at the pipeline output video node and start
670 * all modules in the chain in the given mode.
671 *
672 * Return 0 if successful, or the return value of the failed video::s_stream
673 * operation otherwise.
674 */
675 static int isp_pipeline_enable(struct isp_pipeline *pipe,
676 enum isp_pipeline_stream_state mode)
677 {
678 struct isp_device *isp = pipe->output->isp;
679 struct media_entity *entity;
680 struct media_pad *pad;
681 struct v4l2_subdev *subdev;
682 unsigned long flags;
683 int ret;
684
685 /* Refuse to start streaming if an entity included in the pipeline has
686 * crashed. This check must be performed before the loop below to avoid
687 * starting entities if the pipeline won't start anyway (those entities
688 * would then likely fail to stop, making the problem worse).
689 */
690 if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed))
691 return -EIO;
692
693 spin_lock_irqsave(&pipe->lock, flags);
694 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
695 spin_unlock_irqrestore(&pipe->lock, flags);
696
697 pipe->do_propagation = false;
698
699 entity = &pipe->output->video.entity;
700 while (1) {
701 pad = &entity->pads[0];
702 if (!(pad->flags & MEDIA_PAD_FL_SINK))
703 break;
704
705 pad = media_entity_remote_pad(pad);
706 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
707 break;
708
709 entity = pad->entity;
710 subdev = media_entity_to_v4l2_subdev(entity);
711
712 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
713 if (ret < 0 && ret != -ENOIOCTLCMD)
714 return ret;
715
716 if (subdev == &isp->isp_ccdc.subdev) {
717 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
718 s_stream, mode);
719 v4l2_subdev_call(&isp->isp_af.subdev, video,
720 s_stream, mode);
721 v4l2_subdev_call(&isp->isp_hist.subdev, video,
722 s_stream, mode);
723 pipe->do_propagation = true;
724 }
725 }
726
727 return 0;
728 }
729
730 static int isp_pipeline_wait_resizer(struct isp_device *isp)
731 {
732 return omap3isp_resizer_busy(&isp->isp_res);
733 }
734
735 static int isp_pipeline_wait_preview(struct isp_device *isp)
736 {
737 return omap3isp_preview_busy(&isp->isp_prev);
738 }
739
740 static int isp_pipeline_wait_ccdc(struct isp_device *isp)
741 {
742 return omap3isp_stat_busy(&isp->isp_af)
743 || omap3isp_stat_busy(&isp->isp_aewb)
744 || omap3isp_stat_busy(&isp->isp_hist)
745 || omap3isp_ccdc_busy(&isp->isp_ccdc);
746 }
747
748 #define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
749
750 static int isp_pipeline_wait(struct isp_device *isp,
751 int(*busy)(struct isp_device *isp))
752 {
753 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
754
755 while (!time_after(jiffies, timeout)) {
756 if (!busy(isp))
757 return 0;
758 }
759
760 return 1;
761 }
762
763 /*
764 * isp_pipeline_disable - Disable streaming on a pipeline
765 * @pipe: ISP pipeline
766 *
767 * Walk the entities chain starting at the pipeline output video node and stop
768 * all modules in the chain. Wait synchronously for the modules to be stopped if
769 * necessary.
770 *
771 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
772 * can't be stopped (in which case a software reset of the ISP is probably
773 * necessary).
774 */
775 static int isp_pipeline_disable(struct isp_pipeline *pipe)
776 {
777 struct isp_device *isp = pipe->output->isp;
778 struct media_entity *entity;
779 struct media_pad *pad;
780 struct v4l2_subdev *subdev;
781 int failure = 0;
782 int ret;
783
784 /*
785 * We need to stop all the modules after CCDC first or they'll
786 * never stop since they may not get a full frame from CCDC.
787 */
788 entity = &pipe->output->video.entity;
789 while (1) {
790 pad = &entity->pads[0];
791 if (!(pad->flags & MEDIA_PAD_FL_SINK))
792 break;
793
794 pad = media_entity_remote_pad(pad);
795 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
796 break;
797
798 entity = pad->entity;
799 subdev = media_entity_to_v4l2_subdev(entity);
800
801 if (subdev == &isp->isp_ccdc.subdev) {
802 v4l2_subdev_call(&isp->isp_aewb.subdev,
803 video, s_stream, 0);
804 v4l2_subdev_call(&isp->isp_af.subdev,
805 video, s_stream, 0);
806 v4l2_subdev_call(&isp->isp_hist.subdev,
807 video, s_stream, 0);
808 }
809
810 ret = v4l2_subdev_call(subdev, video, s_stream, 0);
811
812 if (subdev == &isp->isp_res.subdev)
813 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
814 else if (subdev == &isp->isp_prev.subdev)
815 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview);
816 else if (subdev == &isp->isp_ccdc.subdev)
817 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
818
819 /* Handle stop failures. An entity that fails to stop can
820 * usually just be restarted. Flag the stop failure nonetheless
821 * to trigger an ISP reset the next time the device is released,
822 * just in case.
823 *
824 * The preview engine is a special case. A failure to stop can
825 * mean a hardware crash. When that happens the preview engine
826 * won't respond to read/write operations on the L4 bus anymore,
827 * resulting in a bus fault and a kernel oops next time it gets
828 * accessed. Mark it as crashed to prevent pipelines including
829 * it from being started.
830 */
831 if (ret) {
832 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
833 isp->stop_failure = true;
834 if (subdev == &isp->isp_prev.subdev)
835 media_entity_enum_set(&isp->crashed,
836 &subdev->entity);
837 failure = -ETIMEDOUT;
838 }
839 }
840
841 return failure;
842 }
843
844 /*
845 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
846 * @pipe: ISP pipeline
847 * @state: Stream state (stopped, single shot or continuous)
848 *
849 * Set the pipeline to the given stream state. Pipelines can be started in
850 * single-shot or continuous mode.
851 *
852 * Return 0 if successful, or the return value of the failed video::s_stream
853 * operation otherwise. The pipeline state is not updated when the operation
854 * fails, except when stopping the pipeline.
855 */
856 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
857 enum isp_pipeline_stream_state state)
858 {
859 int ret;
860
861 if (state == ISP_PIPELINE_STREAM_STOPPED)
862 ret = isp_pipeline_disable(pipe);
863 else
864 ret = isp_pipeline_enable(pipe, state);
865
866 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
867 pipe->stream_state = state;
868
869 return ret;
870 }
871
872 /*
873 * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline
874 * @pipe: ISP pipeline
875 *
876 * Cancelling a stream mark all buffers on all video nodes in the pipeline as
877 * erroneous and makes sure no new buffer can be queued. This function is called
878 * when a fatal error that prevents any further operation on the pipeline
879 * occurs.
880 */
881 void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe)
882 {
883 if (pipe->input)
884 omap3isp_video_cancel_stream(pipe->input);
885 if (pipe->output)
886 omap3isp_video_cancel_stream(pipe->output);
887 }
888
889 /*
890 * isp_pipeline_resume - Resume streaming on a pipeline
891 * @pipe: ISP pipeline
892 *
893 * Resume video output and input and re-enable pipeline.
894 */
895 static void isp_pipeline_resume(struct isp_pipeline *pipe)
896 {
897 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
898
899 omap3isp_video_resume(pipe->output, !singleshot);
900 if (singleshot)
901 omap3isp_video_resume(pipe->input, 0);
902 isp_pipeline_enable(pipe, pipe->stream_state);
903 }
904
905 /*
906 * isp_pipeline_suspend - Suspend streaming on a pipeline
907 * @pipe: ISP pipeline
908 *
909 * Suspend pipeline.
910 */
911 static void isp_pipeline_suspend(struct isp_pipeline *pipe)
912 {
913 isp_pipeline_disable(pipe);
914 }
915
916 /*
917 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
918 * video node
919 * @me: ISP module's media entity
920 *
921 * Returns 1 if the entity has an enabled link to the output video node or 0
922 * otherwise. It's true only while pipeline can have no more than one output
923 * node.
924 */
925 static int isp_pipeline_is_last(struct media_entity *me)
926 {
927 struct isp_pipeline *pipe;
928 struct media_pad *pad;
929
930 if (!me->pipe)
931 return 0;
932 pipe = to_isp_pipeline(me);
933 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
934 return 0;
935 pad = media_entity_remote_pad(&pipe->output->pad);
936 return pad->entity == me;
937 }
938
939 /*
940 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
941 * @me: ISP module's media entity
942 *
943 * Suspend the whole pipeline if module's entity has an enabled link to the
944 * output video node. It works only while pipeline can have no more than one
945 * output node.
946 */
947 static void isp_suspend_module_pipeline(struct media_entity *me)
948 {
949 if (isp_pipeline_is_last(me))
950 isp_pipeline_suspend(to_isp_pipeline(me));
951 }
952
953 /*
954 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
955 * @me: ISP module's media entity
956 *
957 * Resume the whole pipeline if module's entity has an enabled link to the
958 * output video node. It works only while pipeline can have no more than one
959 * output node.
960 */
961 static void isp_resume_module_pipeline(struct media_entity *me)
962 {
963 if (isp_pipeline_is_last(me))
964 isp_pipeline_resume(to_isp_pipeline(me));
965 }
966
967 /*
968 * isp_suspend_modules - Suspend ISP submodules.
969 * @isp: OMAP3 ISP device
970 *
971 * Returns 0 if suspend left in idle state all the submodules properly,
972 * or returns 1 if a general Reset is required to suspend the submodules.
973 */
974 static int __maybe_unused isp_suspend_modules(struct isp_device *isp)
975 {
976 unsigned long timeout;
977
978 omap3isp_stat_suspend(&isp->isp_aewb);
979 omap3isp_stat_suspend(&isp->isp_af);
980 omap3isp_stat_suspend(&isp->isp_hist);
981 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
982 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
983 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
984 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
985 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
986
987 timeout = jiffies + ISP_STOP_TIMEOUT;
988 while (omap3isp_stat_busy(&isp->isp_af)
989 || omap3isp_stat_busy(&isp->isp_aewb)
990 || omap3isp_stat_busy(&isp->isp_hist)
991 || omap3isp_preview_busy(&isp->isp_prev)
992 || omap3isp_resizer_busy(&isp->isp_res)
993 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
994 if (time_after(jiffies, timeout)) {
995 dev_info(isp->dev, "can't stop modules.\n");
996 return 1;
997 }
998 msleep(1);
999 }
1000
1001 return 0;
1002 }
1003
1004 /*
1005 * isp_resume_modules - Resume ISP submodules.
1006 * @isp: OMAP3 ISP device
1007 */
1008 static void __maybe_unused isp_resume_modules(struct isp_device *isp)
1009 {
1010 omap3isp_stat_resume(&isp->isp_aewb);
1011 omap3isp_stat_resume(&isp->isp_af);
1012 omap3isp_stat_resume(&isp->isp_hist);
1013 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1014 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1015 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1016 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1017 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1018 }
1019
1020 /*
1021 * isp_reset - Reset ISP with a timeout wait for idle.
1022 * @isp: OMAP3 ISP device
1023 */
1024 static int isp_reset(struct isp_device *isp)
1025 {
1026 unsigned long timeout = 0;
1027
1028 isp_reg_writel(isp,
1029 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1030 | ISP_SYSCONFIG_SOFTRESET,
1031 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1032 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1033 ISP_SYSSTATUS) & 0x1)) {
1034 if (timeout++ > 10000) {
1035 dev_alert(isp->dev, "cannot reset ISP\n");
1036 return -ETIMEDOUT;
1037 }
1038 udelay(1);
1039 }
1040
1041 isp->stop_failure = false;
1042 media_entity_enum_zero(&isp->crashed);
1043 return 0;
1044 }
1045
1046 /*
1047 * isp_save_context - Saves the values of the ISP module registers.
1048 * @isp: OMAP3 ISP device
1049 * @reg_list: Structure containing pairs of register address and value to
1050 * modify on OMAP.
1051 */
1052 static void
1053 isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1054 {
1055 struct isp_reg *next = reg_list;
1056
1057 for (; next->reg != ISP_TOK_TERM; next++)
1058 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1059 }
1060
1061 /*
1062 * isp_restore_context - Restores the values of the ISP module registers.
1063 * @isp: OMAP3 ISP device
1064 * @reg_list: Structure containing pairs of register address and value to
1065 * modify on OMAP.
1066 */
1067 static void
1068 isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1069 {
1070 struct isp_reg *next = reg_list;
1071
1072 for (; next->reg != ISP_TOK_TERM; next++)
1073 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1074 }
1075
1076 /*
1077 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1078 * @isp: OMAP3 ISP device
1079 *
1080 * Routine for saving the context of each module in the ISP.
1081 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1082 */
1083 static void isp_save_ctx(struct isp_device *isp)
1084 {
1085 isp_save_context(isp, isp_reg_list);
1086 omap_iommu_save_ctx(isp->dev);
1087 }
1088
1089 /*
1090 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1091 * @isp: OMAP3 ISP device
1092 *
1093 * Routine for restoring the context of each module in the ISP.
1094 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1095 */
1096 static void isp_restore_ctx(struct isp_device *isp)
1097 {
1098 isp_restore_context(isp, isp_reg_list);
1099 omap_iommu_restore_ctx(isp->dev);
1100 omap3isp_ccdc_restore_context(isp);
1101 omap3isp_preview_restore_context(isp);
1102 }
1103
1104 /* -----------------------------------------------------------------------------
1105 * SBL resources management
1106 */
1107 #define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1108 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1109 OMAP3_ISP_SBL_PREVIEW_READ | \
1110 OMAP3_ISP_SBL_RESIZER_READ)
1111 #define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1112 OMAP3_ISP_SBL_CSI2A_WRITE | \
1113 OMAP3_ISP_SBL_CSI2C_WRITE | \
1114 OMAP3_ISP_SBL_CCDC_WRITE | \
1115 OMAP3_ISP_SBL_PREVIEW_WRITE)
1116
1117 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1118 {
1119 u32 sbl = 0;
1120
1121 isp->sbl_resources |= res;
1122
1123 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1124 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1125
1126 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1127 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1128
1129 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1130 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1131
1132 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1133 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1134
1135 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1136 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1137
1138 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1139 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1140
1141 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1142 }
1143
1144 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1145 {
1146 u32 sbl = 0;
1147
1148 isp->sbl_resources &= ~res;
1149
1150 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1151 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1152
1153 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1154 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1155
1156 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1157 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1158
1159 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1160 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1161
1162 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1163 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1164
1165 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1166 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1167
1168 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1169 }
1170
1171 /*
1172 * isp_module_sync_idle - Helper to sync module with its idle state
1173 * @me: ISP submodule's media entity
1174 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1175 * @stopping: flag which tells module wants to stop
1176 *
1177 * This function checks if ISP submodule needs to wait for next interrupt. If
1178 * yes, makes the caller to sleep while waiting for such event.
1179 */
1180 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1181 atomic_t *stopping)
1182 {
1183 struct isp_pipeline *pipe = to_isp_pipeline(me);
1184
1185 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1186 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1187 !isp_pipeline_ready(pipe)))
1188 return 0;
1189
1190 /*
1191 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1192 * scenario. We'll call it here to avoid race conditions.
1193 */
1194 atomic_set(stopping, 1);
1195 smp_mb();
1196
1197 /*
1198 * If module is the last one, it's writing to memory. In this case,
1199 * it's necessary to check if the module is already paused due to
1200 * DMA queue underrun or if it has to wait for next interrupt to be
1201 * idle.
1202 * If it isn't the last one, the function won't sleep but *stopping
1203 * will still be set to warn next submodule caller's interrupt the
1204 * module wants to be idle.
1205 */
1206 if (isp_pipeline_is_last(me)) {
1207 struct isp_video *video = pipe->output;
1208 unsigned long flags;
1209 spin_lock_irqsave(&video->irqlock, flags);
1210 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
1211 spin_unlock_irqrestore(&video->irqlock, flags);
1212 atomic_set(stopping, 0);
1213 smp_mb();
1214 return 0;
1215 }
1216 spin_unlock_irqrestore(&video->irqlock, flags);
1217 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1218 msecs_to_jiffies(1000))) {
1219 atomic_set(stopping, 0);
1220 smp_mb();
1221 return -ETIMEDOUT;
1222 }
1223 }
1224
1225 return 0;
1226 }
1227
1228 /*
1229 * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping
1230 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1231 * @stopping: flag which tells module wants to stop
1232 *
1233 * This function checks if ISP submodule was stopping. In case of yes, it
1234 * notices the caller by setting stopping to 0 and waking up the wait queue.
1235 * Returns 1 if it was stopping or 0 otherwise.
1236 */
1237 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1238 atomic_t *stopping)
1239 {
1240 if (atomic_cmpxchg(stopping, 1, 0)) {
1241 wake_up(wait);
1242 return 1;
1243 }
1244
1245 return 0;
1246 }
1247
1248 /* --------------------------------------------------------------------------
1249 * Clock management
1250 */
1251
1252 #define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1253 ISPCTRL_HIST_CLK_EN | \
1254 ISPCTRL_RSZ_CLK_EN | \
1255 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1256 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1257
1258 static void __isp_subclk_update(struct isp_device *isp)
1259 {
1260 u32 clk = 0;
1261
1262 /* AEWB and AF share the same clock. */
1263 if (isp->subclk_resources &
1264 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
1265 clk |= ISPCTRL_H3A_CLK_EN;
1266
1267 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1268 clk |= ISPCTRL_HIST_CLK_EN;
1269
1270 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1271 clk |= ISPCTRL_RSZ_CLK_EN;
1272
1273 /* NOTE: For CCDC & Preview submodules, we need to affect internal
1274 * RAM as well.
1275 */
1276 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1277 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1278
1279 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1280 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1281
1282 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1283 ISPCTRL_CLKS_MASK, clk);
1284 }
1285
1286 void omap3isp_subclk_enable(struct isp_device *isp,
1287 enum isp_subclk_resource res)
1288 {
1289 isp->subclk_resources |= res;
1290
1291 __isp_subclk_update(isp);
1292 }
1293
1294 void omap3isp_subclk_disable(struct isp_device *isp,
1295 enum isp_subclk_resource res)
1296 {
1297 isp->subclk_resources &= ~res;
1298
1299 __isp_subclk_update(isp);
1300 }
1301
1302 /*
1303 * isp_enable_clocks - Enable ISP clocks
1304 * @isp: OMAP3 ISP device
1305 *
1306 * Return 0 if successful, or clk_prepare_enable return value if any of them
1307 * fails.
1308 */
1309 static int isp_enable_clocks(struct isp_device *isp)
1310 {
1311 int r;
1312 unsigned long rate;
1313
1314 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
1315 if (r) {
1316 dev_err(isp->dev, "failed to enable cam_ick clock\n");
1317 goto out_clk_enable_ick;
1318 }
1319 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
1320 if (r) {
1321 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
1322 goto out_clk_enable_mclk;
1323 }
1324 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
1325 if (r) {
1326 dev_err(isp->dev, "failed to enable cam_mclk clock\n");
1327 goto out_clk_enable_mclk;
1328 }
1329 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1330 if (rate != CM_CAM_MCLK_HZ)
1331 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1332 " expected : %d\n"
1333 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
1334 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
1335 if (r) {
1336 dev_err(isp->dev, "failed to enable csi2_fck clock\n");
1337 goto out_clk_enable_csi2_fclk;
1338 }
1339 return 0;
1340
1341 out_clk_enable_csi2_fclk:
1342 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1343 out_clk_enable_mclk:
1344 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1345 out_clk_enable_ick:
1346 return r;
1347 }
1348
1349 /*
1350 * isp_disable_clocks - Disable ISP clocks
1351 * @isp: OMAP3 ISP device
1352 */
1353 static void isp_disable_clocks(struct isp_device *isp)
1354 {
1355 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1356 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1357 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
1358 }
1359
1360 static const char *isp_clocks[] = {
1361 "cam_ick",
1362 "cam_mclk",
1363 "csi2_96m_fck",
1364 "l3_ick",
1365 };
1366
1367 static int isp_get_clocks(struct isp_device *isp)
1368 {
1369 struct clk *clk;
1370 unsigned int i;
1371
1372 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1373 clk = devm_clk_get(isp->dev, isp_clocks[i]);
1374 if (IS_ERR(clk)) {
1375 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
1376 return PTR_ERR(clk);
1377 }
1378
1379 isp->clock[i] = clk;
1380 }
1381
1382 return 0;
1383 }
1384
1385 /*
1386 * omap3isp_get - Acquire the ISP resource.
1387 *
1388 * Initializes the clocks for the first acquire.
1389 *
1390 * Increment the reference count on the ISP. If the first reference is taken,
1391 * enable clocks and power-up all submodules.
1392 *
1393 * Return a pointer to the ISP device structure, or NULL if an error occurred.
1394 */
1395 static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
1396 {
1397 struct isp_device *__isp = isp;
1398
1399 if (isp == NULL)
1400 return NULL;
1401
1402 mutex_lock(&isp->isp_mutex);
1403 if (isp->ref_count > 0)
1404 goto out;
1405
1406 if (isp_enable_clocks(isp) < 0) {
1407 __isp = NULL;
1408 goto out;
1409 }
1410
1411 /* We don't want to restore context before saving it! */
1412 if (isp->has_context)
1413 isp_restore_ctx(isp);
1414
1415 if (irq)
1416 isp_enable_interrupts(isp);
1417
1418 out:
1419 if (__isp != NULL)
1420 isp->ref_count++;
1421 mutex_unlock(&isp->isp_mutex);
1422
1423 return __isp;
1424 }
1425
1426 struct isp_device *omap3isp_get(struct isp_device *isp)
1427 {
1428 return __omap3isp_get(isp, true);
1429 }
1430
1431 /*
1432 * omap3isp_put - Release the ISP
1433 *
1434 * Decrement the reference count on the ISP. If the last reference is released,
1435 * power-down all submodules, disable clocks and free temporary buffers.
1436 */
1437 static void __omap3isp_put(struct isp_device *isp, bool save_ctx)
1438 {
1439 if (isp == NULL)
1440 return;
1441
1442 mutex_lock(&isp->isp_mutex);
1443 BUG_ON(isp->ref_count == 0);
1444 if (--isp->ref_count == 0) {
1445 isp_disable_interrupts(isp);
1446 if (save_ctx) {
1447 isp_save_ctx(isp);
1448 isp->has_context = 1;
1449 }
1450 /* Reset the ISP if an entity has failed to stop. This is the
1451 * only way to recover from such conditions.
1452 */
1453 if (!media_entity_enum_empty(&isp->crashed) ||
1454 isp->stop_failure)
1455 isp_reset(isp);
1456 isp_disable_clocks(isp);
1457 }
1458 mutex_unlock(&isp->isp_mutex);
1459 }
1460
1461 void omap3isp_put(struct isp_device *isp)
1462 {
1463 __omap3isp_put(isp, true);
1464 }
1465
1466 /* --------------------------------------------------------------------------
1467 * Platform device driver
1468 */
1469
1470 /*
1471 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1472 * @isp: OMAP3 ISP device
1473 */
1474 #define ISP_PRINT_REGISTER(isp, name)\
1475 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1476 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1477 #define SBL_PRINT_REGISTER(isp, name)\
1478 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1479 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1480
1481 void omap3isp_print_status(struct isp_device *isp)
1482 {
1483 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1484
1485 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1486 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1487 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1488 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1489 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1490 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1491 ISP_PRINT_REGISTER(isp, CTRL);
1492 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1493 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1494 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1495 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1496 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1497 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1498 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1499 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1500
1501 SBL_PRINT_REGISTER(isp, PCR);
1502 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1503
1504 dev_dbg(isp->dev, "--------------------------------------------\n");
1505 }
1506
1507 #ifdef CONFIG_PM
1508
1509 /*
1510 * Power management support.
1511 *
1512 * As the ISP can't properly handle an input video stream interruption on a non
1513 * frame boundary, the ISP pipelines need to be stopped before sensors get
1514 * suspended. However, as suspending the sensors can require a running clock,
1515 * which can be provided by the ISP, the ISP can't be completely suspended
1516 * before the sensor.
1517 *
1518 * To solve this problem power management support is split into prepare/complete
1519 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1520 * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
1521 * resume(), and the the pipelines are restarted in complete().
1522 *
1523 * TODO: PM dependencies between the ISP and sensors are not modelled explicitly
1524 * yet.
1525 */
1526 static int isp_pm_prepare(struct device *dev)
1527 {
1528 struct isp_device *isp = dev_get_drvdata(dev);
1529 int reset;
1530
1531 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1532
1533 if (isp->ref_count == 0)
1534 return 0;
1535
1536 reset = isp_suspend_modules(isp);
1537 isp_disable_interrupts(isp);
1538 isp_save_ctx(isp);
1539 if (reset)
1540 isp_reset(isp);
1541
1542 return 0;
1543 }
1544
1545 static int isp_pm_suspend(struct device *dev)
1546 {
1547 struct isp_device *isp = dev_get_drvdata(dev);
1548
1549 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1550
1551 if (isp->ref_count)
1552 isp_disable_clocks(isp);
1553
1554 return 0;
1555 }
1556
1557 static int isp_pm_resume(struct device *dev)
1558 {
1559 struct isp_device *isp = dev_get_drvdata(dev);
1560
1561 if (isp->ref_count == 0)
1562 return 0;
1563
1564 return isp_enable_clocks(isp);
1565 }
1566
1567 static void isp_pm_complete(struct device *dev)
1568 {
1569 struct isp_device *isp = dev_get_drvdata(dev);
1570
1571 if (isp->ref_count == 0)
1572 return;
1573
1574 isp_restore_ctx(isp);
1575 isp_enable_interrupts(isp);
1576 isp_resume_modules(isp);
1577 }
1578
1579 #else
1580
1581 #define isp_pm_prepare NULL
1582 #define isp_pm_suspend NULL
1583 #define isp_pm_resume NULL
1584 #define isp_pm_complete NULL
1585
1586 #endif /* CONFIG_PM */
1587
1588 static void isp_unregister_entities(struct isp_device *isp)
1589 {
1590 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1591 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1592 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1593 omap3isp_preview_unregister_entities(&isp->isp_prev);
1594 omap3isp_resizer_unregister_entities(&isp->isp_res);
1595 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1596 omap3isp_stat_unregister_entities(&isp->isp_af);
1597 omap3isp_stat_unregister_entities(&isp->isp_hist);
1598
1599 v4l2_device_unregister(&isp->v4l2_dev);
1600 media_device_unregister(&isp->media_dev);
1601 media_device_cleanup(&isp->media_dev);
1602 }
1603
1604 static int isp_link_entity(
1605 struct isp_device *isp, struct media_entity *entity,
1606 enum isp_interface_type interface)
1607 {
1608 struct media_entity *input;
1609 unsigned int flags;
1610 unsigned int pad;
1611 unsigned int i;
1612
1613 /* Connect the sensor to the correct interface module.
1614 * Parallel sensors are connected directly to the CCDC, while
1615 * serial sensors are connected to the CSI2a, CCP2b or CSI2c
1616 * receiver through CSIPHY1 or CSIPHY2.
1617 */
1618 switch (interface) {
1619 case ISP_INTERFACE_PARALLEL:
1620 input = &isp->isp_ccdc.subdev.entity;
1621 pad = CCDC_PAD_SINK;
1622 flags = 0;
1623 break;
1624
1625 case ISP_INTERFACE_CSI2A_PHY2:
1626 input = &isp->isp_csi2a.subdev.entity;
1627 pad = CSI2_PAD_SINK;
1628 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1629 break;
1630
1631 case ISP_INTERFACE_CCP2B_PHY1:
1632 case ISP_INTERFACE_CCP2B_PHY2:
1633 input = &isp->isp_ccp2.subdev.entity;
1634 pad = CCP2_PAD_SINK;
1635 flags = 0;
1636 break;
1637
1638 case ISP_INTERFACE_CSI2C_PHY1:
1639 input = &isp->isp_csi2c.subdev.entity;
1640 pad = CSI2_PAD_SINK;
1641 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1642 break;
1643
1644 default:
1645 dev_err(isp->dev, "%s: invalid interface type %u\n", __func__,
1646 interface);
1647 return -EINVAL;
1648 }
1649
1650 /*
1651 * Not all interfaces are available on all revisions of the
1652 * ISP. The sub-devices of those interfaces aren't initialised
1653 * in such a case. Check this by ensuring the num_pads is
1654 * non-zero.
1655 */
1656 if (!input->num_pads) {
1657 dev_err(isp->dev, "%s: invalid input %u\n", entity->name,
1658 interface);
1659 return -EINVAL;
1660 }
1661
1662 for (i = 0; i < entity->num_pads; i++) {
1663 if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1664 break;
1665 }
1666 if (i == entity->num_pads) {
1667 dev_err(isp->dev, "%s: no source pad in external entity %s\n",
1668 __func__, entity->name);
1669 return -EINVAL;
1670 }
1671
1672 return media_create_pad_link(entity, i, input, pad, flags);
1673 }
1674
1675 static int isp_register_entities(struct isp_device *isp)
1676 {
1677 int ret;
1678
1679 isp->media_dev.dev = isp->dev;
1680 strlcpy(isp->media_dev.model, "TI OMAP3 ISP",
1681 sizeof(isp->media_dev.model));
1682 isp->media_dev.hw_revision = isp->revision;
1683 isp->media_dev.ops = &isp_media_ops;
1684 media_device_init(&isp->media_dev);
1685
1686 isp->v4l2_dev.mdev = &isp->media_dev;
1687 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1688 if (ret < 0) {
1689 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
1690 __func__, ret);
1691 goto done;
1692 }
1693
1694 /* Register internal entities */
1695 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1696 if (ret < 0)
1697 goto done;
1698
1699 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1700 if (ret < 0)
1701 goto done;
1702
1703 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1704 if (ret < 0)
1705 goto done;
1706
1707 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1708 &isp->v4l2_dev);
1709 if (ret < 0)
1710 goto done;
1711
1712 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1713 if (ret < 0)
1714 goto done;
1715
1716 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1717 if (ret < 0)
1718 goto done;
1719
1720 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1721 if (ret < 0)
1722 goto done;
1723
1724 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1725 if (ret < 0)
1726 goto done;
1727
1728 done:
1729 if (ret < 0)
1730 isp_unregister_entities(isp);
1731
1732 return ret;
1733 }
1734
1735 /*
1736 * isp_create_links() - Create links for internal and external ISP entities
1737 * @isp : Pointer to ISP device
1738 *
1739 * This function creates all links between ISP internal and external entities.
1740 *
1741 * Return: A negative error code on failure or zero on success. Possible error
1742 * codes are those returned by media_create_pad_link().
1743 */
1744 static int isp_create_links(struct isp_device *isp)
1745 {
1746 int ret;
1747
1748 /* Create links between entities and video nodes. */
1749 ret = media_create_pad_link(
1750 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1751 &isp->isp_csi2a.video_out.video.entity, 0, 0);
1752 if (ret < 0)
1753 return ret;
1754
1755 ret = media_create_pad_link(
1756 &isp->isp_ccp2.video_in.video.entity, 0,
1757 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0);
1758 if (ret < 0)
1759 return ret;
1760
1761 ret = media_create_pad_link(
1762 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1763 &isp->isp_ccdc.video_out.video.entity, 0, 0);
1764 if (ret < 0)
1765 return ret;
1766
1767 ret = media_create_pad_link(
1768 &isp->isp_prev.video_in.video.entity, 0,
1769 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1770 if (ret < 0)
1771 return ret;
1772
1773 ret = media_create_pad_link(
1774 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1775 &isp->isp_prev.video_out.video.entity, 0, 0);
1776 if (ret < 0)
1777 return ret;
1778
1779 ret = media_create_pad_link(
1780 &isp->isp_res.video_in.video.entity, 0,
1781 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1782 if (ret < 0)
1783 return ret;
1784
1785 ret = media_create_pad_link(
1786 &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE,
1787 &isp->isp_res.video_out.video.entity, 0, 0);
1788
1789 if (ret < 0)
1790 return ret;
1791
1792 /* Create links between entities. */
1793 ret = media_create_pad_link(
1794 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1795 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1796 if (ret < 0)
1797 return ret;
1798
1799 ret = media_create_pad_link(
1800 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1801 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1802 if (ret < 0)
1803 return ret;
1804
1805 ret = media_create_pad_link(
1806 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1807 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1808 if (ret < 0)
1809 return ret;
1810
1811 ret = media_create_pad_link(
1812 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1813 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1814 if (ret < 0)
1815 return ret;
1816
1817 ret = media_create_pad_link(
1818 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1819 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1820 if (ret < 0)
1821 return ret;
1822
1823 ret = media_create_pad_link(
1824 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1825 &isp->isp_aewb.subdev.entity, 0,
1826 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1827 if (ret < 0)
1828 return ret;
1829
1830 ret = media_create_pad_link(
1831 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1832 &isp->isp_af.subdev.entity, 0,
1833 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1834 if (ret < 0)
1835 return ret;
1836
1837 ret = media_create_pad_link(
1838 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1839 &isp->isp_hist.subdev.entity, 0,
1840 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1841 if (ret < 0)
1842 return ret;
1843
1844 return 0;
1845 }
1846
1847 static void isp_cleanup_modules(struct isp_device *isp)
1848 {
1849 omap3isp_h3a_aewb_cleanup(isp);
1850 omap3isp_h3a_af_cleanup(isp);
1851 omap3isp_hist_cleanup(isp);
1852 omap3isp_resizer_cleanup(isp);
1853 omap3isp_preview_cleanup(isp);
1854 omap3isp_ccdc_cleanup(isp);
1855 omap3isp_ccp2_cleanup(isp);
1856 omap3isp_csi2_cleanup(isp);
1857 omap3isp_csiphy_cleanup(isp);
1858 }
1859
1860 static int isp_initialize_modules(struct isp_device *isp)
1861 {
1862 int ret;
1863
1864 ret = omap3isp_csiphy_init(isp);
1865 if (ret < 0) {
1866 dev_err(isp->dev, "CSI PHY initialization failed\n");
1867 return ret;
1868 }
1869
1870 ret = omap3isp_csi2_init(isp);
1871 if (ret < 0) {
1872 dev_err(isp->dev, "CSI2 initialization failed\n");
1873 goto error_csi2;
1874 }
1875
1876 ret = omap3isp_ccp2_init(isp);
1877 if (ret < 0) {
1878 if (ret != -EPROBE_DEFER)
1879 dev_err(isp->dev, "CCP2 initialization failed\n");
1880 goto error_ccp2;
1881 }
1882
1883 ret = omap3isp_ccdc_init(isp);
1884 if (ret < 0) {
1885 dev_err(isp->dev, "CCDC initialization failed\n");
1886 goto error_ccdc;
1887 }
1888
1889 ret = omap3isp_preview_init(isp);
1890 if (ret < 0) {
1891 dev_err(isp->dev, "Preview initialization failed\n");
1892 goto error_preview;
1893 }
1894
1895 ret = omap3isp_resizer_init(isp);
1896 if (ret < 0) {
1897 dev_err(isp->dev, "Resizer initialization failed\n");
1898 goto error_resizer;
1899 }
1900
1901 ret = omap3isp_hist_init(isp);
1902 if (ret < 0) {
1903 dev_err(isp->dev, "Histogram initialization failed\n");
1904 goto error_hist;
1905 }
1906
1907 ret = omap3isp_h3a_aewb_init(isp);
1908 if (ret < 0) {
1909 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1910 goto error_h3a_aewb;
1911 }
1912
1913 ret = omap3isp_h3a_af_init(isp);
1914 if (ret < 0) {
1915 dev_err(isp->dev, "H3A AF initialization failed\n");
1916 goto error_h3a_af;
1917 }
1918
1919 return 0;
1920
1921 error_h3a_af:
1922 omap3isp_h3a_aewb_cleanup(isp);
1923 error_h3a_aewb:
1924 omap3isp_hist_cleanup(isp);
1925 error_hist:
1926 omap3isp_resizer_cleanup(isp);
1927 error_resizer:
1928 omap3isp_preview_cleanup(isp);
1929 error_preview:
1930 omap3isp_ccdc_cleanup(isp);
1931 error_ccdc:
1932 omap3isp_ccp2_cleanup(isp);
1933 error_ccp2:
1934 omap3isp_csi2_cleanup(isp);
1935 error_csi2:
1936 omap3isp_csiphy_cleanup(isp);
1937
1938 return ret;
1939 }
1940
1941 static void isp_detach_iommu(struct isp_device *isp)
1942 {
1943 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1944 arm_iommu_detach_device(isp->dev);
1945 arm_iommu_release_mapping(isp->mapping);
1946 isp->mapping = NULL;
1947 #endif
1948 }
1949
1950 static int isp_attach_iommu(struct isp_device *isp)
1951 {
1952 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1953 struct dma_iommu_mapping *mapping;
1954 int ret;
1955
1956 /*
1957 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
1958 * VAs. This will allocate a corresponding IOMMU domain.
1959 */
1960 mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
1961 if (IS_ERR(mapping)) {
1962 dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
1963 return PTR_ERR(mapping);
1964 }
1965
1966 isp->mapping = mapping;
1967
1968 /* Attach the ARM VA mapping to the device. */
1969 ret = arm_iommu_attach_device(isp->dev, mapping);
1970 if (ret < 0) {
1971 dev_err(isp->dev, "failed to attach device to VA mapping\n");
1972 goto error;
1973 }
1974
1975 return 0;
1976
1977 error:
1978 arm_iommu_release_mapping(isp->mapping);
1979 isp->mapping = NULL;
1980 return ret;
1981 #else
1982 return -ENODEV;
1983 #endif
1984 }
1985
1986 /*
1987 * isp_remove - Remove ISP platform device
1988 * @pdev: Pointer to ISP platform device
1989 *
1990 * Always returns 0.
1991 */
1992 static int isp_remove(struct platform_device *pdev)
1993 {
1994 struct isp_device *isp = platform_get_drvdata(pdev);
1995
1996 v4l2_async_notifier_unregister(&isp->notifier);
1997 isp_unregister_entities(isp);
1998 isp_cleanup_modules(isp);
1999 isp_xclk_cleanup(isp);
2000
2001 __omap3isp_get(isp, false);
2002 isp_detach_iommu(isp);
2003 __omap3isp_put(isp, false);
2004
2005 media_entity_enum_cleanup(&isp->crashed);
2006 v4l2_async_notifier_cleanup(&isp->notifier);
2007
2008 return 0;
2009 }
2010
2011 enum isp_of_phy {
2012 ISP_OF_PHY_PARALLEL = 0,
2013 ISP_OF_PHY_CSIPHY1,
2014 ISP_OF_PHY_CSIPHY2,
2015 };
2016
2017 static int isp_fwnode_parse(struct device *dev,
2018 struct v4l2_fwnode_endpoint *vep,
2019 struct v4l2_async_subdev *asd)
2020 {
2021 struct isp_async_subdev *isd =
2022 container_of(asd, struct isp_async_subdev, asd);
2023 struct isp_bus_cfg *buscfg = &isd->bus;
2024 bool csi1 = false;
2025 unsigned int i;
2026
2027 dev_dbg(dev, "parsing endpoint %pOF, interface %u\n",
2028 to_of_node(vep->base.local_fwnode), vep->base.port);
2029
2030 switch (vep->base.port) {
2031 case ISP_OF_PHY_PARALLEL:
2032 buscfg->interface = ISP_INTERFACE_PARALLEL;
2033 buscfg->bus.parallel.data_lane_shift =
2034 vep->bus.parallel.data_shift;
2035 buscfg->bus.parallel.clk_pol =
2036 !!(vep->bus.parallel.flags
2037 & V4L2_MBUS_PCLK_SAMPLE_FALLING);
2038 buscfg->bus.parallel.hs_pol =
2039 !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
2040 buscfg->bus.parallel.vs_pol =
2041 !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
2042 buscfg->bus.parallel.fld_pol =
2043 !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW);
2044 buscfg->bus.parallel.data_pol =
2045 !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW);
2046 buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656;
2047 break;
2048
2049 case ISP_OF_PHY_CSIPHY1:
2050 case ISP_OF_PHY_CSIPHY2:
2051 switch (vep->bus_type) {
2052 case V4L2_MBUS_CCP2:
2053 case V4L2_MBUS_CSI1:
2054 dev_dbg(dev, "CSI-1/CCP-2 configuration\n");
2055 csi1 = true;
2056 break;
2057 case V4L2_MBUS_CSI2:
2058 dev_dbg(dev, "CSI-2 configuration\n");
2059 csi1 = false;
2060 break;
2061 default:
2062 dev_err(dev, "unsupported bus type %u\n",
2063 vep->bus_type);
2064 return -EINVAL;
2065 }
2066
2067 switch (vep->base.port) {
2068 case ISP_OF_PHY_CSIPHY1:
2069 if (csi1)
2070 buscfg->interface = ISP_INTERFACE_CCP2B_PHY1;
2071 else
2072 buscfg->interface = ISP_INTERFACE_CSI2C_PHY1;
2073 break;
2074 case ISP_OF_PHY_CSIPHY2:
2075 if (csi1)
2076 buscfg->interface = ISP_INTERFACE_CCP2B_PHY2;
2077 else
2078 buscfg->interface = ISP_INTERFACE_CSI2A_PHY2;
2079 break;
2080 }
2081 if (csi1) {
2082 buscfg->bus.ccp2.lanecfg.clk.pos =
2083 vep->bus.mipi_csi1.clock_lane;
2084 buscfg->bus.ccp2.lanecfg.clk.pol =
2085 vep->bus.mipi_csi1.lane_polarity[0];
2086 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2087 buscfg->bus.ccp2.lanecfg.clk.pol,
2088 buscfg->bus.ccp2.lanecfg.clk.pos);
2089
2090 buscfg->bus.ccp2.lanecfg.data[0].pos =
2091 vep->bus.mipi_csi1.data_lane;
2092 buscfg->bus.ccp2.lanecfg.data[0].pol =
2093 vep->bus.mipi_csi1.lane_polarity[1];
2094
2095 dev_dbg(dev, "data lane polarity %u, pos %u\n",
2096 buscfg->bus.ccp2.lanecfg.data[0].pol,
2097 buscfg->bus.ccp2.lanecfg.data[0].pos);
2098
2099 buscfg->bus.ccp2.strobe_clk_pol =
2100 vep->bus.mipi_csi1.clock_inv;
2101 buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe;
2102 buscfg->bus.ccp2.ccp2_mode =
2103 vep->bus_type == V4L2_MBUS_CCP2;
2104 buscfg->bus.ccp2.vp_clk_pol = 1;
2105
2106 buscfg->bus.ccp2.crc = 1;
2107 } else {
2108 buscfg->bus.csi2.lanecfg.clk.pos =
2109 vep->bus.mipi_csi2.clock_lane;
2110 buscfg->bus.csi2.lanecfg.clk.pol =
2111 vep->bus.mipi_csi2.lane_polarities[0];
2112 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2113 buscfg->bus.csi2.lanecfg.clk.pol,
2114 buscfg->bus.csi2.lanecfg.clk.pos);
2115
2116 buscfg->bus.csi2.num_data_lanes =
2117 vep->bus.mipi_csi2.num_data_lanes;
2118
2119 for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) {
2120 buscfg->bus.csi2.lanecfg.data[i].pos =
2121 vep->bus.mipi_csi2.data_lanes[i];
2122 buscfg->bus.csi2.lanecfg.data[i].pol =
2123 vep->bus.mipi_csi2.lane_polarities[i + 1];
2124 dev_dbg(dev,
2125 "data lane %u polarity %u, pos %u\n", i,
2126 buscfg->bus.csi2.lanecfg.data[i].pol,
2127 buscfg->bus.csi2.lanecfg.data[i].pos);
2128 }
2129 /*
2130 * FIXME: now we assume the CRC is always there.
2131 * Implement a way to obtain this information from the
2132 * sensor. Frame descriptors, perhaps?
2133 */
2134 buscfg->bus.csi2.crc = 1;
2135 }
2136 break;
2137
2138 default:
2139 dev_warn(dev, "%pOF: invalid interface %u\n",
2140 to_of_node(vep->base.local_fwnode), vep->base.port);
2141 return -EINVAL;
2142 }
2143
2144 return 0;
2145 }
2146
2147 static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
2148 {
2149 struct isp_device *isp = container_of(async, struct isp_device,
2150 notifier);
2151 struct v4l2_device *v4l2_dev = &isp->v4l2_dev;
2152 struct v4l2_subdev *sd;
2153 int ret;
2154
2155 ret = media_entity_enum_init(&isp->crashed, &isp->media_dev);
2156 if (ret)
2157 return ret;
2158
2159 list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
2160 if (sd->notifier != &isp->notifier)
2161 continue;
2162
2163 ret = isp_link_entity(isp, &sd->entity,
2164 v4l2_subdev_to_bus_cfg(sd)->interface);
2165 if (ret < 0)
2166 return ret;
2167 }
2168
2169 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
2170 if (ret < 0)
2171 return ret;
2172
2173 return media_device_register(&isp->media_dev);
2174 }
2175
2176 static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
2177 .complete = isp_subdev_notifier_complete,
2178 };
2179
2180 /*
2181 * isp_probe - Probe ISP platform device
2182 * @pdev: Pointer to ISP platform device
2183 *
2184 * Returns 0 if successful,
2185 * -ENOMEM if no memory available,
2186 * -ENODEV if no platform device resources found
2187 * or no space for remapping registers,
2188 * -EINVAL if couldn't install ISR,
2189 * or clk_get return error value.
2190 */
2191 static int isp_probe(struct platform_device *pdev)
2192 {
2193 struct isp_device *isp;
2194 struct resource *mem;
2195 int ret;
2196 int i, m;
2197
2198 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
2199 if (!isp) {
2200 dev_err(&pdev->dev, "could not allocate memory\n");
2201 return -ENOMEM;
2202 }
2203
2204 ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node),
2205 "ti,phy-type", &isp->phy_type);
2206 if (ret)
2207 return ret;
2208
2209 isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2210 "syscon");
2211 if (IS_ERR(isp->syscon))
2212 return PTR_ERR(isp->syscon);
2213
2214 ret = of_property_read_u32_index(pdev->dev.of_node,
2215 "syscon", 1, &isp->syscon_offset);
2216 if (ret)
2217 return ret;
2218
2219 isp->autoidle = autoidle;
2220
2221 mutex_init(&isp->isp_mutex);
2222 spin_lock_init(&isp->stat_lock);
2223
2224 ret = v4l2_async_notifier_parse_fwnode_endpoints(
2225 &pdev->dev, &isp->notifier, sizeof(struct isp_async_subdev),
2226 isp_fwnode_parse);
2227 if (ret < 0)
2228 goto error;
2229
2230 isp->dev = &pdev->dev;
2231 isp->ref_count = 0;
2232
2233 ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32));
2234 if (ret)
2235 goto error;
2236
2237 platform_set_drvdata(pdev, isp);
2238
2239 /* Regulators */
2240 isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1");
2241 isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2");
2242
2243 /* Clocks
2244 *
2245 * The ISP clock tree is revision-dependent. We thus need to enable ICLK
2246 * manually to read the revision before calling __omap3isp_get().
2247 *
2248 * Start by mapping the ISP MMIO area, which is in two pieces.
2249 * The ISP IOMMU is in between. Map both now, and fill in the
2250 * ISP revision specific portions a little later in the
2251 * function.
2252 */
2253 for (i = 0; i < 2; i++) {
2254 unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
2255
2256 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
2257 isp->mmio_base[map_idx] =
2258 devm_ioremap_resource(isp->dev, mem);
2259 if (IS_ERR(isp->mmio_base[map_idx]))
2260 return PTR_ERR(isp->mmio_base[map_idx]);
2261 }
2262
2263 ret = isp_get_clocks(isp);
2264 if (ret < 0)
2265 goto error;
2266
2267 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
2268 if (ret < 0)
2269 goto error;
2270
2271 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2272 dev_info(isp->dev, "Revision %d.%d found\n",
2273 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2274
2275 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
2276
2277 if (__omap3isp_get(isp, false) == NULL) {
2278 ret = -ENODEV;
2279 goto error;
2280 }
2281
2282 ret = isp_reset(isp);
2283 if (ret < 0)
2284 goto error_isp;
2285
2286 ret = isp_xclk_init(isp);
2287 if (ret < 0)
2288 goto error_isp;
2289
2290 /* Memory resources */
2291 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2292 if (isp->revision == isp_res_maps[m].isp_rev)
2293 break;
2294
2295 if (m == ARRAY_SIZE(isp_res_maps)) {
2296 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2297 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2298 ret = -ENODEV;
2299 goto error_isp;
2300 }
2301
2302 for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
2303 isp->mmio_base[i] =
2304 isp->mmio_base[0] + isp_res_maps[m].offset[i];
2305
2306 for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
2307 isp->mmio_base[i] =
2308 isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
2309 + isp_res_maps[m].offset[i];
2310
2311 isp->mmio_hist_base_phys =
2312 mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
2313
2314 /* IOMMU */
2315 ret = isp_attach_iommu(isp);
2316 if (ret < 0) {
2317 dev_err(&pdev->dev, "unable to attach to IOMMU\n");
2318 goto error_isp;
2319 }
2320
2321 /* Interrupt */
2322 ret = platform_get_irq(pdev, 0);
2323 if (ret <= 0) {
2324 dev_err(isp->dev, "No IRQ resource\n");
2325 ret = -ENODEV;
2326 goto error_iommu;
2327 }
2328 isp->irq_num = ret;
2329
2330 if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED,
2331 "OMAP3 ISP", isp)) {
2332 dev_err(isp->dev, "Unable to request IRQ\n");
2333 ret = -EINVAL;
2334 goto error_iommu;
2335 }
2336
2337 /* Entities */
2338 ret = isp_initialize_modules(isp);
2339 if (ret < 0)
2340 goto error_iommu;
2341
2342 ret = isp_register_entities(isp);
2343 if (ret < 0)
2344 goto error_modules;
2345
2346 ret = isp_create_links(isp);
2347 if (ret < 0)
2348 goto error_register_entities;
2349
2350 isp->notifier.ops = &isp_subdev_notifier_ops;
2351
2352 ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
2353 if (ret)
2354 goto error_register_entities;
2355
2356 isp_core_init(isp, 1);
2357 omap3isp_put(isp);
2358
2359 return 0;
2360
2361 error_register_entities:
2362 isp_unregister_entities(isp);
2363 error_modules:
2364 isp_cleanup_modules(isp);
2365 error_iommu:
2366 isp_detach_iommu(isp);
2367 error_isp:
2368 isp_xclk_cleanup(isp);
2369 __omap3isp_put(isp, false);
2370 error:
2371 v4l2_async_notifier_cleanup(&isp->notifier);
2372 mutex_destroy(&isp->isp_mutex);
2373
2374 return ret;
2375 }
2376
2377 static const struct dev_pm_ops omap3isp_pm_ops = {
2378 .prepare = isp_pm_prepare,
2379 .suspend = isp_pm_suspend,
2380 .resume = isp_pm_resume,
2381 .complete = isp_pm_complete,
2382 };
2383
2384 static struct platform_device_id omap3isp_id_table[] = {
2385 { "omap3isp", 0 },
2386 { },
2387 };
2388 MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2389
2390 static const struct of_device_id omap3isp_of_table[] = {
2391 { .compatible = "ti,omap3-isp" },
2392 { },
2393 };
2394 MODULE_DEVICE_TABLE(of, omap3isp_of_table);
2395
2396 static struct platform_driver omap3isp_driver = {
2397 .probe = isp_probe,
2398 .remove = isp_remove,
2399 .id_table = omap3isp_id_table,
2400 .driver = {
2401 .name = "omap3isp",
2402 .pm = &omap3isp_pm_ops,
2403 .of_match_table = omap3isp_of_table,
2404 },
2405 };
2406
2407 module_platform_driver(omap3isp_driver);
2408
2409 MODULE_AUTHOR("Nokia Corporation");
2410 MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2411 MODULE_LICENSE("GPL");
2412 MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);
Linux with added FPC-III support