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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / media / platform / rcar-vin / rcar-csi2.c
blobdc5ae8025832ab6e629557b1fa860731a5dfd796
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Renesas R-Car MIPI CSI-2 Receiver
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/sys_soc.h>
18
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-mc.h>
23 #include <media/v4l2-subdev.h>
24
25 struct rcar_csi2;
26
27 /* Register offsets and bits */
28
29 /* Control Timing Select */
30 #define TREF_REG 0x00
31 #define TREF_TREF BIT(0)
32
33 /* Software Reset */
34 #define SRST_REG 0x04
35 #define SRST_SRST BIT(0)
36
37 /* PHY Operation Control */
38 #define PHYCNT_REG 0x08
39 #define PHYCNT_SHUTDOWNZ BIT(17)
40 #define PHYCNT_RSTZ BIT(16)
41 #define PHYCNT_ENABLECLK BIT(4)
42 #define PHYCNT_ENABLE_3 BIT(3)
43 #define PHYCNT_ENABLE_2 BIT(2)
44 #define PHYCNT_ENABLE_1 BIT(1)
45 #define PHYCNT_ENABLE_0 BIT(0)
46
47 /* Checksum Control */
48 #define CHKSUM_REG 0x0c
49 #define CHKSUM_ECC_EN BIT(1)
50 #define CHKSUM_CRC_EN BIT(0)
51
52 /*
53 * Channel Data Type Select
54 * VCDT[0-15]: Channel 1 VCDT[16-31]: Channel 2
55 * VCDT2[0-15]: Channel 3 VCDT2[16-31]: Channel 4
56 */
57 #define VCDT_REG 0x10
58 #define VCDT2_REG 0x14
59 #define VCDT_VCDTN_EN BIT(15)
60 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
61 #define VCDT_SEL_DTN_ON BIT(6)
62 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
63
64 /* Frame Data Type Select */
65 #define FRDT_REG 0x18
66
67 /* Field Detection Control */
68 #define FLD_REG 0x1c
69 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
70 #define FLD_FLD_EN4 BIT(3)
71 #define FLD_FLD_EN3 BIT(2)
72 #define FLD_FLD_EN2 BIT(1)
73 #define FLD_FLD_EN BIT(0)
74
75 /* Automatic Standby Control */
76 #define ASTBY_REG 0x20
77
78 /* Long Data Type Setting 0 */
79 #define LNGDT0_REG 0x28
80
81 /* Long Data Type Setting 1 */
82 #define LNGDT1_REG 0x2c
83
84 /* Interrupt Enable */
85 #define INTEN_REG 0x30
86
87 /* Interrupt Source Mask */
88 #define INTCLOSE_REG 0x34
89
90 /* Interrupt Status Monitor */
91 #define INTSTATE_REG 0x38
92 #define INTSTATE_INT_ULPS_START BIT(7)
93 #define INTSTATE_INT_ULPS_END BIT(6)
94
95 /* Interrupt Error Status Monitor */
96 #define INTERRSTATE_REG 0x3c
97
98 /* Short Packet Data */
99 #define SHPDAT_REG 0x40
100
101 /* Short Packet Count */
102 #define SHPCNT_REG 0x44
103
104 /* LINK Operation Control */
105 #define LINKCNT_REG 0x48
106 #define LINKCNT_MONITOR_EN BIT(31)
107 #define LINKCNT_REG_MONI_PACT_EN BIT(25)
108 #define LINKCNT_ICLK_NONSTOP BIT(24)
109
110 /* Lane Swap */
111 #define LSWAP_REG 0x4c
112 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
113 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
114 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
115 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
116
117 /* PHY Test Interface Write Register */
118 #define PHTW_REG 0x50
119 #define PHTW_DWEN BIT(24)
120 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
121 #define PHTW_CWEN BIT(8)
122 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
123
124 struct phtw_value {
125 u16 data;
126 u16 code;
127 };
128
129 struct rcsi2_mbps_reg {
130 u16 mbps;
131 u16 reg;
132 };
133
134 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
135 { .mbps = 80, .reg = 0x86 },
136 { .mbps = 90, .reg = 0x86 },
137 { .mbps = 100, .reg = 0x87 },
138 { .mbps = 110, .reg = 0x87 },
139 { .mbps = 120, .reg = 0x88 },
140 { .mbps = 130, .reg = 0x88 },
141 { .mbps = 140, .reg = 0x89 },
142 { .mbps = 150, .reg = 0x89 },
143 { .mbps = 160, .reg = 0x8a },
144 { .mbps = 170, .reg = 0x8a },
145 { .mbps = 180, .reg = 0x8b },
146 { .mbps = 190, .reg = 0x8b },
147 { .mbps = 205, .reg = 0x8c },
148 { .mbps = 220, .reg = 0x8d },
149 { .mbps = 235, .reg = 0x8e },
150 { .mbps = 250, .reg = 0x8e },
151 { /* sentinel */ },
152 };
153
154 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
155 { .mbps = 80, .reg = 0x00 },
156 { .mbps = 90, .reg = 0x20 },
157 { .mbps = 100, .reg = 0x40 },
158 { .mbps = 110, .reg = 0x02 },
159 { .mbps = 130, .reg = 0x22 },
160 { .mbps = 140, .reg = 0x42 },
161 { .mbps = 150, .reg = 0x04 },
162 { .mbps = 170, .reg = 0x24 },
163 { .mbps = 180, .reg = 0x44 },
164 { .mbps = 200, .reg = 0x06 },
165 { .mbps = 220, .reg = 0x26 },
166 { .mbps = 240, .reg = 0x46 },
167 { .mbps = 250, .reg = 0x08 },
168 { .mbps = 270, .reg = 0x28 },
169 { .mbps = 300, .reg = 0x0a },
170 { .mbps = 330, .reg = 0x2a },
171 { .mbps = 360, .reg = 0x4a },
172 { .mbps = 400, .reg = 0x0c },
173 { .mbps = 450, .reg = 0x2c },
174 { .mbps = 500, .reg = 0x0e },
175 { .mbps = 550, .reg = 0x2e },
176 { .mbps = 600, .reg = 0x10 },
177 { .mbps = 650, .reg = 0x30 },
178 { .mbps = 700, .reg = 0x12 },
179 { .mbps = 750, .reg = 0x32 },
180 { .mbps = 800, .reg = 0x52 },
181 { .mbps = 850, .reg = 0x72 },
182 { .mbps = 900, .reg = 0x14 },
183 { .mbps = 950, .reg = 0x34 },
184 { .mbps = 1000, .reg = 0x54 },
185 { .mbps = 1050, .reg = 0x74 },
186 { .mbps = 1125, .reg = 0x16 },
187 { /* sentinel */ },
188 };
189
190 /* PHY Test Interface Clear */
191 #define PHTC_REG 0x58
192 #define PHTC_TESTCLR BIT(0)
193
194 /* PHY Frequency Control */
195 #define PHYPLL_REG 0x68
196 #define PHYPLL_HSFREQRANGE(n) ((n) << 16)
197
198 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
199 { .mbps = 80, .reg = 0x00 },
200 { .mbps = 90, .reg = 0x10 },
201 { .mbps = 100, .reg = 0x20 },
202 { .mbps = 110, .reg = 0x30 },
203 { .mbps = 120, .reg = 0x01 },
204 { .mbps = 130, .reg = 0x11 },
205 { .mbps = 140, .reg = 0x21 },
206 { .mbps = 150, .reg = 0x31 },
207 { .mbps = 160, .reg = 0x02 },
208 { .mbps = 170, .reg = 0x12 },
209 { .mbps = 180, .reg = 0x22 },
210 { .mbps = 190, .reg = 0x32 },
211 { .mbps = 205, .reg = 0x03 },
212 { .mbps = 220, .reg = 0x13 },
213 { .mbps = 235, .reg = 0x23 },
214 { .mbps = 250, .reg = 0x33 },
215 { .mbps = 275, .reg = 0x04 },
216 { .mbps = 300, .reg = 0x14 },
217 { .mbps = 325, .reg = 0x25 },
218 { .mbps = 350, .reg = 0x35 },
219 { .mbps = 400, .reg = 0x05 },
220 { .mbps = 450, .reg = 0x16 },
221 { .mbps = 500, .reg = 0x26 },
222 { .mbps = 550, .reg = 0x37 },
223 { .mbps = 600, .reg = 0x07 },
224 { .mbps = 650, .reg = 0x18 },
225 { .mbps = 700, .reg = 0x28 },
226 { .mbps = 750, .reg = 0x39 },
227 { .mbps = 800, .reg = 0x09 },
228 { .mbps = 850, .reg = 0x19 },
229 { .mbps = 900, .reg = 0x29 },
230 { .mbps = 950, .reg = 0x3a },
231 { .mbps = 1000, .reg = 0x0a },
232 { .mbps = 1050, .reg = 0x1a },
233 { .mbps = 1100, .reg = 0x2a },
234 { .mbps = 1150, .reg = 0x3b },
235 { .mbps = 1200, .reg = 0x0b },
236 { .mbps = 1250, .reg = 0x1b },
237 { .mbps = 1300, .reg = 0x2b },
238 { .mbps = 1350, .reg = 0x3c },
239 { .mbps = 1400, .reg = 0x0c },
240 { .mbps = 1450, .reg = 0x1c },
241 { .mbps = 1500, .reg = 0x2c },
242 { /* sentinel */ },
243 };
244
245 static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
246 { .mbps = 80, .reg = 0x00 },
247 { .mbps = 90, .reg = 0x10 },
248 { .mbps = 100, .reg = 0x20 },
249 { .mbps = 110, .reg = 0x30 },
250 { .mbps = 120, .reg = 0x01 },
251 { .mbps = 130, .reg = 0x11 },
252 { .mbps = 140, .reg = 0x21 },
253 { .mbps = 150, .reg = 0x31 },
254 { .mbps = 160, .reg = 0x02 },
255 { .mbps = 170, .reg = 0x12 },
256 { .mbps = 180, .reg = 0x22 },
257 { .mbps = 190, .reg = 0x32 },
258 { .mbps = 205, .reg = 0x03 },
259 { .mbps = 220, .reg = 0x13 },
260 { .mbps = 235, .reg = 0x23 },
261 { .mbps = 250, .reg = 0x33 },
262 { .mbps = 275, .reg = 0x04 },
263 { .mbps = 300, .reg = 0x14 },
264 { .mbps = 325, .reg = 0x05 },
265 { .mbps = 350, .reg = 0x15 },
266 { .mbps = 400, .reg = 0x25 },
267 { .mbps = 450, .reg = 0x06 },
268 { .mbps = 500, .reg = 0x16 },
269 { .mbps = 550, .reg = 0x07 },
270 { .mbps = 600, .reg = 0x17 },
271 { .mbps = 650, .reg = 0x08 },
272 { .mbps = 700, .reg = 0x18 },
273 { .mbps = 750, .reg = 0x09 },
274 { .mbps = 800, .reg = 0x19 },
275 { .mbps = 850, .reg = 0x29 },
276 { .mbps = 900, .reg = 0x39 },
277 { .mbps = 950, .reg = 0x0a },
278 { .mbps = 1000, .reg = 0x1a },
279 { .mbps = 1050, .reg = 0x2a },
280 { .mbps = 1100, .reg = 0x3a },
281 { .mbps = 1150, .reg = 0x0b },
282 { .mbps = 1200, .reg = 0x1b },
283 { .mbps = 1250, .reg = 0x2b },
284 { .mbps = 1300, .reg = 0x3b },
285 { .mbps = 1350, .reg = 0x0c },
286 { .mbps = 1400, .reg = 0x1c },
287 { .mbps = 1450, .reg = 0x2c },
288 { .mbps = 1500, .reg = 0x3c },
289 { /* sentinel */ },
290 };
291
292 /* PHY ESC Error Monitor */
293 #define PHEERM_REG 0x74
294
295 /* PHY Clock Lane Monitor */
296 #define PHCLM_REG 0x78
297 #define PHCLM_STOPSTATECKL BIT(0)
298
299 /* PHY Data Lane Monitor */
300 #define PHDLM_REG 0x7c
301
302 /* CSI0CLK Frequency Configuration Preset Register */
303 #define CSI0CLKFCPR_REG 0x260
304 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
305
306 struct rcar_csi2_format {
307 u32 code;
308 unsigned int datatype;
309 unsigned int bpp;
310 };
311
312 static const struct rcar_csi2_format rcar_csi2_formats[] = {
313 { .code = MEDIA_BUS_FMT_RGB888_1X24, .datatype = 0x24, .bpp = 24 },
314 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 },
315 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .datatype = 0x1e, .bpp = 16 },
316 { .code = MEDIA_BUS_FMT_UYVY8_2X8, .datatype = 0x1e, .bpp = 16 },
317 { .code = MEDIA_BUS_FMT_YUYV10_2X10, .datatype = 0x1e, .bpp = 20 },
318 };
319
320 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
321 {
322 unsigned int i;
323
324 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
325 if (rcar_csi2_formats[i].code == code)
326 return &rcar_csi2_formats[i];
327
328 return NULL;
329 }
330
331 enum rcar_csi2_pads {
332 RCAR_CSI2_SINK,
333 RCAR_CSI2_SOURCE_VC0,
334 RCAR_CSI2_SOURCE_VC1,
335 RCAR_CSI2_SOURCE_VC2,
336 RCAR_CSI2_SOURCE_VC3,
337 NR_OF_RCAR_CSI2_PAD,
338 };
339
340 struct rcar_csi2_info {
341 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
342 int (*confirm_start)(struct rcar_csi2 *priv);
343 const struct rcsi2_mbps_reg *hsfreqrange;
344 unsigned int csi0clkfreqrange;
345 bool clear_ulps;
346 };
347
348 struct rcar_csi2 {
349 struct device *dev;
350 void __iomem *base;
351 const struct rcar_csi2_info *info;
352
353 struct v4l2_subdev subdev;
354 struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
355
356 struct v4l2_async_notifier notifier;
357 struct v4l2_async_subdev asd;
358 struct v4l2_subdev *remote;
359
360 struct v4l2_mbus_framefmt mf;
361
362 struct mutex lock;
363 int stream_count;
364
365 unsigned short lanes;
366 unsigned char lane_swap[4];
367 };
368
369 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
370 {
371 return container_of(sd, struct rcar_csi2, subdev);
372 }
373
374 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
375 {
376 return container_of(n, struct rcar_csi2, notifier);
377 }
378
379 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
380 {
381 return ioread32(priv->base + reg);
382 }
383
384 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
385 {
386 iowrite32(data, priv->base + reg);
387 }
388
389 static void rcsi2_reset(struct rcar_csi2 *priv)
390 {
391 rcsi2_write(priv, SRST_REG, SRST_SRST);
392 usleep_range(100, 150);
393 rcsi2_write(priv, SRST_REG, 0);
394 }
395
396 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv)
397 {
398 unsigned int timeout;
399
400 /* Wait for the clock and data lanes to enter LP-11 state. */
401 for (timeout = 0; timeout <= 20; timeout++) {
402 const u32 lane_mask = (1 << priv->lanes) - 1;
403
404 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
405 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
406 return 0;
407
408 usleep_range(1000, 2000);
409 }
410
411 dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
412
413 return -ETIMEDOUT;
414 }
415
416 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
417 {
418 const struct rcsi2_mbps_reg *hsfreq;
419
420 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++)
421 if (hsfreq->mbps >= mbps)
422 break;
423
424 if (!hsfreq->mbps) {
425 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
426 return -ERANGE;
427 }
428
429 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
430
431 return 0;
432 }
433
434 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp)
435 {
436 struct v4l2_subdev *source;
437 struct v4l2_ctrl *ctrl;
438 u64 mbps;
439
440 if (!priv->remote)
441 return -ENODEV;
442
443 source = priv->remote;
444
445 /* Read the pixel rate control from remote. */
446 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
447 if (!ctrl) {
448 dev_err(priv->dev, "no pixel rate control in subdev %s\n",
449 source->name);
450 return -EINVAL;
451 }
452
453 /*
454 * Calculate the phypll in mbps.
455 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
456 * bps = link_freq * 2
457 */
458 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
459 do_div(mbps, priv->lanes * 1000000);
460
461 return mbps;
462 }
463
464 static int rcsi2_start(struct rcar_csi2 *priv)
465 {
466 const struct rcar_csi2_format *format;
467 u32 phycnt, vcdt = 0, vcdt2 = 0;
468 unsigned int i;
469 int mbps, ret;
470
471 dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
472 priv->mf.width, priv->mf.height,
473 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
474
475 /* Code is validated in set_fmt. */
476 format = rcsi2_code_to_fmt(priv->mf.code);
477
478 /*
479 * Enable all Virtual Channels.
480 *
481 * NOTE: It's not possible to get individual datatype for each
482 * source virtual channel. Once this is possible in V4L2
483 * it should be used here.
484 */
485 for (i = 0; i < 4; i++) {
486 u32 vcdt_part;
487
488 vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
489 VCDT_SEL_DT(format->datatype);
490
491 /* Store in correct reg and offset. */
492 if (i < 2)
493 vcdt |= vcdt_part << ((i % 2) * 16);
494 else
495 vcdt2 |= vcdt_part << ((i % 2) * 16);
496 }
497
498 phycnt = PHYCNT_ENABLECLK;
499 phycnt |= (1 << priv->lanes) - 1;
500
501 mbps = rcsi2_calc_mbps(priv, format->bpp);
502 if (mbps < 0)
503 return mbps;
504
505 /* Init */
506 rcsi2_write(priv, TREF_REG, TREF_TREF);
507 rcsi2_reset(priv);
508 rcsi2_write(priv, PHTC_REG, 0);
509
510 /* Configure */
511 rcsi2_write(priv, FLD_REG, FLD_FLD_NUM(2) | FLD_FLD_EN4 |
512 FLD_FLD_EN3 | FLD_FLD_EN2 | FLD_FLD_EN);
513 rcsi2_write(priv, VCDT_REG, vcdt);
514 rcsi2_write(priv, VCDT2_REG, vcdt2);
515 /* Lanes are zero indexed. */
516 rcsi2_write(priv, LSWAP_REG,
517 LSWAP_L0SEL(priv->lane_swap[0] - 1) |
518 LSWAP_L1SEL(priv->lane_swap[1] - 1) |
519 LSWAP_L2SEL(priv->lane_swap[2] - 1) |
520 LSWAP_L3SEL(priv->lane_swap[3] - 1));
521
522 /* Start */
523 if (priv->info->init_phtw) {
524 ret = priv->info->init_phtw(priv, mbps);
525 if (ret)
526 return ret;
527 }
528
529 if (priv->info->hsfreqrange) {
530 ret = rcsi2_set_phypll(priv, mbps);
531 if (ret)
532 return ret;
533 }
534
535 if (priv->info->csi0clkfreqrange)
536 rcsi2_write(priv, CSI0CLKFCPR_REG,
537 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
538
539 rcsi2_write(priv, PHYCNT_REG, phycnt);
540 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
541 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
542 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
543 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
544
545 ret = rcsi2_wait_phy_start(priv);
546 if (ret)
547 return ret;
548
549 /* Confirm start */
550 if (priv->info->confirm_start) {
551 ret = priv->info->confirm_start(priv);
552 if (ret)
553 return ret;
554 }
555
556 /* Clear Ultra Low Power interrupt. */
557 if (priv->info->clear_ulps)
558 rcsi2_write(priv, INTSTATE_REG,
559 INTSTATE_INT_ULPS_START |
560 INTSTATE_INT_ULPS_END);
561 return 0;
562 }
563
564 static void rcsi2_stop(struct rcar_csi2 *priv)
565 {
566 rcsi2_write(priv, PHYCNT_REG, 0);
567
568 rcsi2_reset(priv);
569
570 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
571 }
572
573 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
574 {
575 struct rcar_csi2 *priv = sd_to_csi2(sd);
576 struct v4l2_subdev *nextsd;
577 int ret = 0;
578
579 mutex_lock(&priv->lock);
580
581 if (!priv->remote) {
582 ret = -ENODEV;
583 goto out;
584 }
585
586 nextsd = priv->remote;
587
588 if (enable && priv->stream_count == 0) {
589 pm_runtime_get_sync(priv->dev);
590
591 ret = rcsi2_start(priv);
592 if (ret) {
593 pm_runtime_put(priv->dev);
594 goto out;
595 }
596
597 ret = v4l2_subdev_call(nextsd, video, s_stream, 1);
598 if (ret) {
599 rcsi2_stop(priv);
600 pm_runtime_put(priv->dev);
601 goto out;
602 }
603 } else if (!enable && priv->stream_count == 1) {
604 rcsi2_stop(priv);
605 v4l2_subdev_call(nextsd, video, s_stream, 0);
606 pm_runtime_put(priv->dev);
607 }
608
609 priv->stream_count += enable ? 1 : -1;
610 out:
611 mutex_unlock(&priv->lock);
612
613 return ret;
614 }
615
616 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
617 struct v4l2_subdev_pad_config *cfg,
618 struct v4l2_subdev_format *format)
619 {
620 struct rcar_csi2 *priv = sd_to_csi2(sd);
621 struct v4l2_mbus_framefmt *framefmt;
622
623 if (!rcsi2_code_to_fmt(format->format.code))
624 format->format.code = rcar_csi2_formats[0].code;
625
626 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
627 priv->mf = format->format;
628 } else {
629 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
630 *framefmt = format->format;
631 }
632
633 return 0;
634 }
635
636 static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
637 struct v4l2_subdev_pad_config *cfg,
638 struct v4l2_subdev_format *format)
639 {
640 struct rcar_csi2 *priv = sd_to_csi2(sd);
641
642 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
643 format->format = priv->mf;
644 else
645 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
646
647 return 0;
648 }
649
650 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
651 .s_stream = rcsi2_s_stream,
652 };
653
654 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
655 .set_fmt = rcsi2_set_pad_format,
656 .get_fmt = rcsi2_get_pad_format,
657 };
658
659 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
660 .video = &rcar_csi2_video_ops,
661 .pad = &rcar_csi2_pad_ops,
662 };
663
664 /* -----------------------------------------------------------------------------
665 * Async handling and registration of subdevices and links.
666 */
667
668 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
669 struct v4l2_subdev *subdev,
670 struct v4l2_async_subdev *asd)
671 {
672 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
673 int pad;
674
675 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
676 MEDIA_PAD_FL_SOURCE);
677 if (pad < 0) {
678 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
679 return pad;
680 }
681
682 priv->remote = subdev;
683
684 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
685
686 return media_create_pad_link(&subdev->entity, pad,
687 &priv->subdev.entity, 0,
688 MEDIA_LNK_FL_ENABLED |
689 MEDIA_LNK_FL_IMMUTABLE);
690 }
691
692 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
693 struct v4l2_subdev *subdev,
694 struct v4l2_async_subdev *asd)
695 {
696 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
697
698 priv->remote = NULL;
699
700 dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
701 }
702
703 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
704 .bound = rcsi2_notify_bound,
705 .unbind = rcsi2_notify_unbind,
706 };
707
708 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
709 struct v4l2_fwnode_endpoint *vep)
710 {
711 unsigned int i;
712
713 /* Only port 0 endpoint 0 is valid. */
714 if (vep->base.port || vep->base.id)
715 return -ENOTCONN;
716
717 if (vep->bus_type != V4L2_MBUS_CSI2) {
718 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
719 return -EINVAL;
720 }
721
722 priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
723 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
724 dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
725 priv->lanes);
726 return -EINVAL;
727 }
728
729 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
730 priv->lane_swap[i] = i < priv->lanes ?
731 vep->bus.mipi_csi2.data_lanes[i] : i;
732
733 /* Check for valid lane number. */
734 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
735 dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
736 return -EINVAL;
737 }
738 }
739
740 return 0;
741 }
742
743 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
744 {
745 struct device_node *ep;
746 struct v4l2_fwnode_endpoint v4l2_ep;
747 int ret;
748
749 ep = of_graph_get_endpoint_by_regs(priv->dev->of_node, 0, 0);
750 if (!ep) {
751 dev_err(priv->dev, "Not connected to subdevice\n");
752 return -EINVAL;
753 }
754
755 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep);
756 if (ret) {
757 dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
758 of_node_put(ep);
759 return -EINVAL;
760 }
761
762 ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
763 if (ret) {
764 of_node_put(ep);
765 return ret;
766 }
767
768 priv->asd.match.fwnode =
769 fwnode_graph_get_remote_endpoint(of_fwnode_handle(ep));
770 priv->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
771
772 of_node_put(ep);
773
774 priv->notifier.subdevs = devm_kzalloc(priv->dev,
775 sizeof(*priv->notifier.subdevs),
776 GFP_KERNEL);
777 if (!priv->notifier.subdevs)
778 return -ENOMEM;
779
780 priv->notifier.num_subdevs = 1;
781 priv->notifier.subdevs[0] = &priv->asd;
782 priv->notifier.ops = &rcar_csi2_notify_ops;
783
784 dev_dbg(priv->dev, "Found '%pOF'\n",
785 to_of_node(priv->asd.match.fwnode));
786
787 return v4l2_async_subdev_notifier_register(&priv->subdev,
788 &priv->notifier);
789 }
790
791 /* -----------------------------------------------------------------------------
792 * PHTW initialization sequences.
793 *
794 * NOTE: Magic values are from the datasheet and lack documentation.
795 */
796
797 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
798 {
799 unsigned int timeout;
800
801 rcsi2_write(priv, PHTW_REG,
802 PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
803 PHTW_CWEN | PHTW_TESTDIN_CODE(code));
804
805 /* Wait for DWEN and CWEN to be cleared by hardware. */
806 for (timeout = 0; timeout <= 20; timeout++) {
807 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
808 return 0;
809
810 usleep_range(1000, 2000);
811 }
812
813 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
814
815 return -ETIMEDOUT;
816 }
817
818 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
819 const struct phtw_value *values)
820 {
821 const struct phtw_value *value;
822 int ret;
823
824 for (value = values; value->data || value->code; value++) {
825 ret = rcsi2_phtw_write(priv, value->data, value->code);
826 if (ret)
827 return ret;
828 }
829
830 return 0;
831 }
832
833 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
834 const struct rcsi2_mbps_reg *values, u16 code)
835 {
836 const struct rcsi2_mbps_reg *value;
837
838 for (value = values; value->mbps; value++)
839 if (value->mbps >= mbps)
840 break;
841
842 if (!value->mbps) {
843 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
844 return -ERANGE;
845 }
846
847 return rcsi2_phtw_write(priv, value->reg, code);
848 }
849
850 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
851 {
852 static const struct phtw_value step1[] = {
853 { .data = 0xcc, .code = 0xe2 },
854 { .data = 0x01, .code = 0xe3 },
855 { .data = 0x11, .code = 0xe4 },
856 { .data = 0x01, .code = 0xe5 },
857 { .data = 0x10, .code = 0x04 },
858 { /* sentinel */ },
859 };
860
861 static const struct phtw_value step2[] = {
862 { .data = 0x38, .code = 0x08 },
863 { .data = 0x01, .code = 0x00 },
864 { .data = 0x4b, .code = 0xac },
865 { .data = 0x03, .code = 0x00 },
866 { .data = 0x80, .code = 0x07 },
867 { /* sentinel */ },
868 };
869
870 int ret;
871
872 ret = rcsi2_phtw_write_array(priv, step1);
873 if (ret)
874 return ret;
875
876 if (mbps <= 250) {
877 ret = rcsi2_phtw_write(priv, 0x39, 0x05);
878 if (ret)
879 return ret;
880
881 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
882 0xf1);
883 if (ret)
884 return ret;
885 }
886
887 return rcsi2_phtw_write_array(priv, step2);
888 }
889
890 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
891 {
892 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
893 }
894
895 static int rcsi2_confirm_start_v3m_e3(struct rcar_csi2 *priv)
896 {
897 static const struct phtw_value step1[] = {
898 { .data = 0xed, .code = 0x34 },
899 { .data = 0xed, .code = 0x44 },
900 { .data = 0xed, .code = 0x54 },
901 { .data = 0xed, .code = 0x84 },
902 { .data = 0xed, .code = 0x94 },
903 { /* sentinel */ },
904 };
905
906 return rcsi2_phtw_write_array(priv, step1);
907 }
908
909 /* -----------------------------------------------------------------------------
910 * Platform Device Driver.
911 */
912
913 static const struct media_entity_operations rcar_csi2_entity_ops = {
914 .link_validate = v4l2_subdev_link_validate,
915 };
916
917 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
918 struct platform_device *pdev)
919 {
920 struct resource *res;
921 int irq;
922
923 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
924 priv->base = devm_ioremap_resource(&pdev->dev, res);
925 if (IS_ERR(priv->base))
926 return PTR_ERR(priv->base);
927
928 irq = platform_get_irq(pdev, 0);
929 if (irq < 0)
930 return irq;
931
932 return 0;
933 }
934
935 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
936 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
937 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
938 .csi0clkfreqrange = 0x20,
939 .clear_ulps = true,
940 };
941
942 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
943 .hsfreqrange = hsfreqrange_m3w_h3es1,
944 };
945
946 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
947 .hsfreqrange = hsfreqrange_m3w_h3es1,
948 };
949
950 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
951 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
952 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
953 .csi0clkfreqrange = 0x20,
954 .clear_ulps = true,
955 };
956
957 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
958 .init_phtw = rcsi2_init_phtw_v3m_e3,
959 .confirm_start = rcsi2_confirm_start_v3m_e3,
960 };
961
962 static const struct of_device_id rcar_csi2_of_table[] = {
963 {
964 .compatible = "renesas,r8a7795-csi2",
965 .data = &rcar_csi2_info_r8a7795,
966 },
967 {
968 .compatible = "renesas,r8a7796-csi2",
969 .data = &rcar_csi2_info_r8a7796,
970 },
971 {
972 .compatible = "renesas,r8a77965-csi2",
973 .data = &rcar_csi2_info_r8a77965,
974 },
975 {
976 .compatible = "renesas,r8a77970-csi2",
977 .data = &rcar_csi2_info_r8a77970,
978 },
979 { /* sentinel */ },
980 };
981 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
982
983 static const struct soc_device_attribute r8a7795es1[] = {
984 {
985 .soc_id = "r8a7795", .revision = "ES1.*",
986 .data = &rcar_csi2_info_r8a7795es1,
987 },
988 { /* sentinel */ },
989 };
990
991 static int rcsi2_probe(struct platform_device *pdev)
992 {
993 const struct soc_device_attribute *attr;
994 struct rcar_csi2 *priv;
995 unsigned int i;
996 int ret;
997
998 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
999 if (!priv)
1000 return -ENOMEM;
1001
1002 priv->info = of_device_get_match_data(&pdev->dev);
1003
1004 /*
1005 * r8a7795 ES1.x behaves differently than the ES2.0+ but doesn't
1006 * have it's own compatible string.
1007 */
1008 attr = soc_device_match(r8a7795es1);
1009 if (attr)
1010 priv->info = attr->data;
1011
1012 priv->dev = &pdev->dev;
1013
1014 mutex_init(&priv->lock);
1015 priv->stream_count = 0;
1016
1017 ret = rcsi2_probe_resources(priv, pdev);
1018 if (ret) {
1019 dev_err(priv->dev, "Failed to get resources\n");
1020 return ret;
1021 }
1022
1023 platform_set_drvdata(pdev, priv);
1024
1025 ret = rcsi2_parse_dt(priv);
1026 if (ret)
1027 return ret;
1028
1029 priv->subdev.owner = THIS_MODULE;
1030 priv->subdev.dev = &pdev->dev;
1031 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
1032 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
1033 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
1034 KBUILD_MODNAME, dev_name(&pdev->dev));
1035 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1036
1037 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1038 priv->subdev.entity.ops = &rcar_csi2_entity_ops;
1039
1040 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
1041 for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++)
1042 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
1043
1044 ret = media_entity_pads_init(&priv->subdev.entity, NR_OF_RCAR_CSI2_PAD,
1045 priv->pads);
1046 if (ret)
1047 goto error;
1048
1049 pm_runtime_enable(&pdev->dev);
1050
1051 ret = v4l2_async_register_subdev(&priv->subdev);
1052 if (ret < 0)
1053 goto error;
1054
1055 dev_info(priv->dev, "%d lanes found\n", priv->lanes);
1056
1057 return 0;
1058
1059 error:
1060 v4l2_async_notifier_unregister(&priv->notifier);
1061 v4l2_async_notifier_cleanup(&priv->notifier);
1062
1063 return ret;
1064 }
1065
1066 static int rcsi2_remove(struct platform_device *pdev)
1067 {
1068 struct rcar_csi2 *priv = platform_get_drvdata(pdev);
1069
1070 v4l2_async_notifier_unregister(&priv->notifier);
1071 v4l2_async_notifier_cleanup(&priv->notifier);
1072 v4l2_async_unregister_subdev(&priv->subdev);
1073
1074 pm_runtime_disable(&pdev->dev);
1075
1076 return 0;
1077 }
1078
1079 static struct platform_driver rcar_csi2_pdrv = {
1080 .remove = rcsi2_remove,
1081 .probe = rcsi2_probe,
1082 .driver = {
1083 .name = "rcar-csi2",
1084 .of_match_table = rcar_csi2_of_table,
1085 },
1086 };
1087
1088 module_platform_driver(rcar_csi2_pdrv);
1089
1090 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
1091 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
1092 MODULE_LICENSE("GPL");
Linux with added FPC-III support