drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c

   1 /* drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c
   2  *
   3  * Copyright (c) 2009, 2014 Samsung Electronics
   4  *              http://www.samsung.com/
   5  *
   6  * cec ftn file for Samsung TVOUT driver
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/device.h>
  15
  16 #include "exynos_hdmi_cec.h"
  17 #include "regs-cec.h"
  18
  19 #define S5P_HDMI_FIN                    24000000
  20 #define CEC_DIV_RATIO                   320000
  21
  22 #define CEC_MESSAGE_BROADCAST_MASK      0x0F
  23 #define CEC_MESSAGE_BROADCAST           0x0F
  24 #define CEC_FILTER_THRESHOLD            0x15
  25
  26 void s5p_cec_set_divider(struct s5p_cec_dev *cec)
  27 {
  28         u32 div_ratio, div_val;
  29         unsigned int reg;
  30
  31         div_ratio  = S5P_HDMI_FIN / CEC_DIV_RATIO - 1;
  32
  33         if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, &reg)) {
  34                 dev_err(cec->dev, "failed to read phy control\n");
  35                 return;
  36         }
  37
  38         reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16);
  39
  40         if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) {
  41                 dev_err(cec->dev, "failed to write phy control\n");
  42                 return;
  43         }
  44
  45         div_val = CEC_DIV_RATIO * 0.00005 - 1;
  46
  47         writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3);
  48         writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2);
  49         writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1);
  50         writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0);
  51 }
  52
  53 void s5p_cec_enable_rx(struct s5p_cec_dev *cec)
  54 {
  55         u8 reg;
  56
  57         reg = readb(cec->reg + S5P_CEC_RX_CTRL);
  58         reg |= S5P_CEC_RX_CTRL_ENABLE;
  59         writeb(reg, cec->reg + S5P_CEC_RX_CTRL);
  60 }
  61
  62 void s5p_cec_mask_rx_interrupts(struct s5p_cec_dev *cec)
  63 {
  64         u8 reg;
  65
  66         reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
  67         reg |= S5P_CEC_IRQ_RX_DONE;
  68         reg |= S5P_CEC_IRQ_RX_ERROR;
  69         writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
  70 }
  71
  72 void s5p_cec_unmask_rx_interrupts(struct s5p_cec_dev *cec)
  73 {
  74         u8 reg;
  75
  76         reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
  77         reg &= ~S5P_CEC_IRQ_RX_DONE;
  78         reg &= ~S5P_CEC_IRQ_RX_ERROR;
  79         writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
  80 }
  81
  82 void s5p_cec_mask_tx_interrupts(struct s5p_cec_dev *cec)
  83 {
  84         u8 reg;
  85
  86         reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
  87         reg |= S5P_CEC_IRQ_TX_DONE;
  88         reg |= S5P_CEC_IRQ_TX_ERROR;
  89         writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
  90 }
  91
  92 void s5p_cec_unmask_tx_interrupts(struct s5p_cec_dev *cec)
  93 {
  94         u8 reg;
  95
  96         reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
  97         reg &= ~S5P_CEC_IRQ_TX_DONE;
  98         reg &= ~S5P_CEC_IRQ_TX_ERROR;
  99         writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
 100 }
 101
 102 void s5p_cec_reset(struct s5p_cec_dev *cec)
 103 {
 104         u8 reg;
 105
 106         writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL);
 107         writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL);
 108
 109         reg = readb(cec->reg + 0xc4);
 110         reg &= ~0x1;
 111         writeb(reg, cec->reg + 0xc4);
 112 }
 113
 114 void s5p_cec_tx_reset(struct s5p_cec_dev *cec)
 115 {
 116         writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL);
 117 }
 118
 119 void s5p_cec_rx_reset(struct s5p_cec_dev *cec)
 120 {
 121         u8 reg;
 122
 123         writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL);
 124
 125         reg = readb(cec->reg + 0xc4);
 126         reg &= ~0x1;
 127         writeb(reg, cec->reg + 0xc4);
 128 }
 129
 130 void s5p_cec_threshold(struct s5p_cec_dev *cec)
 131 {
 132         writeb(CEC_FILTER_THRESHOLD, cec->reg + S5P_CEC_RX_FILTER_TH);
 133         writeb(0, cec->reg + S5P_CEC_RX_FILTER_CTRL);
 134 }
 135
 136 void s5p_cec_copy_packet(struct s5p_cec_dev *cec, char *data,
 137                          size_t count, u8 retries)
 138 {
 139         int i = 0;
 140         u8 reg;
 141
 142         while (i < count) {
 143                 writeb(data[i], cec->reg + (S5P_CEC_TX_BUFF0 + (i * 4)));
 144                 i++;
 145         }
 146
 147         writeb(count, cec->reg + S5P_CEC_TX_BYTES);
 148         reg = readb(cec->reg + S5P_CEC_TX_CTRL);
 149         reg |= S5P_CEC_TX_CTRL_START;
 150         reg &= ~0x70;
 151         reg |= retries << 4;
 152
 153         if ((data[0] & CEC_MESSAGE_BROADCAST_MASK) == CEC_MESSAGE_BROADCAST) {
 154                 dev_dbg(cec->dev, "Broadcast");
 155                 reg |= S5P_CEC_TX_CTRL_BCAST;
 156         } else {
 157                 dev_dbg(cec->dev, "No Broadcast");
 158                 reg &= ~S5P_CEC_TX_CTRL_BCAST;
 159         }
 160
 161         writeb(reg, cec->reg + S5P_CEC_TX_CTRL);
 162         dev_dbg(cec->dev, "cec-tx: cec count (%zu): %*ph", count,
 163                 (int)count, data);
 164 }
 165
 166 void s5p_cec_set_addr(struct s5p_cec_dev *cec, u32 addr)
 167 {
 168         writeb(addr & 0x0F, cec->reg + S5P_CEC_LOGIC_ADDR);
 169 }
 170
 171 u32 s5p_cec_get_status(struct s5p_cec_dev *cec)
 172 {
 173         u32 status = 0;
 174
 175         status = readb(cec->reg + S5P_CEC_STATUS_0) & 0xf;
 176         status |= (readb(cec->reg + S5P_CEC_TX_STAT1) & 0xf) << 4;
 177         status |= readb(cec->reg + S5P_CEC_STATUS_1) << 8;
 178         status |= readb(cec->reg + S5P_CEC_STATUS_2) << 16;
 179         status |= readb(cec->reg + S5P_CEC_STATUS_3) << 24;
 180
 181         dev_dbg(cec->dev, "status = 0x%x!\n", status);
 182
 183         return status;
 184 }
 185
 186 void s5p_clr_pending_tx(struct s5p_cec_dev *cec)
 187 {
 188         writeb(S5P_CEC_IRQ_TX_DONE | S5P_CEC_IRQ_TX_ERROR,
 189                cec->reg + S5P_CEC_IRQ_CLEAR);
 190 }
 191
 192 void s5p_clr_pending_rx(struct s5p_cec_dev *cec)
 193 {
 194         writeb(S5P_CEC_IRQ_RX_DONE | S5P_CEC_IRQ_RX_ERROR,
 195                cec->reg + S5P_CEC_IRQ_CLEAR);
 196 }
 197
 198 void s5p_cec_get_rx_buf(struct s5p_cec_dev *cec, u32 size, u8 *buffer)
 199 {
 200         u32 i = 0;
 201         char debug[40];
 202
 203         while (i < size) {
 204                 buffer[i] = readb(cec->reg + S5P_CEC_RX_BUFF0 + (i * 4));
 205                 sprintf(debug + i * 2, "%02x ", buffer[i]);
 206                 i++;
 207         }
 208         dev_dbg(cec->dev, "cec-rx: cec size(%d): %s", size, debug);
 209 }