2 /* By Ross Biro 1/23/92 */
3 /* edited by Linus Torvalds */
4 /* mangled further by Bob Manson (manson@santafe.edu) */
5 /* more mutilation by David Mosberger (davidm@azstarnet.com) */
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/smp.h>
11 #include <linux/errno.h>
12 #include <linux/ptrace.h>
13 #include <linux/user.h>
14 #include <linux/security.h>
15 #include <linux/signal.h>
16 #include <linux/tracehook.h>
18 #include <asm/uaccess.h>
19 #include <asm/pgtable.h>
33 #define DBG(fac,args) {if ((fac) & DEBUG) printk args;}
38 #define BREAKINST 0x00000080 /* call_pal bpt */
41 * does not yet catch signals sent when the child dies.
42 * in exit.c or in signal.c.
46 * Processes always block with the following stack-layout:
48 * +================================+ <---- task + 2*PAGE_SIZE
49 * | PALcode saved frame (ps, pc, | ^
50 * | gp, a0, a1, a2) | |
51 * +================================+ | struct pt_regs
53 * | frame generated by SAVE_ALL | |
55 * +================================+
57 * | frame saved by do_switch_stack | | struct switch_stack
59 * +================================+
63 * The following table maps a register index into the stack offset at
64 * which the register is saved. Register indices are 0-31 for integer
65 * regs, 32-63 for fp regs, and 64 for the pc. Notice that sp and
66 * zero have no stack-slot and need to be treated specially (see
67 * get_reg/put_reg below).
70 REG_R0
= 0, REG_F0
= 32, REG_FPCR
= 63, REG_PC
= 64
74 (PAGE_SIZE*2 - sizeof(struct pt_regs) + offsetof(struct pt_regs, reg))
77 (PAGE_SIZE*2 - sizeof(struct pt_regs) - sizeof(struct switch_stack) \
78 + offsetof(struct switch_stack, reg))
80 static int regoff
[] = {
81 PT_REG( r0
), PT_REG( r1
), PT_REG( r2
), PT_REG( r3
),
82 PT_REG( r4
), PT_REG( r5
), PT_REG( r6
), PT_REG( r7
),
83 PT_REG( r8
), SW_REG( r9
), SW_REG( r10
), SW_REG( r11
),
84 SW_REG( r12
), SW_REG( r13
), SW_REG( r14
), SW_REG( r15
),
85 PT_REG( r16
), PT_REG( r17
), PT_REG( r18
), PT_REG( r19
),
86 PT_REG( r20
), PT_REG( r21
), PT_REG( r22
), PT_REG( r23
),
87 PT_REG( r24
), PT_REG( r25
), PT_REG( r26
), PT_REG( r27
),
88 PT_REG( r28
), PT_REG( gp
), -1, -1,
89 SW_REG(fp
[ 0]), SW_REG(fp
[ 1]), SW_REG(fp
[ 2]), SW_REG(fp
[ 3]),
90 SW_REG(fp
[ 4]), SW_REG(fp
[ 5]), SW_REG(fp
[ 6]), SW_REG(fp
[ 7]),
91 SW_REG(fp
[ 8]), SW_REG(fp
[ 9]), SW_REG(fp
[10]), SW_REG(fp
[11]),
92 SW_REG(fp
[12]), SW_REG(fp
[13]), SW_REG(fp
[14]), SW_REG(fp
[15]),
93 SW_REG(fp
[16]), SW_REG(fp
[17]), SW_REG(fp
[18]), SW_REG(fp
[19]),
94 SW_REG(fp
[20]), SW_REG(fp
[21]), SW_REG(fp
[22]), SW_REG(fp
[23]),
95 SW_REG(fp
[24]), SW_REG(fp
[25]), SW_REG(fp
[26]), SW_REG(fp
[27]),
96 SW_REG(fp
[28]), SW_REG(fp
[29]), SW_REG(fp
[30]), SW_REG(fp
[31]),
100 static unsigned long zero
;
103 * Get address of register REGNO in task TASK.
105 static unsigned long *
106 get_reg_addr(struct task_struct
* task
, unsigned long regno
)
111 addr
= &task_thread_info(task
)->pcb
.usp
;
112 } else if (regno
== 65) {
113 addr
= &task_thread_info(task
)->pcb
.unique
;
114 } else if (regno
== 31 || regno
> 65) {
118 addr
= task_stack_page(task
) + regoff
[regno
];
124 * Get contents of register REGNO in task TASK.
127 get_reg(struct task_struct
* task
, unsigned long regno
)
129 /* Special hack for fpcr -- combine hardware and software bits. */
131 unsigned long fpcr
= *get_reg_addr(task
, regno
);
133 = task_thread_info(task
)->ieee_state
& IEEE_SW_MASK
;
134 swcr
= swcr_update_status(swcr
, fpcr
);
137 return *get_reg_addr(task
, regno
);
141 * Write contents of register REGNO in task TASK.
144 put_reg(struct task_struct
*task
, unsigned long regno
, unsigned long data
)
147 task_thread_info(task
)->ieee_state
148 = ((task_thread_info(task
)->ieee_state
& ~IEEE_SW_MASK
)
149 | (data
& IEEE_SW_MASK
));
150 data
= (data
& FPCR_DYN_MASK
) | ieee_swcr_to_fpcr(data
);
152 *get_reg_addr(task
, regno
) = data
;
157 read_int(struct task_struct
*task
, unsigned long addr
, int * data
)
159 int copied
= access_process_vm(task
, addr
, data
, sizeof(int), 0);
160 return (copied
== sizeof(int)) ? 0 : -EIO
;
164 write_int(struct task_struct
*task
, unsigned long addr
, int data
)
166 int copied
= access_process_vm(task
, addr
, &data
, sizeof(int), 1);
167 return (copied
== sizeof(int)) ? 0 : -EIO
;
174 ptrace_set_bpt(struct task_struct
* child
)
176 int displ
, i
, res
, reg_b
, nsaved
= 0;
177 unsigned int insn
, op_code
;
180 pc
= get_reg(child
, REG_PC
);
181 res
= read_int(child
, pc
, (int *) &insn
);
185 op_code
= insn
>> 26;
186 if (op_code
>= 0x30) {
188 * It's a branch: instead of trying to figure out
189 * whether the branch will be taken or not, we'll put
190 * a breakpoint at either location. This is simpler,
191 * more reliable, and probably not a whole lot slower
192 * than the alternative approach of emulating the
193 * branch (emulation can be tricky for fp branches).
195 displ
= ((s32
)(insn
<< 11)) >> 9;
196 task_thread_info(child
)->bpt_addr
[nsaved
++] = pc
+ 4;
197 if (displ
) /* guard against unoptimized code */
198 task_thread_info(child
)->bpt_addr
[nsaved
++]
200 DBG(DBG_BPT
, ("execing branch\n"));
201 } else if (op_code
== 0x1a) {
202 reg_b
= (insn
>> 16) & 0x1f;
203 task_thread_info(child
)->bpt_addr
[nsaved
++] = get_reg(child
, reg_b
);
204 DBG(DBG_BPT
, ("execing jump\n"));
206 task_thread_info(child
)->bpt_addr
[nsaved
++] = pc
+ 4;
207 DBG(DBG_BPT
, ("execing normal insn\n"));
210 /* install breakpoints: */
211 for (i
= 0; i
< nsaved
; ++i
) {
212 res
= read_int(child
, task_thread_info(child
)->bpt_addr
[i
],
216 task_thread_info(child
)->bpt_insn
[i
] = insn
;
217 DBG(DBG_BPT
, (" -> next_pc=%lx\n",
218 task_thread_info(child
)->bpt_addr
[i
]));
219 res
= write_int(child
, task_thread_info(child
)->bpt_addr
[i
],
224 task_thread_info(child
)->bpt_nsaved
= nsaved
;
229 * Ensure no single-step breakpoint is pending. Returns non-zero
230 * value if child was being single-stepped.
233 ptrace_cancel_bpt(struct task_struct
* child
)
235 int i
, nsaved
= task_thread_info(child
)->bpt_nsaved
;
237 task_thread_info(child
)->bpt_nsaved
= 0;
240 printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved
);
244 for (i
= 0; i
< nsaved
; ++i
) {
245 write_int(child
, task_thread_info(child
)->bpt_addr
[i
],
246 task_thread_info(child
)->bpt_insn
[i
]);
248 return (nsaved
!= 0);
251 void user_enable_single_step(struct task_struct
*child
)
253 /* Mark single stepping. */
254 task_thread_info(child
)->bpt_nsaved
= -1;
257 void user_disable_single_step(struct task_struct
*child
)
259 ptrace_cancel_bpt(child
);
263 * Called by kernel/ptrace.c when detaching..
265 * Make sure the single step bit is not set.
267 void ptrace_disable(struct task_struct
*child
)
269 user_disable_single_step(child
);
272 long arch_ptrace(struct task_struct
*child
, long request
,
273 unsigned long addr
, unsigned long data
)
280 /* When I and D space are separate, these will need to be fixed. */
281 case PTRACE_PEEKTEXT
: /* read word at location addr. */
282 case PTRACE_PEEKDATA
:
283 copied
= access_process_vm(child
, addr
, &tmp
, sizeof(tmp
), 0);
285 if (copied
!= sizeof(tmp
))
288 force_successful_syscall_return();
292 /* Read register number ADDR. */
294 force_successful_syscall_return();
295 ret
= get_reg(child
, addr
);
296 DBG(DBG_MEM
, ("peek $%lu->%#lx\n", addr
, ret
));
299 /* When I and D space are separate, this will have to be fixed. */
300 case PTRACE_POKETEXT
: /* write the word at location addr. */
301 case PTRACE_POKEDATA
:
302 ret
= generic_ptrace_pokedata(child
, addr
, data
);
305 case PTRACE_POKEUSR
: /* write the specified register */
306 DBG(DBG_MEM
, ("poke $%lu<-%#lx\n", addr
, data
));
307 ret
= put_reg(child
, addr
, data
);
310 ret
= ptrace_request(child
, request
, addr
, data
);
316 asmlinkage
unsigned long syscall_trace_enter(void)
318 unsigned long ret
= 0;
319 if (test_thread_flag(TIF_SYSCALL_TRACE
) &&
320 tracehook_report_syscall_entry(current_pt_regs()))
322 return ret
?: current_pt_regs()->r0
;
326 syscall_trace_leave(void)
328 if (test_thread_flag(TIF_SYSCALL_TRACE
))
329 tracehook_report_syscall_exit(current_pt_regs(), 0);