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i2c: aspeed: Fix initial values of master and slave state
[linux/fpc-iii.git] / drivers / mmc / host / dw_mmc.c
blob80dc2fd6576cf3f88afd695ad1f36ec1b4f52b41
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/of.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
42
43 #include "dw_mmc.h"
44
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
52 DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS 1
54 #define DW_MCI_RECV_STATUS 2
55 #define DW_MCI_DMA_THRESHOLD 16
56
57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 #define DESC_RING_BUF_SZ PAGE_SIZE
66
67 struct idmac_desc_64addr {
68 u32 des0; /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
71
72 u32 des1; /* Reserved */
73
74 u32 des2; /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
78
79 u32 des3; /* Reserved */
80
81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
83
84 u32 des6; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 };
87
88 struct idmac_desc {
89 __le32 des0; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
97
98 __le32 des1; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
101
102 __le32 des2; /* buffer 1 physical address */
103
104 __le32 des3; /* buffer 2 physical address */
105 };
106
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
109
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
112 {
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149 }
150 DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
151
152 static int dw_mci_regs_show(struct seq_file *s, void *v)
153 {
154 struct dw_mci *host = s->private;
155
156 pm_runtime_get_sync(host->dev);
157
158 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
159 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
160 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
161 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
162 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
163 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
164
165 pm_runtime_put_autosuspend(host->dev);
166
167 return 0;
168 }
169 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
170
171 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
172 {
173 struct mmc_host *mmc = slot->mmc;
174 struct dw_mci *host = slot->host;
175 struct dentry *root;
176 struct dentry *node;
177
178 root = mmc->debugfs_root;
179 if (!root)
180 return;
181
182 node = debugfs_create_file("regs", S_IRUSR, root, host,
183 &dw_mci_regs_fops);
184 if (!node)
185 goto err;
186
187 node = debugfs_create_file("req", S_IRUSR, root, slot,
188 &dw_mci_req_fops);
189 if (!node)
190 goto err;
191
192 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
193 if (!node)
194 goto err;
195
196 node = debugfs_create_x32("pending_events", S_IRUSR, root,
197 (u32 *)&host->pending_events);
198 if (!node)
199 goto err;
200
201 node = debugfs_create_x32("completed_events", S_IRUSR, root,
202 (u32 *)&host->completed_events);
203 if (!node)
204 goto err;
205
206 return;
207
208 err:
209 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
210 }
211 #endif /* defined(CONFIG_DEBUG_FS) */
212
213 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
214 {
215 u32 ctrl;
216
217 ctrl = mci_readl(host, CTRL);
218 ctrl |= reset;
219 mci_writel(host, CTRL, ctrl);
220
221 /* wait till resets clear */
222 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
223 !(ctrl & reset),
224 1, 500 * USEC_PER_MSEC)) {
225 dev_err(host->dev,
226 "Timeout resetting block (ctrl reset %#x)\n",
227 ctrl & reset);
228 return false;
229 }
230
231 return true;
232 }
233
234 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
235 {
236 u32 status;
237
238 /*
239 * Databook says that before issuing a new data transfer command
240 * we need to check to see if the card is busy. Data transfer commands
241 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
242 *
243 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
244 * expected.
245 */
246 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
247 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
248 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
249 status,
250 !(status & SDMMC_STATUS_BUSY),
251 10, 500 * USEC_PER_MSEC))
252 dev_err(host->dev, "Busy; trying anyway\n");
253 }
254 }
255
256 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
257 {
258 struct dw_mci *host = slot->host;
259 unsigned int cmd_status = 0;
260
261 mci_writel(host, CMDARG, arg);
262 wmb(); /* drain writebuffer */
263 dw_mci_wait_while_busy(host, cmd);
264 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
265
266 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
267 !(cmd_status & SDMMC_CMD_START),
268 1, 500 * USEC_PER_MSEC))
269 dev_err(&slot->mmc->class_dev,
270 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
271 cmd, arg, cmd_status);
272 }
273
274 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
275 {
276 struct dw_mci_slot *slot = mmc_priv(mmc);
277 struct dw_mci *host = slot->host;
278 u32 cmdr;
279
280 cmd->error = -EINPROGRESS;
281 cmdr = cmd->opcode;
282
283 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
284 cmd->opcode == MMC_GO_IDLE_STATE ||
285 cmd->opcode == MMC_GO_INACTIVE_STATE ||
286 (cmd->opcode == SD_IO_RW_DIRECT &&
287 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
288 cmdr |= SDMMC_CMD_STOP;
289 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
290 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
291
292 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
293 u32 clk_en_a;
294
295 /* Special bit makes CMD11 not die */
296 cmdr |= SDMMC_CMD_VOLT_SWITCH;
297
298 /* Change state to continue to handle CMD11 weirdness */
299 WARN_ON(slot->host->state != STATE_SENDING_CMD);
300 slot->host->state = STATE_SENDING_CMD11;
301
302 /*
303 * We need to disable low power mode (automatic clock stop)
304 * while doing voltage switch so we don't confuse the card,
305 * since stopping the clock is a specific part of the UHS
306 * voltage change dance.
307 *
308 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
309 * unconditionally turned back on in dw_mci_setup_bus() if it's
310 * ever called with a non-zero clock. That shouldn't happen
311 * until the voltage change is all done.
312 */
313 clk_en_a = mci_readl(host, CLKENA);
314 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
315 mci_writel(host, CLKENA, clk_en_a);
316 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
317 SDMMC_CMD_PRV_DAT_WAIT, 0);
318 }
319
320 if (cmd->flags & MMC_RSP_PRESENT) {
321 /* We expect a response, so set this bit */
322 cmdr |= SDMMC_CMD_RESP_EXP;
323 if (cmd->flags & MMC_RSP_136)
324 cmdr |= SDMMC_CMD_RESP_LONG;
325 }
326
327 if (cmd->flags & MMC_RSP_CRC)
328 cmdr |= SDMMC_CMD_RESP_CRC;
329
330 if (cmd->data) {
331 cmdr |= SDMMC_CMD_DAT_EXP;
332 if (cmd->data->flags & MMC_DATA_WRITE)
333 cmdr |= SDMMC_CMD_DAT_WR;
334 }
335
336 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
337 cmdr |= SDMMC_CMD_USE_HOLD_REG;
338
339 return cmdr;
340 }
341
342 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
343 {
344 struct mmc_command *stop;
345 u32 cmdr;
346
347 if (!cmd->data)
348 return 0;
349
350 stop = &host->stop_abort;
351 cmdr = cmd->opcode;
352 memset(stop, 0, sizeof(struct mmc_command));
353
354 if (cmdr == MMC_READ_SINGLE_BLOCK ||
355 cmdr == MMC_READ_MULTIPLE_BLOCK ||
356 cmdr == MMC_WRITE_BLOCK ||
357 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
358 cmdr == MMC_SEND_TUNING_BLOCK ||
359 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
360 stop->opcode = MMC_STOP_TRANSMISSION;
361 stop->arg = 0;
362 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
363 } else if (cmdr == SD_IO_RW_EXTENDED) {
364 stop->opcode = SD_IO_RW_DIRECT;
365 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
366 ((cmd->arg >> 28) & 0x7);
367 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
368 } else {
369 return 0;
370 }
371
372 cmdr = stop->opcode | SDMMC_CMD_STOP |
373 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
374
375 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
376 cmdr |= SDMMC_CMD_USE_HOLD_REG;
377
378 return cmdr;
379 }
380
381 static inline void dw_mci_set_cto(struct dw_mci *host)
382 {
383 unsigned int cto_clks;
384 unsigned int cto_div;
385 unsigned int cto_ms;
386 unsigned long irqflags;
387
388 cto_clks = mci_readl(host, TMOUT) & 0xff;
389 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
390 if (cto_div == 0)
391 cto_div = 1;
392
393 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
394 host->bus_hz);
395
396 /* add a bit spare time */
397 cto_ms += 10;
398
399 /*
400 * The durations we're working with are fairly short so we have to be
401 * extra careful about synchronization here. Specifically in hardware a
402 * command timeout is _at most_ 5.1 ms, so that means we expect an
403 * interrupt (either command done or timeout) to come rather quickly
404 * after the mci_writel. ...but just in case we have a long interrupt
405 * latency let's add a bit of paranoia.
406 *
407 * In general we'll assume that at least an interrupt will be asserted
408 * in hardware by the time the cto_timer runs. ...and if it hasn't
409 * been asserted in hardware by that time then we'll assume it'll never
410 * come.
411 */
412 spin_lock_irqsave(&host->irq_lock, irqflags);
413 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
414 mod_timer(&host->cto_timer,
415 jiffies + msecs_to_jiffies(cto_ms) + 1);
416 spin_unlock_irqrestore(&host->irq_lock, irqflags);
417 }
418
419 static void dw_mci_start_command(struct dw_mci *host,
420 struct mmc_command *cmd, u32 cmd_flags)
421 {
422 host->cmd = cmd;
423 dev_vdbg(host->dev,
424 "start command: ARGR=0x%08x CMDR=0x%08x\n",
425 cmd->arg, cmd_flags);
426
427 mci_writel(host, CMDARG, cmd->arg);
428 wmb(); /* drain writebuffer */
429 dw_mci_wait_while_busy(host, cmd_flags);
430
431 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
432
433 /* response expected command only */
434 if (cmd_flags & SDMMC_CMD_RESP_EXP)
435 dw_mci_set_cto(host);
436 }
437
438 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
439 {
440 struct mmc_command *stop = &host->stop_abort;
441
442 dw_mci_start_command(host, stop, host->stop_cmdr);
443 }
444
445 /* DMA interface functions */
446 static void dw_mci_stop_dma(struct dw_mci *host)
447 {
448 if (host->using_dma) {
449 host->dma_ops->stop(host);
450 host->dma_ops->cleanup(host);
451 }
452
453 /* Data transfer was stopped by the interrupt handler */
454 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
455 }
456
457 static void dw_mci_dma_cleanup(struct dw_mci *host)
458 {
459 struct mmc_data *data = host->data;
460
461 if (data && data->host_cookie == COOKIE_MAPPED) {
462 dma_unmap_sg(host->dev,
463 data->sg,
464 data->sg_len,
465 mmc_get_dma_dir(data));
466 data->host_cookie = COOKIE_UNMAPPED;
467 }
468 }
469
470 static void dw_mci_idmac_reset(struct dw_mci *host)
471 {
472 u32 bmod = mci_readl(host, BMOD);
473 /* Software reset of DMA */
474 bmod |= SDMMC_IDMAC_SWRESET;
475 mci_writel(host, BMOD, bmod);
476 }
477
478 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
479 {
480 u32 temp;
481
482 /* Disable and reset the IDMAC interface */
483 temp = mci_readl(host, CTRL);
484 temp &= ~SDMMC_CTRL_USE_IDMAC;
485 temp |= SDMMC_CTRL_DMA_RESET;
486 mci_writel(host, CTRL, temp);
487
488 /* Stop the IDMAC running */
489 temp = mci_readl(host, BMOD);
490 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
491 temp |= SDMMC_IDMAC_SWRESET;
492 mci_writel(host, BMOD, temp);
493 }
494
495 static void dw_mci_dmac_complete_dma(void *arg)
496 {
497 struct dw_mci *host = arg;
498 struct mmc_data *data = host->data;
499
500 dev_vdbg(host->dev, "DMA complete\n");
501
502 if ((host->use_dma == TRANS_MODE_EDMAC) &&
503 data && (data->flags & MMC_DATA_READ))
504 /* Invalidate cache after read */
505 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
506 data->sg,
507 data->sg_len,
508 DMA_FROM_DEVICE);
509
510 host->dma_ops->cleanup(host);
511
512 /*
513 * If the card was removed, data will be NULL. No point in trying to
514 * send the stop command or waiting for NBUSY in this case.
515 */
516 if (data) {
517 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
518 tasklet_schedule(&host->tasklet);
519 }
520 }
521
522 static int dw_mci_idmac_init(struct dw_mci *host)
523 {
524 int i;
525
526 if (host->dma_64bit_address == 1) {
527 struct idmac_desc_64addr *p;
528 /* Number of descriptors in the ring buffer */
529 host->ring_size =
530 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
531
532 /* Forward link the descriptor list */
533 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
534 i++, p++) {
535 p->des6 = (host->sg_dma +
536 (sizeof(struct idmac_desc_64addr) *
537 (i + 1))) & 0xffffffff;
538
539 p->des7 = (u64)(host->sg_dma +
540 (sizeof(struct idmac_desc_64addr) *
541 (i + 1))) >> 32;
542 /* Initialize reserved and buffer size fields to "0" */
543 p->des0 = 0;
544 p->des1 = 0;
545 p->des2 = 0;
546 p->des3 = 0;
547 }
548
549 /* Set the last descriptor as the end-of-ring descriptor */
550 p->des6 = host->sg_dma & 0xffffffff;
551 p->des7 = (u64)host->sg_dma >> 32;
552 p->des0 = IDMAC_DES0_ER;
553
554 } else {
555 struct idmac_desc *p;
556 /* Number of descriptors in the ring buffer */
557 host->ring_size =
558 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
559
560 /* Forward link the descriptor list */
561 for (i = 0, p = host->sg_cpu;
562 i < host->ring_size - 1;
563 i++, p++) {
564 p->des3 = cpu_to_le32(host->sg_dma +
565 (sizeof(struct idmac_desc) * (i + 1)));
566 p->des0 = 0;
567 p->des1 = 0;
568 }
569
570 /* Set the last descriptor as the end-of-ring descriptor */
571 p->des3 = cpu_to_le32(host->sg_dma);
572 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
573 }
574
575 dw_mci_idmac_reset(host);
576
577 if (host->dma_64bit_address == 1) {
578 /* Mask out interrupts - get Tx & Rx complete only */
579 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
580 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
581 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
582
583 /* Set the descriptor base address */
584 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
585 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
586
587 } else {
588 /* Mask out interrupts - get Tx & Rx complete only */
589 mci_writel(host, IDSTS, IDMAC_INT_CLR);
590 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
591 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
592
593 /* Set the descriptor base address */
594 mci_writel(host, DBADDR, host->sg_dma);
595 }
596
597 return 0;
598 }
599
600 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
601 struct mmc_data *data,
602 unsigned int sg_len)
603 {
604 unsigned int desc_len;
605 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
606 u32 val;
607 int i;
608
609 desc_first = desc_last = desc = host->sg_cpu;
610
611 for (i = 0; i < sg_len; i++) {
612 unsigned int length = sg_dma_len(&data->sg[i]);
613
614 u64 mem_addr = sg_dma_address(&data->sg[i]);
615
616 for ( ; length ; desc++) {
617 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
618 length : DW_MCI_DESC_DATA_LENGTH;
619
620 length -= desc_len;
621
622 /*
623 * Wait for the former clear OWN bit operation
624 * of IDMAC to make sure that this descriptor
625 * isn't still owned by IDMAC as IDMAC's write
626 * ops and CPU's read ops are asynchronous.
627 */
628 if (readl_poll_timeout_atomic(&desc->des0, val,
629 !(val & IDMAC_DES0_OWN),
630 10, 100 * USEC_PER_MSEC))
631 goto err_own_bit;
632
633 /*
634 * Set the OWN bit and disable interrupts
635 * for this descriptor
636 */
637 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
638 IDMAC_DES0_CH;
639
640 /* Buffer length */
641 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
642
643 /* Physical address to DMA to/from */
644 desc->des4 = mem_addr & 0xffffffff;
645 desc->des5 = mem_addr >> 32;
646
647 /* Update physical address for the next desc */
648 mem_addr += desc_len;
649
650 /* Save pointer to the last descriptor */
651 desc_last = desc;
652 }
653 }
654
655 /* Set first descriptor */
656 desc_first->des0 |= IDMAC_DES0_FD;
657
658 /* Set last descriptor */
659 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
660 desc_last->des0 |= IDMAC_DES0_LD;
661
662 return 0;
663 err_own_bit:
664 /* restore the descriptor chain as it's polluted */
665 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
666 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
667 dw_mci_idmac_init(host);
668 return -EINVAL;
669 }
670
671
672 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
673 struct mmc_data *data,
674 unsigned int sg_len)
675 {
676 unsigned int desc_len;
677 struct idmac_desc *desc_first, *desc_last, *desc;
678 u32 val;
679 int i;
680
681 desc_first = desc_last = desc = host->sg_cpu;
682
683 for (i = 0; i < sg_len; i++) {
684 unsigned int length = sg_dma_len(&data->sg[i]);
685
686 u32 mem_addr = sg_dma_address(&data->sg[i]);
687
688 for ( ; length ; desc++) {
689 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
690 length : DW_MCI_DESC_DATA_LENGTH;
691
692 length -= desc_len;
693
694 /*
695 * Wait for the former clear OWN bit operation
696 * of IDMAC to make sure that this descriptor
697 * isn't still owned by IDMAC as IDMAC's write
698 * ops and CPU's read ops are asynchronous.
699 */
700 if (readl_poll_timeout_atomic(&desc->des0, val,
701 IDMAC_OWN_CLR64(val),
702 10,
703 100 * USEC_PER_MSEC))
704 goto err_own_bit;
705
706 /*
707 * Set the OWN bit and disable interrupts
708 * for this descriptor
709 */
710 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
711 IDMAC_DES0_DIC |
712 IDMAC_DES0_CH);
713
714 /* Buffer length */
715 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
716
717 /* Physical address to DMA to/from */
718 desc->des2 = cpu_to_le32(mem_addr);
719
720 /* Update physical address for the next desc */
721 mem_addr += desc_len;
722
723 /* Save pointer to the last descriptor */
724 desc_last = desc;
725 }
726 }
727
728 /* Set first descriptor */
729 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
730
731 /* Set last descriptor */
732 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
733 IDMAC_DES0_DIC));
734 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
735
736 return 0;
737 err_own_bit:
738 /* restore the descriptor chain as it's polluted */
739 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
740 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
741 dw_mci_idmac_init(host);
742 return -EINVAL;
743 }
744
745 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
746 {
747 u32 temp;
748 int ret;
749
750 if (host->dma_64bit_address == 1)
751 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
752 else
753 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
754
755 if (ret)
756 goto out;
757
758 /* drain writebuffer */
759 wmb();
760
761 /* Make sure to reset DMA in case we did PIO before this */
762 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
763 dw_mci_idmac_reset(host);
764
765 /* Select IDMAC interface */
766 temp = mci_readl(host, CTRL);
767 temp |= SDMMC_CTRL_USE_IDMAC;
768 mci_writel(host, CTRL, temp);
769
770 /* drain writebuffer */
771 wmb();
772
773 /* Enable the IDMAC */
774 temp = mci_readl(host, BMOD);
775 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
776 mci_writel(host, BMOD, temp);
777
778 /* Start it running */
779 mci_writel(host, PLDMND, 1);
780
781 out:
782 return ret;
783 }
784
785 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
786 .init = dw_mci_idmac_init,
787 .start = dw_mci_idmac_start_dma,
788 .stop = dw_mci_idmac_stop_dma,
789 .complete = dw_mci_dmac_complete_dma,
790 .cleanup = dw_mci_dma_cleanup,
791 };
792
793 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
794 {
795 dmaengine_terminate_async(host->dms->ch);
796 }
797
798 static int dw_mci_edmac_start_dma(struct dw_mci *host,
799 unsigned int sg_len)
800 {
801 struct dma_slave_config cfg;
802 struct dma_async_tx_descriptor *desc = NULL;
803 struct scatterlist *sgl = host->data->sg;
804 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
805 u32 sg_elems = host->data->sg_len;
806 u32 fifoth_val;
807 u32 fifo_offset = host->fifo_reg - host->regs;
808 int ret = 0;
809
810 /* Set external dma config: burst size, burst width */
811 cfg.dst_addr = host->phy_regs + fifo_offset;
812 cfg.src_addr = cfg.dst_addr;
813 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
814 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
815
816 /* Match burst msize with external dma config */
817 fifoth_val = mci_readl(host, FIFOTH);
818 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
819 cfg.src_maxburst = cfg.dst_maxburst;
820
821 if (host->data->flags & MMC_DATA_WRITE)
822 cfg.direction = DMA_MEM_TO_DEV;
823 else
824 cfg.direction = DMA_DEV_TO_MEM;
825
826 ret = dmaengine_slave_config(host->dms->ch, &cfg);
827 if (ret) {
828 dev_err(host->dev, "Failed to config edmac.\n");
829 return -EBUSY;
830 }
831
832 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
833 sg_len, cfg.direction,
834 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
835 if (!desc) {
836 dev_err(host->dev, "Can't prepare slave sg.\n");
837 return -EBUSY;
838 }
839
840 /* Set dw_mci_dmac_complete_dma as callback */
841 desc->callback = dw_mci_dmac_complete_dma;
842 desc->callback_param = (void *)host;
843 dmaengine_submit(desc);
844
845 /* Flush cache before write */
846 if (host->data->flags & MMC_DATA_WRITE)
847 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
848 sg_elems, DMA_TO_DEVICE);
849
850 dma_async_issue_pending(host->dms->ch);
851
852 return 0;
853 }
854
855 static int dw_mci_edmac_init(struct dw_mci *host)
856 {
857 /* Request external dma channel */
858 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
859 if (!host->dms)
860 return -ENOMEM;
861
862 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
863 if (!host->dms->ch) {
864 dev_err(host->dev, "Failed to get external DMA channel.\n");
865 kfree(host->dms);
866 host->dms = NULL;
867 return -ENXIO;
868 }
869
870 return 0;
871 }
872
873 static void dw_mci_edmac_exit(struct dw_mci *host)
874 {
875 if (host->dms) {
876 if (host->dms->ch) {
877 dma_release_channel(host->dms->ch);
878 host->dms->ch = NULL;
879 }
880 kfree(host->dms);
881 host->dms = NULL;
882 }
883 }
884
885 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
886 .init = dw_mci_edmac_init,
887 .exit = dw_mci_edmac_exit,
888 .start = dw_mci_edmac_start_dma,
889 .stop = dw_mci_edmac_stop_dma,
890 .complete = dw_mci_dmac_complete_dma,
891 .cleanup = dw_mci_dma_cleanup,
892 };
893
894 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
895 struct mmc_data *data,
896 int cookie)
897 {
898 struct scatterlist *sg;
899 unsigned int i, sg_len;
900
901 if (data->host_cookie == COOKIE_PRE_MAPPED)
902 return data->sg_len;
903
904 /*
905 * We don't do DMA on "complex" transfers, i.e. with
906 * non-word-aligned buffers or lengths. Also, we don't bother
907 * with all the DMA setup overhead for short transfers.
908 */
909 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
910 return -EINVAL;
911
912 if (data->blksz & 3)
913 return -EINVAL;
914
915 for_each_sg(data->sg, sg, data->sg_len, i) {
916 if (sg->offset & 3 || sg->length & 3)
917 return -EINVAL;
918 }
919
920 sg_len = dma_map_sg(host->dev,
921 data->sg,
922 data->sg_len,
923 mmc_get_dma_dir(data));
924 if (sg_len == 0)
925 return -EINVAL;
926
927 data->host_cookie = cookie;
928
929 return sg_len;
930 }
931
932 static void dw_mci_pre_req(struct mmc_host *mmc,
933 struct mmc_request *mrq)
934 {
935 struct dw_mci_slot *slot = mmc_priv(mmc);
936 struct mmc_data *data = mrq->data;
937
938 if (!slot->host->use_dma || !data)
939 return;
940
941 /* This data might be unmapped at this time */
942 data->host_cookie = COOKIE_UNMAPPED;
943
944 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
945 COOKIE_PRE_MAPPED) < 0)
946 data->host_cookie = COOKIE_UNMAPPED;
947 }
948
949 static void dw_mci_post_req(struct mmc_host *mmc,
950 struct mmc_request *mrq,
951 int err)
952 {
953 struct dw_mci_slot *slot = mmc_priv(mmc);
954 struct mmc_data *data = mrq->data;
955
956 if (!slot->host->use_dma || !data)
957 return;
958
959 if (data->host_cookie != COOKIE_UNMAPPED)
960 dma_unmap_sg(slot->host->dev,
961 data->sg,
962 data->sg_len,
963 mmc_get_dma_dir(data));
964 data->host_cookie = COOKIE_UNMAPPED;
965 }
966
967 static int dw_mci_get_cd(struct mmc_host *mmc)
968 {
969 int present;
970 struct dw_mci_slot *slot = mmc_priv(mmc);
971 struct dw_mci *host = slot->host;
972 int gpio_cd = mmc_gpio_get_cd(mmc);
973
974 /* Use platform get_cd function, else try onboard card detect */
975 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
976 || !mmc_card_is_removable(mmc))) {
977 present = 1;
978
979 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
980 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
981 dev_info(&mmc->class_dev,
982 "card is polling.\n");
983 } else {
984 dev_info(&mmc->class_dev,
985 "card is non-removable.\n");
986 }
987 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
988 }
989
990 return present;
991 } else if (gpio_cd >= 0)
992 present = gpio_cd;
993 else
994 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
995 == 0 ? 1 : 0;
996
997 spin_lock_bh(&host->lock);
998 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
999 dev_dbg(&mmc->class_dev, "card is present\n");
1000 else if (!present &&
1001 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1002 dev_dbg(&mmc->class_dev, "card is not present\n");
1003 spin_unlock_bh(&host->lock);
1004
1005 return present;
1006 }
1007
1008 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1009 {
1010 unsigned int blksz = data->blksz;
1011 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1012 u32 fifo_width = 1 << host->data_shift;
1013 u32 blksz_depth = blksz / fifo_width, fifoth_val;
1014 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1015 int idx = ARRAY_SIZE(mszs) - 1;
1016
1017 /* pio should ship this scenario */
1018 if (!host->use_dma)
1019 return;
1020
1021 tx_wmark = (host->fifo_depth) / 2;
1022 tx_wmark_invers = host->fifo_depth - tx_wmark;
1023
1024 /*
1025 * MSIZE is '1',
1026 * if blksz is not a multiple of the FIFO width
1027 */
1028 if (blksz % fifo_width)
1029 goto done;
1030
1031 do {
1032 if (!((blksz_depth % mszs[idx]) ||
1033 (tx_wmark_invers % mszs[idx]))) {
1034 msize = idx;
1035 rx_wmark = mszs[idx] - 1;
1036 break;
1037 }
1038 } while (--idx > 0);
1039 /*
1040 * If idx is '0', it won't be tried
1041 * Thus, initial values are uesed
1042 */
1043 done:
1044 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1045 mci_writel(host, FIFOTH, fifoth_val);
1046 }
1047
1048 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1049 {
1050 unsigned int blksz = data->blksz;
1051 u32 blksz_depth, fifo_depth;
1052 u16 thld_size;
1053 u8 enable;
1054
1055 /*
1056 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1057 * in the FIFO region, so we really shouldn't access it).
1058 */
1059 if (host->verid < DW_MMC_240A ||
1060 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1061 return;
1062
1063 /*
1064 * Card write Threshold is introduced since 2.80a
1065 * It's used when HS400 mode is enabled.
1066 */
1067 if (data->flags & MMC_DATA_WRITE &&
1068 host->timing != MMC_TIMING_MMC_HS400)
1069 goto disable;
1070
1071 if (data->flags & MMC_DATA_WRITE)
1072 enable = SDMMC_CARD_WR_THR_EN;
1073 else
1074 enable = SDMMC_CARD_RD_THR_EN;
1075
1076 if (host->timing != MMC_TIMING_MMC_HS200 &&
1077 host->timing != MMC_TIMING_UHS_SDR104 &&
1078 host->timing != MMC_TIMING_MMC_HS400)
1079 goto disable;
1080
1081 blksz_depth = blksz / (1 << host->data_shift);
1082 fifo_depth = host->fifo_depth;
1083
1084 if (blksz_depth > fifo_depth)
1085 goto disable;
1086
1087 /*
1088 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1089 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1090 * Currently just choose blksz.
1091 */
1092 thld_size = blksz;
1093 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1094 return;
1095
1096 disable:
1097 mci_writel(host, CDTHRCTL, 0);
1098 }
1099
1100 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1101 {
1102 unsigned long irqflags;
1103 int sg_len;
1104 u32 temp;
1105
1106 host->using_dma = 0;
1107
1108 /* If we don't have a channel, we can't do DMA */
1109 if (!host->use_dma)
1110 return -ENODEV;
1111
1112 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1113 if (sg_len < 0) {
1114 host->dma_ops->stop(host);
1115 return sg_len;
1116 }
1117
1118 host->using_dma = 1;
1119
1120 if (host->use_dma == TRANS_MODE_IDMAC)
1121 dev_vdbg(host->dev,
1122 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1123 (unsigned long)host->sg_cpu,
1124 (unsigned long)host->sg_dma,
1125 sg_len);
1126
1127 /*
1128 * Decide the MSIZE and RX/TX Watermark.
1129 * If current block size is same with previous size,
1130 * no need to update fifoth.
1131 */
1132 if (host->prev_blksz != data->blksz)
1133 dw_mci_adjust_fifoth(host, data);
1134
1135 /* Enable the DMA interface */
1136 temp = mci_readl(host, CTRL);
1137 temp |= SDMMC_CTRL_DMA_ENABLE;
1138 mci_writel(host, CTRL, temp);
1139
1140 /* Disable RX/TX IRQs, let DMA handle it */
1141 spin_lock_irqsave(&host->irq_lock, irqflags);
1142 temp = mci_readl(host, INTMASK);
1143 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1144 mci_writel(host, INTMASK, temp);
1145 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1146
1147 if (host->dma_ops->start(host, sg_len)) {
1148 host->dma_ops->stop(host);
1149 /* We can't do DMA, try PIO for this one */
1150 dev_dbg(host->dev,
1151 "%s: fall back to PIO mode for current transfer\n",
1152 __func__);
1153 return -ENODEV;
1154 }
1155
1156 return 0;
1157 }
1158
1159 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1160 {
1161 unsigned long irqflags;
1162 int flags = SG_MITER_ATOMIC;
1163 u32 temp;
1164
1165 data->error = -EINPROGRESS;
1166
1167 WARN_ON(host->data);
1168 host->sg = NULL;
1169 host->data = data;
1170
1171 if (data->flags & MMC_DATA_READ)
1172 host->dir_status = DW_MCI_RECV_STATUS;
1173 else
1174 host->dir_status = DW_MCI_SEND_STATUS;
1175
1176 dw_mci_ctrl_thld(host, data);
1177
1178 if (dw_mci_submit_data_dma(host, data)) {
1179 if (host->data->flags & MMC_DATA_READ)
1180 flags |= SG_MITER_TO_SG;
1181 else
1182 flags |= SG_MITER_FROM_SG;
1183
1184 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1185 host->sg = data->sg;
1186 host->part_buf_start = 0;
1187 host->part_buf_count = 0;
1188
1189 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1190
1191 spin_lock_irqsave(&host->irq_lock, irqflags);
1192 temp = mci_readl(host, INTMASK);
1193 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1194 mci_writel(host, INTMASK, temp);
1195 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1196
1197 temp = mci_readl(host, CTRL);
1198 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1199 mci_writel(host, CTRL, temp);
1200
1201 /*
1202 * Use the initial fifoth_val for PIO mode. If wm_algined
1203 * is set, we set watermark same as data size.
1204 * If next issued data may be transfered by DMA mode,
1205 * prev_blksz should be invalidated.
1206 */
1207 if (host->wm_aligned)
1208 dw_mci_adjust_fifoth(host, data);
1209 else
1210 mci_writel(host, FIFOTH, host->fifoth_val);
1211 host->prev_blksz = 0;
1212 } else {
1213 /*
1214 * Keep the current block size.
1215 * It will be used to decide whether to update
1216 * fifoth register next time.
1217 */
1218 host->prev_blksz = data->blksz;
1219 }
1220 }
1221
1222 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1223 {
1224 struct dw_mci *host = slot->host;
1225 unsigned int clock = slot->clock;
1226 u32 div;
1227 u32 clk_en_a;
1228 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1229
1230 /* We must continue to set bit 28 in CMD until the change is complete */
1231 if (host->state == STATE_WAITING_CMD11_DONE)
1232 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1233
1234 slot->mmc->actual_clock = 0;
1235
1236 if (!clock) {
1237 mci_writel(host, CLKENA, 0);
1238 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1239 } else if (clock != host->current_speed || force_clkinit) {
1240 div = host->bus_hz / clock;
1241 if (host->bus_hz % clock && host->bus_hz > clock)
1242 /*
1243 * move the + 1 after the divide to prevent
1244 * over-clocking the card.
1245 */
1246 div += 1;
1247
1248 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1249
1250 if ((clock != slot->__clk_old &&
1251 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1252 force_clkinit) {
1253 /* Silent the verbose log if calling from PM context */
1254 if (!force_clkinit)
1255 dev_info(&slot->mmc->class_dev,
1256 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1257 slot->id, host->bus_hz, clock,
1258 div ? ((host->bus_hz / div) >> 1) :
1259 host->bus_hz, div);
1260
1261 /*
1262 * If card is polling, display the message only
1263 * one time at boot time.
1264 */
1265 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1266 slot->mmc->f_min == clock)
1267 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1268 }
1269
1270 /* disable clock */
1271 mci_writel(host, CLKENA, 0);
1272 mci_writel(host, CLKSRC, 0);
1273
1274 /* inform CIU */
1275 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1276
1277 /* set clock to desired speed */
1278 mci_writel(host, CLKDIV, div);
1279
1280 /* inform CIU */
1281 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1282
1283 /* enable clock; only low power if no SDIO */
1284 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1285 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1286 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1287 mci_writel(host, CLKENA, clk_en_a);
1288
1289 /* inform CIU */
1290 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1291
1292 /* keep the last clock value that was requested from core */
1293 slot->__clk_old = clock;
1294 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1295 host->bus_hz;
1296 }
1297
1298 host->current_speed = clock;
1299
1300 /* Set the current slot bus width */
1301 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1302 }
1303
1304 static void __dw_mci_start_request(struct dw_mci *host,
1305 struct dw_mci_slot *slot,
1306 struct mmc_command *cmd)
1307 {
1308 struct mmc_request *mrq;
1309 struct mmc_data *data;
1310 u32 cmdflags;
1311
1312 mrq = slot->mrq;
1313
1314 host->mrq = mrq;
1315
1316 host->pending_events = 0;
1317 host->completed_events = 0;
1318 host->cmd_status = 0;
1319 host->data_status = 0;
1320 host->dir_status = 0;
1321
1322 data = cmd->data;
1323 if (data) {
1324 mci_writel(host, TMOUT, 0xFFFFFFFF);
1325 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1326 mci_writel(host, BLKSIZ, data->blksz);
1327 }
1328
1329 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1330
1331 /* this is the first command, send the initialization clock */
1332 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1333 cmdflags |= SDMMC_CMD_INIT;
1334
1335 if (data) {
1336 dw_mci_submit_data(host, data);
1337 wmb(); /* drain writebuffer */
1338 }
1339
1340 dw_mci_start_command(host, cmd, cmdflags);
1341
1342 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1343 unsigned long irqflags;
1344
1345 /*
1346 * Databook says to fail after 2ms w/ no response, but evidence
1347 * shows that sometimes the cmd11 interrupt takes over 130ms.
1348 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1349 * is just about to roll over.
1350 *
1351 * We do this whole thing under spinlock and only if the
1352 * command hasn't already completed (indicating the the irq
1353 * already ran so we don't want the timeout).
1354 */
1355 spin_lock_irqsave(&host->irq_lock, irqflags);
1356 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1357 mod_timer(&host->cmd11_timer,
1358 jiffies + msecs_to_jiffies(500) + 1);
1359 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1360 }
1361
1362 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1363 }
1364
1365 static void dw_mci_start_request(struct dw_mci *host,
1366 struct dw_mci_slot *slot)
1367 {
1368 struct mmc_request *mrq = slot->mrq;
1369 struct mmc_command *cmd;
1370
1371 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1372 __dw_mci_start_request(host, slot, cmd);
1373 }
1374
1375 /* must be called with host->lock held */
1376 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1377 struct mmc_request *mrq)
1378 {
1379 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1380 host->state);
1381
1382 slot->mrq = mrq;
1383
1384 if (host->state == STATE_WAITING_CMD11_DONE) {
1385 dev_warn(&slot->mmc->class_dev,
1386 "Voltage change didn't complete\n");
1387 /*
1388 * this case isn't expected to happen, so we can
1389 * either crash here or just try to continue on
1390 * in the closest possible state
1391 */
1392 host->state = STATE_IDLE;
1393 }
1394
1395 if (host->state == STATE_IDLE) {
1396 host->state = STATE_SENDING_CMD;
1397 dw_mci_start_request(host, slot);
1398 } else {
1399 list_add_tail(&slot->queue_node, &host->queue);
1400 }
1401 }
1402
1403 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1404 {
1405 struct dw_mci_slot *slot = mmc_priv(mmc);
1406 struct dw_mci *host = slot->host;
1407
1408 WARN_ON(slot->mrq);
1409
1410 /*
1411 * The check for card presence and queueing of the request must be
1412 * atomic, otherwise the card could be removed in between and the
1413 * request wouldn't fail until another card was inserted.
1414 */
1415
1416 if (!dw_mci_get_cd(mmc)) {
1417 mrq->cmd->error = -ENOMEDIUM;
1418 mmc_request_done(mmc, mrq);
1419 return;
1420 }
1421
1422 spin_lock_bh(&host->lock);
1423
1424 dw_mci_queue_request(host, slot, mrq);
1425
1426 spin_unlock_bh(&host->lock);
1427 }
1428
1429 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1430 {
1431 struct dw_mci_slot *slot = mmc_priv(mmc);
1432 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1433 u32 regs;
1434 int ret;
1435
1436 switch (ios->bus_width) {
1437 case MMC_BUS_WIDTH_4:
1438 slot->ctype = SDMMC_CTYPE_4BIT;
1439 break;
1440 case MMC_BUS_WIDTH_8:
1441 slot->ctype = SDMMC_CTYPE_8BIT;
1442 break;
1443 default:
1444 /* set default 1 bit mode */
1445 slot->ctype = SDMMC_CTYPE_1BIT;
1446 }
1447
1448 regs = mci_readl(slot->host, UHS_REG);
1449
1450 /* DDR mode set */
1451 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1452 ios->timing == MMC_TIMING_UHS_DDR50 ||
1453 ios->timing == MMC_TIMING_MMC_HS400)
1454 regs |= ((0x1 << slot->id) << 16);
1455 else
1456 regs &= ~((0x1 << slot->id) << 16);
1457
1458 mci_writel(slot->host, UHS_REG, regs);
1459 slot->host->timing = ios->timing;
1460
1461 /*
1462 * Use mirror of ios->clock to prevent race with mmc
1463 * core ios update when finding the minimum.
1464 */
1465 slot->clock = ios->clock;
1466
1467 if (drv_data && drv_data->set_ios)
1468 drv_data->set_ios(slot->host, ios);
1469
1470 switch (ios->power_mode) {
1471 case MMC_POWER_UP:
1472 if (!IS_ERR(mmc->supply.vmmc)) {
1473 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1474 ios->vdd);
1475 if (ret) {
1476 dev_err(slot->host->dev,
1477 "failed to enable vmmc regulator\n");
1478 /*return, if failed turn on vmmc*/
1479 return;
1480 }
1481 }
1482 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1483 regs = mci_readl(slot->host, PWREN);
1484 regs |= (1 << slot->id);
1485 mci_writel(slot->host, PWREN, regs);
1486 break;
1487 case MMC_POWER_ON:
1488 if (!slot->host->vqmmc_enabled) {
1489 if (!IS_ERR(mmc->supply.vqmmc)) {
1490 ret = regulator_enable(mmc->supply.vqmmc);
1491 if (ret < 0)
1492 dev_err(slot->host->dev,
1493 "failed to enable vqmmc\n");
1494 else
1495 slot->host->vqmmc_enabled = true;
1496
1497 } else {
1498 /* Keep track so we don't reset again */
1499 slot->host->vqmmc_enabled = true;
1500 }
1501
1502 /* Reset our state machine after powering on */
1503 dw_mci_ctrl_reset(slot->host,
1504 SDMMC_CTRL_ALL_RESET_FLAGS);
1505 }
1506
1507 /* Adjust clock / bus width after power is up */
1508 dw_mci_setup_bus(slot, false);
1509
1510 break;
1511 case MMC_POWER_OFF:
1512 /* Turn clock off before power goes down */
1513 dw_mci_setup_bus(slot, false);
1514
1515 if (!IS_ERR(mmc->supply.vmmc))
1516 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1517
1518 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1519 regulator_disable(mmc->supply.vqmmc);
1520 slot->host->vqmmc_enabled = false;
1521
1522 regs = mci_readl(slot->host, PWREN);
1523 regs &= ~(1 << slot->id);
1524 mci_writel(slot->host, PWREN, regs);
1525 break;
1526 default:
1527 break;
1528 }
1529
1530 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1531 slot->host->state = STATE_IDLE;
1532 }
1533
1534 static int dw_mci_card_busy(struct mmc_host *mmc)
1535 {
1536 struct dw_mci_slot *slot = mmc_priv(mmc);
1537 u32 status;
1538
1539 /*
1540 * Check the busy bit which is low when DAT[3:0]
1541 * (the data lines) are 0000
1542 */
1543 status = mci_readl(slot->host, STATUS);
1544
1545 return !!(status & SDMMC_STATUS_BUSY);
1546 }
1547
1548 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1549 {
1550 struct dw_mci_slot *slot = mmc_priv(mmc);
1551 struct dw_mci *host = slot->host;
1552 const struct dw_mci_drv_data *drv_data = host->drv_data;
1553 u32 uhs;
1554 u32 v18 = SDMMC_UHS_18V << slot->id;
1555 int ret;
1556
1557 if (drv_data && drv_data->switch_voltage)
1558 return drv_data->switch_voltage(mmc, ios);
1559
1560 /*
1561 * Program the voltage. Note that some instances of dw_mmc may use
1562 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1563 * does no harm but you need to set the regulator directly. Try both.
1564 */
1565 uhs = mci_readl(host, UHS_REG);
1566 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1567 uhs &= ~v18;
1568 else
1569 uhs |= v18;
1570
1571 if (!IS_ERR(mmc->supply.vqmmc)) {
1572 ret = mmc_regulator_set_vqmmc(mmc, ios);
1573
1574 if (ret) {
1575 dev_dbg(&mmc->class_dev,
1576 "Regulator set error %d - %s V\n",
1577 ret, uhs & v18 ? "1.8" : "3.3");
1578 return ret;
1579 }
1580 }
1581 mci_writel(host, UHS_REG, uhs);
1582
1583 return 0;
1584 }
1585
1586 static int dw_mci_get_ro(struct mmc_host *mmc)
1587 {
1588 int read_only;
1589 struct dw_mci_slot *slot = mmc_priv(mmc);
1590 int gpio_ro = mmc_gpio_get_ro(mmc);
1591
1592 /* Use platform get_ro function, else try on board write protect */
1593 if (gpio_ro >= 0)
1594 read_only = gpio_ro;
1595 else
1596 read_only =
1597 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1598
1599 dev_dbg(&mmc->class_dev, "card is %s\n",
1600 read_only ? "read-only" : "read-write");
1601
1602 return read_only;
1603 }
1604
1605 static void dw_mci_hw_reset(struct mmc_host *mmc)
1606 {
1607 struct dw_mci_slot *slot = mmc_priv(mmc);
1608 struct dw_mci *host = slot->host;
1609 int reset;
1610
1611 if (host->use_dma == TRANS_MODE_IDMAC)
1612 dw_mci_idmac_reset(host);
1613
1614 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1615 SDMMC_CTRL_FIFO_RESET))
1616 return;
1617
1618 /*
1619 * According to eMMC spec, card reset procedure:
1620 * tRstW >= 1us: RST_n pulse width
1621 * tRSCA >= 200us: RST_n to Command time
1622 * tRSTH >= 1us: RST_n high period
1623 */
1624 reset = mci_readl(host, RST_N);
1625 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1626 mci_writel(host, RST_N, reset);
1627 usleep_range(1, 2);
1628 reset |= SDMMC_RST_HWACTIVE << slot->id;
1629 mci_writel(host, RST_N, reset);
1630 usleep_range(200, 300);
1631 }
1632
1633 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1634 {
1635 struct dw_mci_slot *slot = mmc_priv(mmc);
1636 struct dw_mci *host = slot->host;
1637
1638 /*
1639 * Low power mode will stop the card clock when idle. According to the
1640 * description of the CLKENA register we should disable low power mode
1641 * for SDIO cards if we need SDIO interrupts to work.
1642 */
1643 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1644 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1645 u32 clk_en_a_old;
1646 u32 clk_en_a;
1647
1648 clk_en_a_old = mci_readl(host, CLKENA);
1649
1650 if (card->type == MMC_TYPE_SDIO ||
1651 card->type == MMC_TYPE_SD_COMBO) {
1652 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1653 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1654 } else {
1655 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1656 clk_en_a = clk_en_a_old | clken_low_pwr;
1657 }
1658
1659 if (clk_en_a != clk_en_a_old) {
1660 mci_writel(host, CLKENA, clk_en_a);
1661 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1662 SDMMC_CMD_PRV_DAT_WAIT, 0);
1663 }
1664 }
1665 }
1666
1667 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1668 {
1669 struct dw_mci *host = slot->host;
1670 unsigned long irqflags;
1671 u32 int_mask;
1672
1673 spin_lock_irqsave(&host->irq_lock, irqflags);
1674
1675 /* Enable/disable Slot Specific SDIO interrupt */
1676 int_mask = mci_readl(host, INTMASK);
1677 if (enb)
1678 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1679 else
1680 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1681 mci_writel(host, INTMASK, int_mask);
1682
1683 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1684 }
1685
1686 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1687 {
1688 struct dw_mci_slot *slot = mmc_priv(mmc);
1689 struct dw_mci *host = slot->host;
1690
1691 __dw_mci_enable_sdio_irq(slot, enb);
1692
1693 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1694 if (enb)
1695 pm_runtime_get_noresume(host->dev);
1696 else
1697 pm_runtime_put_noidle(host->dev);
1698 }
1699
1700 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1701 {
1702 struct dw_mci_slot *slot = mmc_priv(mmc);
1703
1704 __dw_mci_enable_sdio_irq(slot, 1);
1705 }
1706
1707 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1708 {
1709 struct dw_mci_slot *slot = mmc_priv(mmc);
1710 struct dw_mci *host = slot->host;
1711 const struct dw_mci_drv_data *drv_data = host->drv_data;
1712 int err = -EINVAL;
1713
1714 if (drv_data && drv_data->execute_tuning)
1715 err = drv_data->execute_tuning(slot, opcode);
1716 return err;
1717 }
1718
1719 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1720 struct mmc_ios *ios)
1721 {
1722 struct dw_mci_slot *slot = mmc_priv(mmc);
1723 struct dw_mci *host = slot->host;
1724 const struct dw_mci_drv_data *drv_data = host->drv_data;
1725
1726 if (drv_data && drv_data->prepare_hs400_tuning)
1727 return drv_data->prepare_hs400_tuning(host, ios);
1728
1729 return 0;
1730 }
1731
1732 static bool dw_mci_reset(struct dw_mci *host)
1733 {
1734 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1735 bool ret = false;
1736 u32 status = 0;
1737
1738 /*
1739 * Resetting generates a block interrupt, hence setting
1740 * the scatter-gather pointer to NULL.
1741 */
1742 if (host->sg) {
1743 sg_miter_stop(&host->sg_miter);
1744 host->sg = NULL;
1745 }
1746
1747 if (host->use_dma)
1748 flags |= SDMMC_CTRL_DMA_RESET;
1749
1750 if (dw_mci_ctrl_reset(host, flags)) {
1751 /*
1752 * In all cases we clear the RAWINTS
1753 * register to clear any interrupts.
1754 */
1755 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1756
1757 if (!host->use_dma) {
1758 ret = true;
1759 goto ciu_out;
1760 }
1761
1762 /* Wait for dma_req to be cleared */
1763 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1764 status,
1765 !(status & SDMMC_STATUS_DMA_REQ),
1766 1, 500 * USEC_PER_MSEC)) {
1767 dev_err(host->dev,
1768 "%s: Timeout waiting for dma_req to be cleared\n",
1769 __func__);
1770 goto ciu_out;
1771 }
1772
1773 /* when using DMA next we reset the fifo again */
1774 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1775 goto ciu_out;
1776 } else {
1777 /* if the controller reset bit did clear, then set clock regs */
1778 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1779 dev_err(host->dev,
1780 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1781 __func__);
1782 goto ciu_out;
1783 }
1784 }
1785
1786 if (host->use_dma == TRANS_MODE_IDMAC)
1787 /* It is also required that we reinit idmac */
1788 dw_mci_idmac_init(host);
1789
1790 ret = true;
1791
1792 ciu_out:
1793 /* After a CTRL reset we need to have CIU set clock registers */
1794 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1795
1796 return ret;
1797 }
1798
1799 static const struct mmc_host_ops dw_mci_ops = {
1800 .request = dw_mci_request,
1801 .pre_req = dw_mci_pre_req,
1802 .post_req = dw_mci_post_req,
1803 .set_ios = dw_mci_set_ios,
1804 .get_ro = dw_mci_get_ro,
1805 .get_cd = dw_mci_get_cd,
1806 .hw_reset = dw_mci_hw_reset,
1807 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1808 .ack_sdio_irq = dw_mci_ack_sdio_irq,
1809 .execute_tuning = dw_mci_execute_tuning,
1810 .card_busy = dw_mci_card_busy,
1811 .start_signal_voltage_switch = dw_mci_switch_voltage,
1812 .init_card = dw_mci_init_card,
1813 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1814 };
1815
1816 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1817 __releases(&host->lock)
1818 __acquires(&host->lock)
1819 {
1820 struct dw_mci_slot *slot;
1821 struct mmc_host *prev_mmc = host->slot->mmc;
1822
1823 WARN_ON(host->cmd || host->data);
1824
1825 host->slot->mrq = NULL;
1826 host->mrq = NULL;
1827 if (!list_empty(&host->queue)) {
1828 slot = list_entry(host->queue.next,
1829 struct dw_mci_slot, queue_node);
1830 list_del(&slot->queue_node);
1831 dev_vdbg(host->dev, "list not empty: %s is next\n",
1832 mmc_hostname(slot->mmc));
1833 host->state = STATE_SENDING_CMD;
1834 dw_mci_start_request(host, slot);
1835 } else {
1836 dev_vdbg(host->dev, "list empty\n");
1837
1838 if (host->state == STATE_SENDING_CMD11)
1839 host->state = STATE_WAITING_CMD11_DONE;
1840 else
1841 host->state = STATE_IDLE;
1842 }
1843
1844 spin_unlock(&host->lock);
1845 mmc_request_done(prev_mmc, mrq);
1846 spin_lock(&host->lock);
1847 }
1848
1849 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1850 {
1851 u32 status = host->cmd_status;
1852
1853 host->cmd_status = 0;
1854
1855 /* Read the response from the card (up to 16 bytes) */
1856 if (cmd->flags & MMC_RSP_PRESENT) {
1857 if (cmd->flags & MMC_RSP_136) {
1858 cmd->resp[3] = mci_readl(host, RESP0);
1859 cmd->resp[2] = mci_readl(host, RESP1);
1860 cmd->resp[1] = mci_readl(host, RESP2);
1861 cmd->resp[0] = mci_readl(host, RESP3);
1862 } else {
1863 cmd->resp[0] = mci_readl(host, RESP0);
1864 cmd->resp[1] = 0;
1865 cmd->resp[2] = 0;
1866 cmd->resp[3] = 0;
1867 }
1868 }
1869
1870 if (status & SDMMC_INT_RTO)
1871 cmd->error = -ETIMEDOUT;
1872 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1873 cmd->error = -EILSEQ;
1874 else if (status & SDMMC_INT_RESP_ERR)
1875 cmd->error = -EIO;
1876 else
1877 cmd->error = 0;
1878
1879 return cmd->error;
1880 }
1881
1882 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1883 {
1884 u32 status = host->data_status;
1885
1886 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1887 if (status & SDMMC_INT_DRTO) {
1888 data->error = -ETIMEDOUT;
1889 } else if (status & SDMMC_INT_DCRC) {
1890 data->error = -EILSEQ;
1891 } else if (status & SDMMC_INT_EBE) {
1892 if (host->dir_status ==
1893 DW_MCI_SEND_STATUS) {
1894 /*
1895 * No data CRC status was returned.
1896 * The number of bytes transferred
1897 * will be exaggerated in PIO mode.
1898 */
1899 data->bytes_xfered = 0;
1900 data->error = -ETIMEDOUT;
1901 } else if (host->dir_status ==
1902 DW_MCI_RECV_STATUS) {
1903 data->error = -EILSEQ;
1904 }
1905 } else {
1906 /* SDMMC_INT_SBE is included */
1907 data->error = -EILSEQ;
1908 }
1909
1910 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1911
1912 /*
1913 * After an error, there may be data lingering
1914 * in the FIFO
1915 */
1916 dw_mci_reset(host);
1917 } else {
1918 data->bytes_xfered = data->blocks * data->blksz;
1919 data->error = 0;
1920 }
1921
1922 return data->error;
1923 }
1924
1925 static void dw_mci_set_drto(struct dw_mci *host)
1926 {
1927 unsigned int drto_clks;
1928 unsigned int drto_div;
1929 unsigned int drto_ms;
1930 unsigned long irqflags;
1931
1932 drto_clks = mci_readl(host, TMOUT) >> 8;
1933 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1934 if (drto_div == 0)
1935 drto_div = 1;
1936
1937 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1938 host->bus_hz);
1939
1940 /* add a bit spare time */
1941 drto_ms += 10;
1942
1943 spin_lock_irqsave(&host->irq_lock, irqflags);
1944 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1945 mod_timer(&host->dto_timer,
1946 jiffies + msecs_to_jiffies(drto_ms));
1947 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1948 }
1949
1950 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1951 {
1952 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1953 return false;
1954
1955 /*
1956 * Really be certain that the timer has stopped. This is a bit of
1957 * paranoia and could only really happen if we had really bad
1958 * interrupt latency and the interrupt routine and timeout were
1959 * running concurrently so that the del_timer() in the interrupt
1960 * handler couldn't run.
1961 */
1962 WARN_ON(del_timer_sync(&host->cto_timer));
1963 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1964
1965 return true;
1966 }
1967
1968 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
1969 {
1970 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1971 return false;
1972
1973 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1974 WARN_ON(del_timer_sync(&host->dto_timer));
1975 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1976
1977 return true;
1978 }
1979
1980 static void dw_mci_tasklet_func(unsigned long priv)
1981 {
1982 struct dw_mci *host = (struct dw_mci *)priv;
1983 struct mmc_data *data;
1984 struct mmc_command *cmd;
1985 struct mmc_request *mrq;
1986 enum dw_mci_state state;
1987 enum dw_mci_state prev_state;
1988 unsigned int err;
1989
1990 spin_lock(&host->lock);
1991
1992 state = host->state;
1993 data = host->data;
1994 mrq = host->mrq;
1995
1996 do {
1997 prev_state = state;
1998
1999 switch (state) {
2000 case STATE_IDLE:
2001 case STATE_WAITING_CMD11_DONE:
2002 break;
2003
2004 case STATE_SENDING_CMD11:
2005 case STATE_SENDING_CMD:
2006 if (!dw_mci_clear_pending_cmd_complete(host))
2007 break;
2008
2009 cmd = host->cmd;
2010 host->cmd = NULL;
2011 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2012 err = dw_mci_command_complete(host, cmd);
2013 if (cmd == mrq->sbc && !err) {
2014 __dw_mci_start_request(host, host->slot,
2015 mrq->cmd);
2016 goto unlock;
2017 }
2018
2019 if (cmd->data && err) {
2020 /*
2021 * During UHS tuning sequence, sending the stop
2022 * command after the response CRC error would
2023 * throw the system into a confused state
2024 * causing all future tuning phases to report
2025 * failure.
2026 *
2027 * In such case controller will move into a data
2028 * transfer state after a response error or
2029 * response CRC error. Let's let that finish
2030 * before trying to send a stop, so we'll go to
2031 * STATE_SENDING_DATA.
2032 *
2033 * Although letting the data transfer take place
2034 * will waste a bit of time (we already know
2035 * the command was bad), it can't cause any
2036 * errors since it's possible it would have
2037 * taken place anyway if this tasklet got
2038 * delayed. Allowing the transfer to take place
2039 * avoids races and keeps things simple.
2040 */
2041 if ((err != -ETIMEDOUT) &&
2042 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
2043 state = STATE_SENDING_DATA;
2044 continue;
2045 }
2046
2047 dw_mci_stop_dma(host);
2048 send_stop_abort(host, data);
2049 state = STATE_SENDING_STOP;
2050 break;
2051 }
2052
2053 if (!cmd->data || err) {
2054 dw_mci_request_end(host, mrq);
2055 goto unlock;
2056 }
2057
2058 prev_state = state = STATE_SENDING_DATA;
2059 /* fall through */
2060
2061 case STATE_SENDING_DATA:
2062 /*
2063 * We could get a data error and never a transfer
2064 * complete so we'd better check for it here.
2065 *
2066 * Note that we don't really care if we also got a
2067 * transfer complete; stopping the DMA and sending an
2068 * abort won't hurt.
2069 */
2070 if (test_and_clear_bit(EVENT_DATA_ERROR,
2071 &host->pending_events)) {
2072 dw_mci_stop_dma(host);
2073 if (!(host->data_status & (SDMMC_INT_DRTO |
2074 SDMMC_INT_EBE)))
2075 send_stop_abort(host, data);
2076 state = STATE_DATA_ERROR;
2077 break;
2078 }
2079
2080 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2081 &host->pending_events)) {
2082 /*
2083 * If all data-related interrupts don't come
2084 * within the given time in reading data state.
2085 */
2086 if (host->dir_status == DW_MCI_RECV_STATUS)
2087 dw_mci_set_drto(host);
2088 break;
2089 }
2090
2091 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2092
2093 /*
2094 * Handle an EVENT_DATA_ERROR that might have shown up
2095 * before the transfer completed. This might not have
2096 * been caught by the check above because the interrupt
2097 * could have gone off between the previous check and
2098 * the check for transfer complete.
2099 *
2100 * Technically this ought not be needed assuming we
2101 * get a DATA_COMPLETE eventually (we'll notice the
2102 * error and end the request), but it shouldn't hurt.
2103 *
2104 * This has the advantage of sending the stop command.
2105 */
2106 if (test_and_clear_bit(EVENT_DATA_ERROR,
2107 &host->pending_events)) {
2108 dw_mci_stop_dma(host);
2109 if (!(host->data_status & (SDMMC_INT_DRTO |
2110 SDMMC_INT_EBE)))
2111 send_stop_abort(host, data);
2112 state = STATE_DATA_ERROR;
2113 break;
2114 }
2115 prev_state = state = STATE_DATA_BUSY;
2116
2117 /* fall through */
2118
2119 case STATE_DATA_BUSY:
2120 if (!dw_mci_clear_pending_data_complete(host)) {
2121 /*
2122 * If data error interrupt comes but data over
2123 * interrupt doesn't come within the given time.
2124 * in reading data state.
2125 */
2126 if (host->dir_status == DW_MCI_RECV_STATUS)
2127 dw_mci_set_drto(host);
2128 break;
2129 }
2130
2131 host->data = NULL;
2132 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2133 err = dw_mci_data_complete(host, data);
2134
2135 if (!err) {
2136 if (!data->stop || mrq->sbc) {
2137 if (mrq->sbc && data->stop)
2138 data->stop->error = 0;
2139 dw_mci_request_end(host, mrq);
2140 goto unlock;
2141 }
2142
2143 /* stop command for open-ended transfer*/
2144 if (data->stop)
2145 send_stop_abort(host, data);
2146 } else {
2147 /*
2148 * If we don't have a command complete now we'll
2149 * never get one since we just reset everything;
2150 * better end the request.
2151 *
2152 * If we do have a command complete we'll fall
2153 * through to the SENDING_STOP command and
2154 * everything will be peachy keen.
2155 */
2156 if (!test_bit(EVENT_CMD_COMPLETE,
2157 &host->pending_events)) {
2158 host->cmd = NULL;
2159 dw_mci_request_end(host, mrq);
2160 goto unlock;
2161 }
2162 }
2163
2164 /*
2165 * If err has non-zero,
2166 * stop-abort command has been already issued.
2167 */
2168 prev_state = state = STATE_SENDING_STOP;
2169
2170 /* fall through */
2171
2172 case STATE_SENDING_STOP:
2173 if (!dw_mci_clear_pending_cmd_complete(host))
2174 break;
2175
2176 /* CMD error in data command */
2177 if (mrq->cmd->error && mrq->data)
2178 dw_mci_reset(host);
2179
2180 host->cmd = NULL;
2181 host->data = NULL;
2182
2183 if (!mrq->sbc && mrq->stop)
2184 dw_mci_command_complete(host, mrq->stop);
2185 else
2186 host->cmd_status = 0;
2187
2188 dw_mci_request_end(host, mrq);
2189 goto unlock;
2190
2191 case STATE_DATA_ERROR:
2192 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2193 &host->pending_events))
2194 break;
2195
2196 state = STATE_DATA_BUSY;
2197 break;
2198 }
2199 } while (state != prev_state);
2200
2201 host->state = state;
2202 unlock:
2203 spin_unlock(&host->lock);
2204
2205 }
2206
2207 /* push final bytes to part_buf, only use during push */
2208 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2209 {
2210 memcpy((void *)&host->part_buf, buf, cnt);
2211 host->part_buf_count = cnt;
2212 }
2213
2214 /* append bytes to part_buf, only use during push */
2215 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2216 {
2217 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2218 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2219 host->part_buf_count += cnt;
2220 return cnt;
2221 }
2222
2223 /* pull first bytes from part_buf, only use during pull */
2224 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2225 {
2226 cnt = min_t(int, cnt, host->part_buf_count);
2227 if (cnt) {
2228 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2229 cnt);
2230 host->part_buf_count -= cnt;
2231 host->part_buf_start += cnt;
2232 }
2233 return cnt;
2234 }
2235
2236 /* pull final bytes from the part_buf, assuming it's just been filled */
2237 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2238 {
2239 memcpy(buf, &host->part_buf, cnt);
2240 host->part_buf_start = cnt;
2241 host->part_buf_count = (1 << host->data_shift) - cnt;
2242 }
2243
2244 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2245 {
2246 struct mmc_data *data = host->data;
2247 int init_cnt = cnt;
2248
2249 /* try and push anything in the part_buf */
2250 if (unlikely(host->part_buf_count)) {
2251 int len = dw_mci_push_part_bytes(host, buf, cnt);
2252
2253 buf += len;
2254 cnt -= len;
2255 if (host->part_buf_count == 2) {
2256 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2257 host->part_buf_count = 0;
2258 }
2259 }
2260 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2261 if (unlikely((unsigned long)buf & 0x1)) {
2262 while (cnt >= 2) {
2263 u16 aligned_buf[64];
2264 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2265 int items = len >> 1;
2266 int i;
2267 /* memcpy from input buffer into aligned buffer */
2268 memcpy(aligned_buf, buf, len);
2269 buf += len;
2270 cnt -= len;
2271 /* push data from aligned buffer into fifo */
2272 for (i = 0; i < items; ++i)
2273 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2274 }
2275 } else
2276 #endif
2277 {
2278 u16 *pdata = buf;
2279
2280 for (; cnt >= 2; cnt -= 2)
2281 mci_fifo_writew(host->fifo_reg, *pdata++);
2282 buf = pdata;
2283 }
2284 /* put anything remaining in the part_buf */
2285 if (cnt) {
2286 dw_mci_set_part_bytes(host, buf, cnt);
2287 /* Push data if we have reached the expected data length */
2288 if ((data->bytes_xfered + init_cnt) ==
2289 (data->blksz * data->blocks))
2290 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2291 }
2292 }
2293
2294 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2295 {
2296 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2297 if (unlikely((unsigned long)buf & 0x1)) {
2298 while (cnt >= 2) {
2299 /* pull data from fifo into aligned buffer */
2300 u16 aligned_buf[64];
2301 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2302 int items = len >> 1;
2303 int i;
2304
2305 for (i = 0; i < items; ++i)
2306 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2307 /* memcpy from aligned buffer into output buffer */
2308 memcpy(buf, aligned_buf, len);
2309 buf += len;
2310 cnt -= len;
2311 }
2312 } else
2313 #endif
2314 {
2315 u16 *pdata = buf;
2316
2317 for (; cnt >= 2; cnt -= 2)
2318 *pdata++ = mci_fifo_readw(host->fifo_reg);
2319 buf = pdata;
2320 }
2321 if (cnt) {
2322 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2323 dw_mci_pull_final_bytes(host, buf, cnt);
2324 }
2325 }
2326
2327 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2328 {
2329 struct mmc_data *data = host->data;
2330 int init_cnt = cnt;
2331
2332 /* try and push anything in the part_buf */
2333 if (unlikely(host->part_buf_count)) {
2334 int len = dw_mci_push_part_bytes(host, buf, cnt);
2335
2336 buf += len;
2337 cnt -= len;
2338 if (host->part_buf_count == 4) {
2339 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2340 host->part_buf_count = 0;
2341 }
2342 }
2343 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2344 if (unlikely((unsigned long)buf & 0x3)) {
2345 while (cnt >= 4) {
2346 u32 aligned_buf[32];
2347 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2348 int items = len >> 2;
2349 int i;
2350 /* memcpy from input buffer into aligned buffer */
2351 memcpy(aligned_buf, buf, len);
2352 buf += len;
2353 cnt -= len;
2354 /* push data from aligned buffer into fifo */
2355 for (i = 0; i < items; ++i)
2356 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2357 }
2358 } else
2359 #endif
2360 {
2361 u32 *pdata = buf;
2362
2363 for (; cnt >= 4; cnt -= 4)
2364 mci_fifo_writel(host->fifo_reg, *pdata++);
2365 buf = pdata;
2366 }
2367 /* put anything remaining in the part_buf */
2368 if (cnt) {
2369 dw_mci_set_part_bytes(host, buf, cnt);
2370 /* Push data if we have reached the expected data length */
2371 if ((data->bytes_xfered + init_cnt) ==
2372 (data->blksz * data->blocks))
2373 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2374 }
2375 }
2376
2377 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2378 {
2379 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2380 if (unlikely((unsigned long)buf & 0x3)) {
2381 while (cnt >= 4) {
2382 /* pull data from fifo into aligned buffer */
2383 u32 aligned_buf[32];
2384 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2385 int items = len >> 2;
2386 int i;
2387
2388 for (i = 0; i < items; ++i)
2389 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2390 /* memcpy from aligned buffer into output buffer */
2391 memcpy(buf, aligned_buf, len);
2392 buf += len;
2393 cnt -= len;
2394 }
2395 } else
2396 #endif
2397 {
2398 u32 *pdata = buf;
2399
2400 for (; cnt >= 4; cnt -= 4)
2401 *pdata++ = mci_fifo_readl(host->fifo_reg);
2402 buf = pdata;
2403 }
2404 if (cnt) {
2405 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2406 dw_mci_pull_final_bytes(host, buf, cnt);
2407 }
2408 }
2409
2410 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2411 {
2412 struct mmc_data *data = host->data;
2413 int init_cnt = cnt;
2414
2415 /* try and push anything in the part_buf */
2416 if (unlikely(host->part_buf_count)) {
2417 int len = dw_mci_push_part_bytes(host, buf, cnt);
2418
2419 buf += len;
2420 cnt -= len;
2421
2422 if (host->part_buf_count == 8) {
2423 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2424 host->part_buf_count = 0;
2425 }
2426 }
2427 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2428 if (unlikely((unsigned long)buf & 0x7)) {
2429 while (cnt >= 8) {
2430 u64 aligned_buf[16];
2431 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2432 int items = len >> 3;
2433 int i;
2434 /* memcpy from input buffer into aligned buffer */
2435 memcpy(aligned_buf, buf, len);
2436 buf += len;
2437 cnt -= len;
2438 /* push data from aligned buffer into fifo */
2439 for (i = 0; i < items; ++i)
2440 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2441 }
2442 } else
2443 #endif
2444 {
2445 u64 *pdata = buf;
2446
2447 for (; cnt >= 8; cnt -= 8)
2448 mci_fifo_writeq(host->fifo_reg, *pdata++);
2449 buf = pdata;
2450 }
2451 /* put anything remaining in the part_buf */
2452 if (cnt) {
2453 dw_mci_set_part_bytes(host, buf, cnt);
2454 /* Push data if we have reached the expected data length */
2455 if ((data->bytes_xfered + init_cnt) ==
2456 (data->blksz * data->blocks))
2457 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2458 }
2459 }
2460
2461 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2462 {
2463 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2464 if (unlikely((unsigned long)buf & 0x7)) {
2465 while (cnt >= 8) {
2466 /* pull data from fifo into aligned buffer */
2467 u64 aligned_buf[16];
2468 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2469 int items = len >> 3;
2470 int i;
2471
2472 for (i = 0; i < items; ++i)
2473 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2474
2475 /* memcpy from aligned buffer into output buffer */
2476 memcpy(buf, aligned_buf, len);
2477 buf += len;
2478 cnt -= len;
2479 }
2480 } else
2481 #endif
2482 {
2483 u64 *pdata = buf;
2484
2485 for (; cnt >= 8; cnt -= 8)
2486 *pdata++ = mci_fifo_readq(host->fifo_reg);
2487 buf = pdata;
2488 }
2489 if (cnt) {
2490 host->part_buf = mci_fifo_readq(host->fifo_reg);
2491 dw_mci_pull_final_bytes(host, buf, cnt);
2492 }
2493 }
2494
2495 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2496 {
2497 int len;
2498
2499 /* get remaining partial bytes */
2500 len = dw_mci_pull_part_bytes(host, buf, cnt);
2501 if (unlikely(len == cnt))
2502 return;
2503 buf += len;
2504 cnt -= len;
2505
2506 /* get the rest of the data */
2507 host->pull_data(host, buf, cnt);
2508 }
2509
2510 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2511 {
2512 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2513 void *buf;
2514 unsigned int offset;
2515 struct mmc_data *data = host->data;
2516 int shift = host->data_shift;
2517 u32 status;
2518 unsigned int len;
2519 unsigned int remain, fcnt;
2520
2521 do {
2522 if (!sg_miter_next(sg_miter))
2523 goto done;
2524
2525 host->sg = sg_miter->piter.sg;
2526 buf = sg_miter->addr;
2527 remain = sg_miter->length;
2528 offset = 0;
2529
2530 do {
2531 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2532 << shift) + host->part_buf_count;
2533 len = min(remain, fcnt);
2534 if (!len)
2535 break;
2536 dw_mci_pull_data(host, (void *)(buf + offset), len);
2537 data->bytes_xfered += len;
2538 offset += len;
2539 remain -= len;
2540 } while (remain);
2541
2542 sg_miter->consumed = offset;
2543 status = mci_readl(host, MINTSTS);
2544 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2545 /* if the RXDR is ready read again */
2546 } while ((status & SDMMC_INT_RXDR) ||
2547 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2548
2549 if (!remain) {
2550 if (!sg_miter_next(sg_miter))
2551 goto done;
2552 sg_miter->consumed = 0;
2553 }
2554 sg_miter_stop(sg_miter);
2555 return;
2556
2557 done:
2558 sg_miter_stop(sg_miter);
2559 host->sg = NULL;
2560 smp_wmb(); /* drain writebuffer */
2561 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2562 }
2563
2564 static void dw_mci_write_data_pio(struct dw_mci *host)
2565 {
2566 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2567 void *buf;
2568 unsigned int offset;
2569 struct mmc_data *data = host->data;
2570 int shift = host->data_shift;
2571 u32 status;
2572 unsigned int len;
2573 unsigned int fifo_depth = host->fifo_depth;
2574 unsigned int remain, fcnt;
2575
2576 do {
2577 if (!sg_miter_next(sg_miter))
2578 goto done;
2579
2580 host->sg = sg_miter->piter.sg;
2581 buf = sg_miter->addr;
2582 remain = sg_miter->length;
2583 offset = 0;
2584
2585 do {
2586 fcnt = ((fifo_depth -
2587 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2588 << shift) - host->part_buf_count;
2589 len = min(remain, fcnt);
2590 if (!len)
2591 break;
2592 host->push_data(host, (void *)(buf + offset), len);
2593 data->bytes_xfered += len;
2594 offset += len;
2595 remain -= len;
2596 } while (remain);
2597
2598 sg_miter->consumed = offset;
2599 status = mci_readl(host, MINTSTS);
2600 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2601 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2602
2603 if (!remain) {
2604 if (!sg_miter_next(sg_miter))
2605 goto done;
2606 sg_miter->consumed = 0;
2607 }
2608 sg_miter_stop(sg_miter);
2609 return;
2610
2611 done:
2612 sg_miter_stop(sg_miter);
2613 host->sg = NULL;
2614 smp_wmb(); /* drain writebuffer */
2615 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2616 }
2617
2618 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2619 {
2620 del_timer(&host->cto_timer);
2621
2622 if (!host->cmd_status)
2623 host->cmd_status = status;
2624
2625 smp_wmb(); /* drain writebuffer */
2626
2627 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2628 tasklet_schedule(&host->tasklet);
2629 }
2630
2631 static void dw_mci_handle_cd(struct dw_mci *host)
2632 {
2633 struct dw_mci_slot *slot = host->slot;
2634
2635 if (slot->mmc->ops->card_event)
2636 slot->mmc->ops->card_event(slot->mmc);
2637 mmc_detect_change(slot->mmc,
2638 msecs_to_jiffies(host->pdata->detect_delay_ms));
2639 }
2640
2641 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2642 {
2643 struct dw_mci *host = dev_id;
2644 u32 pending;
2645 struct dw_mci_slot *slot = host->slot;
2646 unsigned long irqflags;
2647
2648 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2649
2650 if (pending) {
2651 /* Check volt switch first, since it can look like an error */
2652 if ((host->state == STATE_SENDING_CMD11) &&
2653 (pending & SDMMC_INT_VOLT_SWITCH)) {
2654 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2655 pending &= ~SDMMC_INT_VOLT_SWITCH;
2656
2657 /*
2658 * Hold the lock; we know cmd11_timer can't be kicked
2659 * off after the lock is released, so safe to delete.
2660 */
2661 spin_lock_irqsave(&host->irq_lock, irqflags);
2662 dw_mci_cmd_interrupt(host, pending);
2663 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2664
2665 del_timer(&host->cmd11_timer);
2666 }
2667
2668 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2669 spin_lock_irqsave(&host->irq_lock, irqflags);
2670
2671 del_timer(&host->cto_timer);
2672 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2673 host->cmd_status = pending;
2674 smp_wmb(); /* drain writebuffer */
2675 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2676
2677 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2678 }
2679
2680 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2681 /* if there is an error report DATA_ERROR */
2682 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2683 host->data_status = pending;
2684 smp_wmb(); /* drain writebuffer */
2685 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2686 tasklet_schedule(&host->tasklet);
2687 }
2688
2689 if (pending & SDMMC_INT_DATA_OVER) {
2690 spin_lock_irqsave(&host->irq_lock, irqflags);
2691
2692 del_timer(&host->dto_timer);
2693
2694 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2695 if (!host->data_status)
2696 host->data_status = pending;
2697 smp_wmb(); /* drain writebuffer */
2698 if (host->dir_status == DW_MCI_RECV_STATUS) {
2699 if (host->sg != NULL)
2700 dw_mci_read_data_pio(host, true);
2701 }
2702 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2703 tasklet_schedule(&host->tasklet);
2704
2705 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2706 }
2707
2708 if (pending & SDMMC_INT_RXDR) {
2709 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2710 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2711 dw_mci_read_data_pio(host, false);
2712 }
2713
2714 if (pending & SDMMC_INT_TXDR) {
2715 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2716 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2717 dw_mci_write_data_pio(host);
2718 }
2719
2720 if (pending & SDMMC_INT_CMD_DONE) {
2721 spin_lock_irqsave(&host->irq_lock, irqflags);
2722
2723 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2724 dw_mci_cmd_interrupt(host, pending);
2725
2726 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2727 }
2728
2729 if (pending & SDMMC_INT_CD) {
2730 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2731 dw_mci_handle_cd(host);
2732 }
2733
2734 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2735 mci_writel(host, RINTSTS,
2736 SDMMC_INT_SDIO(slot->sdio_id));
2737 __dw_mci_enable_sdio_irq(slot, 0);
2738 sdio_signal_irq(slot->mmc);
2739 }
2740
2741 }
2742
2743 if (host->use_dma != TRANS_MODE_IDMAC)
2744 return IRQ_HANDLED;
2745
2746 /* Handle IDMA interrupts */
2747 if (host->dma_64bit_address == 1) {
2748 pending = mci_readl(host, IDSTS64);
2749 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2750 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2751 SDMMC_IDMAC_INT_RI);
2752 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2753 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2754 host->dma_ops->complete((void *)host);
2755 }
2756 } else {
2757 pending = mci_readl(host, IDSTS);
2758 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2759 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2760 SDMMC_IDMAC_INT_RI);
2761 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2762 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2763 host->dma_ops->complete((void *)host);
2764 }
2765 }
2766
2767 return IRQ_HANDLED;
2768 }
2769
2770 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2771 {
2772 struct dw_mci *host = slot->host;
2773 const struct dw_mci_drv_data *drv_data = host->drv_data;
2774 struct mmc_host *mmc = slot->mmc;
2775 int ctrl_id;
2776
2777 if (host->pdata->caps)
2778 mmc->caps = host->pdata->caps;
2779
2780 /*
2781 * Support MMC_CAP_ERASE by default.
2782 * It needs to use trim/discard/erase commands.
2783 */
2784 mmc->caps |= MMC_CAP_ERASE;
2785
2786 if (host->pdata->pm_caps)
2787 mmc->pm_caps = host->pdata->pm_caps;
2788
2789 if (host->dev->of_node) {
2790 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2791 if (ctrl_id < 0)
2792 ctrl_id = 0;
2793 } else {
2794 ctrl_id = to_platform_device(host->dev)->id;
2795 }
2796
2797 if (drv_data && drv_data->caps) {
2798 if (ctrl_id >= drv_data->num_caps) {
2799 dev_err(host->dev, "invalid controller id %d\n",
2800 ctrl_id);
2801 return -EINVAL;
2802 }
2803 mmc->caps |= drv_data->caps[ctrl_id];
2804 }
2805
2806 if (host->pdata->caps2)
2807 mmc->caps2 = host->pdata->caps2;
2808
2809 mmc->f_min = DW_MCI_FREQ_MIN;
2810 if (!mmc->f_max)
2811 mmc->f_max = DW_MCI_FREQ_MAX;
2812
2813 /* Process SDIO IRQs through the sdio_irq_work. */
2814 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2815 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2816
2817 return 0;
2818 }
2819
2820 static int dw_mci_init_slot(struct dw_mci *host)
2821 {
2822 struct mmc_host *mmc;
2823 struct dw_mci_slot *slot;
2824 int ret;
2825
2826 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2827 if (!mmc)
2828 return -ENOMEM;
2829
2830 slot = mmc_priv(mmc);
2831 slot->id = 0;
2832 slot->sdio_id = host->sdio_id0 + slot->id;
2833 slot->mmc = mmc;
2834 slot->host = host;
2835 host->slot = slot;
2836
2837 mmc->ops = &dw_mci_ops;
2838
2839 /*if there are external regulators, get them*/
2840 ret = mmc_regulator_get_supply(mmc);
2841 if (ret)
2842 goto err_host_allocated;
2843
2844 if (!mmc->ocr_avail)
2845 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2846
2847 ret = mmc_of_parse(mmc);
2848 if (ret)
2849 goto err_host_allocated;
2850
2851 ret = dw_mci_init_slot_caps(slot);
2852 if (ret)
2853 goto err_host_allocated;
2854
2855 /* Useful defaults if platform data is unset. */
2856 if (host->use_dma == TRANS_MODE_IDMAC) {
2857 mmc->max_segs = host->ring_size;
2858 mmc->max_blk_size = 65535;
2859 mmc->max_seg_size = 0x1000;
2860 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2861 mmc->max_blk_count = mmc->max_req_size / 512;
2862 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2863 mmc->max_segs = 64;
2864 mmc->max_blk_size = 65535;
2865 mmc->max_blk_count = 65535;
2866 mmc->max_req_size =
2867 mmc->max_blk_size * mmc->max_blk_count;
2868 mmc->max_seg_size = mmc->max_req_size;
2869 } else {
2870 /* TRANS_MODE_PIO */
2871 mmc->max_segs = 64;
2872 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2873 mmc->max_blk_count = 512;
2874 mmc->max_req_size = mmc->max_blk_size *
2875 mmc->max_blk_count;
2876 mmc->max_seg_size = mmc->max_req_size;
2877 }
2878
2879 dw_mci_get_cd(mmc);
2880
2881 ret = mmc_add_host(mmc);
2882 if (ret)
2883 goto err_host_allocated;
2884
2885 #if defined(CONFIG_DEBUG_FS)
2886 dw_mci_init_debugfs(slot);
2887 #endif
2888
2889 return 0;
2890
2891 err_host_allocated:
2892 mmc_free_host(mmc);
2893 return ret;
2894 }
2895
2896 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2897 {
2898 /* Debugfs stuff is cleaned up by mmc core */
2899 mmc_remove_host(slot->mmc);
2900 slot->host->slot = NULL;
2901 mmc_free_host(slot->mmc);
2902 }
2903
2904 static void dw_mci_init_dma(struct dw_mci *host)
2905 {
2906 int addr_config;
2907 struct device *dev = host->dev;
2908
2909 /*
2910 * Check tansfer mode from HCON[17:16]
2911 * Clear the ambiguous description of dw_mmc databook:
2912 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2913 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2914 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2915 * 2b'11: Non DW DMA Interface -> pio only
2916 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2917 * simpler request/acknowledge handshake mechanism and both of them
2918 * are regarded as external dma master for dw_mmc.
2919 */
2920 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2921 if (host->use_dma == DMA_INTERFACE_IDMA) {
2922 host->use_dma = TRANS_MODE_IDMAC;
2923 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2924 host->use_dma == DMA_INTERFACE_GDMA) {
2925 host->use_dma = TRANS_MODE_EDMAC;
2926 } else {
2927 goto no_dma;
2928 }
2929
2930 /* Determine which DMA interface to use */
2931 if (host->use_dma == TRANS_MODE_IDMAC) {
2932 /*
2933 * Check ADDR_CONFIG bit in HCON to find
2934 * IDMAC address bus width
2935 */
2936 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2937
2938 if (addr_config == 1) {
2939 /* host supports IDMAC in 64-bit address mode */
2940 host->dma_64bit_address = 1;
2941 dev_info(host->dev,
2942 "IDMAC supports 64-bit address mode.\n");
2943 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2944 dma_set_coherent_mask(host->dev,
2945 DMA_BIT_MASK(64));
2946 } else {
2947 /* host supports IDMAC in 32-bit address mode */
2948 host->dma_64bit_address = 0;
2949 dev_info(host->dev,
2950 "IDMAC supports 32-bit address mode.\n");
2951 }
2952
2953 /* Alloc memory for sg translation */
2954 host->sg_cpu = dmam_alloc_coherent(host->dev,
2955 DESC_RING_BUF_SZ,
2956 &host->sg_dma, GFP_KERNEL);
2957 if (!host->sg_cpu) {
2958 dev_err(host->dev,
2959 "%s: could not alloc DMA memory\n",
2960 __func__);
2961 goto no_dma;
2962 }
2963
2964 host->dma_ops = &dw_mci_idmac_ops;
2965 dev_info(host->dev, "Using internal DMA controller.\n");
2966 } else {
2967 /* TRANS_MODE_EDMAC: check dma bindings again */
2968 if ((device_property_read_string_array(dev, "dma-names",
2969 NULL, 0) < 0) ||
2970 !device_property_present(dev, "dmas")) {
2971 goto no_dma;
2972 }
2973 host->dma_ops = &dw_mci_edmac_ops;
2974 dev_info(host->dev, "Using external DMA controller.\n");
2975 }
2976
2977 if (host->dma_ops->init && host->dma_ops->start &&
2978 host->dma_ops->stop && host->dma_ops->cleanup) {
2979 if (host->dma_ops->init(host)) {
2980 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2981 __func__);
2982 goto no_dma;
2983 }
2984 } else {
2985 dev_err(host->dev, "DMA initialization not found.\n");
2986 goto no_dma;
2987 }
2988
2989 return;
2990
2991 no_dma:
2992 dev_info(host->dev, "Using PIO mode.\n");
2993 host->use_dma = TRANS_MODE_PIO;
2994 }
2995
2996 static void dw_mci_cmd11_timer(struct timer_list *t)
2997 {
2998 struct dw_mci *host = from_timer(host, t, cmd11_timer);
2999
3000 if (host->state != STATE_SENDING_CMD11) {
3001 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3002 return;
3003 }
3004
3005 host->cmd_status = SDMMC_INT_RTO;
3006 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3007 tasklet_schedule(&host->tasklet);
3008 }
3009
3010 static void dw_mci_cto_timer(struct timer_list *t)
3011 {
3012 struct dw_mci *host = from_timer(host, t, cto_timer);
3013 unsigned long irqflags;
3014 u32 pending;
3015
3016 spin_lock_irqsave(&host->irq_lock, irqflags);
3017
3018 /*
3019 * If somehow we have very bad interrupt latency it's remotely possible
3020 * that the timer could fire while the interrupt is still pending or
3021 * while the interrupt is midway through running. Let's be paranoid
3022 * and detect those two cases. Note that this is paranoia is somewhat
3023 * justified because in this function we don't actually cancel the
3024 * pending command in the controller--we just assume it will never come.
3025 */
3026 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3027 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3028 /* The interrupt should fire; no need to act but we can warn */
3029 dev_warn(host->dev, "Unexpected interrupt latency\n");
3030 goto exit;
3031 }
3032 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3033 /* Presumably interrupt handler couldn't delete the timer */
3034 dev_warn(host->dev, "CTO timeout when already completed\n");
3035 goto exit;
3036 }
3037
3038 /*
3039 * Continued paranoia to make sure we're in the state we expect.
3040 * This paranoia isn't really justified but it seems good to be safe.
3041 */
3042 switch (host->state) {
3043 case STATE_SENDING_CMD11:
3044 case STATE_SENDING_CMD:
3045 case STATE_SENDING_STOP:
3046 /*
3047 * If CMD_DONE interrupt does NOT come in sending command
3048 * state, we should notify the driver to terminate current
3049 * transfer and report a command timeout to the core.
3050 */
3051 host->cmd_status = SDMMC_INT_RTO;
3052 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3053 tasklet_schedule(&host->tasklet);
3054 break;
3055 default:
3056 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3057 host->state);
3058 break;
3059 }
3060
3061 exit:
3062 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3063 }
3064
3065 static void dw_mci_dto_timer(struct timer_list *t)
3066 {
3067 struct dw_mci *host = from_timer(host, t, dto_timer);
3068 unsigned long irqflags;
3069 u32 pending;
3070
3071 spin_lock_irqsave(&host->irq_lock, irqflags);
3072
3073 /*
3074 * The DTO timer is much longer than the CTO timer, so it's even less
3075 * likely that we'll these cases, but it pays to be paranoid.
3076 */
3077 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3078 if (pending & SDMMC_INT_DATA_OVER) {
3079 /* The interrupt should fire; no need to act but we can warn */
3080 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3081 goto exit;
3082 }
3083 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3084 /* Presumably interrupt handler couldn't delete the timer */
3085 dev_warn(host->dev, "DTO timeout when already completed\n");
3086 goto exit;
3087 }
3088
3089 /*
3090 * Continued paranoia to make sure we're in the state we expect.
3091 * This paranoia isn't really justified but it seems good to be safe.
3092 */
3093 switch (host->state) {
3094 case STATE_SENDING_DATA:
3095 case STATE_DATA_BUSY:
3096 /*
3097 * If DTO interrupt does NOT come in sending data state,
3098 * we should notify the driver to terminate current transfer
3099 * and report a data timeout to the core.
3100 */
3101 host->data_status = SDMMC_INT_DRTO;
3102 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3103 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3104 tasklet_schedule(&host->tasklet);
3105 break;
3106 default:
3107 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3108 host->state);
3109 break;
3110 }
3111
3112 exit:
3113 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3114 }
3115
3116 #ifdef CONFIG_OF
3117 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3118 {
3119 struct dw_mci_board *pdata;
3120 struct device *dev = host->dev;
3121 const struct dw_mci_drv_data *drv_data = host->drv_data;
3122 int ret;
3123 u32 clock_frequency;
3124
3125 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3126 if (!pdata)
3127 return ERR_PTR(-ENOMEM);
3128
3129 /* find reset controller when exist */
3130 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3131 if (IS_ERR(pdata->rstc)) {
3132 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3133 return ERR_PTR(-EPROBE_DEFER);
3134 }
3135
3136 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3137 dev_info(dev,
3138 "fifo-depth property not found, using value of FIFOTH register as default\n");
3139
3140 device_property_read_u32(dev, "card-detect-delay",
3141 &pdata->detect_delay_ms);
3142
3143 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3144
3145 if (device_property_present(dev, "fifo-watermark-aligned"))
3146 host->wm_aligned = true;
3147
3148 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3149 pdata->bus_hz = clock_frequency;
3150
3151 if (drv_data && drv_data->parse_dt) {
3152 ret = drv_data->parse_dt(host);
3153 if (ret)
3154 return ERR_PTR(ret);
3155 }
3156
3157 return pdata;
3158 }
3159
3160 #else /* CONFIG_OF */
3161 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3162 {
3163 return ERR_PTR(-EINVAL);
3164 }
3165 #endif /* CONFIG_OF */
3166
3167 static void dw_mci_enable_cd(struct dw_mci *host)
3168 {
3169 unsigned long irqflags;
3170 u32 temp;
3171
3172 /*
3173 * No need for CD if all slots have a non-error GPIO
3174 * as well as broken card detection is found.
3175 */
3176 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3177 return;
3178
3179 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3180 spin_lock_irqsave(&host->irq_lock, irqflags);
3181 temp = mci_readl(host, INTMASK);
3182 temp |= SDMMC_INT_CD;
3183 mci_writel(host, INTMASK, temp);
3184 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3185 }
3186 }
3187
3188 int dw_mci_probe(struct dw_mci *host)
3189 {
3190 const struct dw_mci_drv_data *drv_data = host->drv_data;
3191 int width, i, ret = 0;
3192 u32 fifo_size;
3193
3194 if (!host->pdata) {
3195 host->pdata = dw_mci_parse_dt(host);
3196 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3197 return -EPROBE_DEFER;
3198 } else if (IS_ERR(host->pdata)) {
3199 dev_err(host->dev, "platform data not available\n");
3200 return -EINVAL;
3201 }
3202 }
3203
3204 host->biu_clk = devm_clk_get(host->dev, "biu");
3205 if (IS_ERR(host->biu_clk)) {
3206 dev_dbg(host->dev, "biu clock not available\n");
3207 } else {
3208 ret = clk_prepare_enable(host->biu_clk);
3209 if (ret) {
3210 dev_err(host->dev, "failed to enable biu clock\n");
3211 return ret;
3212 }
3213 }
3214
3215 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3216 if (IS_ERR(host->ciu_clk)) {
3217 dev_dbg(host->dev, "ciu clock not available\n");
3218 host->bus_hz = host->pdata->bus_hz;
3219 } else {
3220 ret = clk_prepare_enable(host->ciu_clk);
3221 if (ret) {
3222 dev_err(host->dev, "failed to enable ciu clock\n");
3223 goto err_clk_biu;
3224 }
3225
3226 if (host->pdata->bus_hz) {
3227 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3228 if (ret)
3229 dev_warn(host->dev,
3230 "Unable to set bus rate to %uHz\n",
3231 host->pdata->bus_hz);
3232 }
3233 host->bus_hz = clk_get_rate(host->ciu_clk);
3234 }
3235
3236 if (!host->bus_hz) {
3237 dev_err(host->dev,
3238 "Platform data must supply bus speed\n");
3239 ret = -ENODEV;
3240 goto err_clk_ciu;
3241 }
3242
3243 if (!IS_ERR(host->pdata->rstc)) {
3244 reset_control_assert(host->pdata->rstc);
3245 usleep_range(10, 50);
3246 reset_control_deassert(host->pdata->rstc);
3247 }
3248
3249 if (drv_data && drv_data->init) {
3250 ret = drv_data->init(host);
3251 if (ret) {
3252 dev_err(host->dev,
3253 "implementation specific init failed\n");
3254 goto err_clk_ciu;
3255 }
3256 }
3257
3258 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3259 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3260 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3261
3262 spin_lock_init(&host->lock);
3263 spin_lock_init(&host->irq_lock);
3264 INIT_LIST_HEAD(&host->queue);
3265
3266 /*
3267 * Get the host data width - this assumes that HCON has been set with
3268 * the correct values.
3269 */
3270 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3271 if (!i) {
3272 host->push_data = dw_mci_push_data16;
3273 host->pull_data = dw_mci_pull_data16;
3274 width = 16;
3275 host->data_shift = 1;
3276 } else if (i == 2) {
3277 host->push_data = dw_mci_push_data64;
3278 host->pull_data = dw_mci_pull_data64;
3279 width = 64;
3280 host->data_shift = 3;
3281 } else {
3282 /* Check for a reserved value, and warn if it is */
3283 WARN((i != 1),
3284 "HCON reports a reserved host data width!\n"
3285 "Defaulting to 32-bit access.\n");
3286 host->push_data = dw_mci_push_data32;
3287 host->pull_data = dw_mci_pull_data32;
3288 width = 32;
3289 host->data_shift = 2;
3290 }
3291
3292 /* Reset all blocks */
3293 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3294 ret = -ENODEV;
3295 goto err_clk_ciu;
3296 }
3297
3298 host->dma_ops = host->pdata->dma_ops;
3299 dw_mci_init_dma(host);
3300
3301 /* Clear the interrupts for the host controller */
3302 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3303 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3304
3305 /* Put in max timeout */
3306 mci_writel(host, TMOUT, 0xFFFFFFFF);
3307
3308 /*
3309 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3310 * Tx Mark = fifo_size / 2 DMA Size = 8
3311 */
3312 if (!host->pdata->fifo_depth) {
3313 /*
3314 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3315 * have been overwritten by the bootloader, just like we're
3316 * about to do, so if you know the value for your hardware, you
3317 * should put it in the platform data.
3318 */
3319 fifo_size = mci_readl(host, FIFOTH);
3320 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3321 } else {
3322 fifo_size = host->pdata->fifo_depth;
3323 }
3324 host->fifo_depth = fifo_size;
3325 host->fifoth_val =
3326 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3327 mci_writel(host, FIFOTH, host->fifoth_val);
3328
3329 /* disable clock to CIU */
3330 mci_writel(host, CLKENA, 0);
3331 mci_writel(host, CLKSRC, 0);
3332
3333 /*
3334 * In 2.40a spec, Data offset is changed.
3335 * Need to check the version-id and set data-offset for DATA register.
3336 */
3337 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3338 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3339
3340 if (host->data_addr_override)
3341 host->fifo_reg = host->regs + host->data_addr_override;
3342 else if (host->verid < DW_MMC_240A)
3343 host->fifo_reg = host->regs + DATA_OFFSET;
3344 else
3345 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3346
3347 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3348 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3349 host->irq_flags, "dw-mci", host);
3350 if (ret)
3351 goto err_dmaunmap;
3352
3353 /*
3354 * Enable interrupts for command done, data over, data empty,
3355 * receive ready and error such as transmit, receive timeout, crc error
3356 */
3357 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3358 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3359 DW_MCI_ERROR_FLAGS);
3360 /* Enable mci interrupt */
3361 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3362
3363 dev_info(host->dev,
3364 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3365 host->irq, width, fifo_size);
3366
3367 /* We need at least one slot to succeed */
3368 ret = dw_mci_init_slot(host);
3369 if (ret) {
3370 dev_dbg(host->dev, "slot %d init failed\n", i);
3371 goto err_dmaunmap;
3372 }
3373
3374 /* Now that slots are all setup, we can enable card detect */
3375 dw_mci_enable_cd(host);
3376
3377 return 0;
3378
3379 err_dmaunmap:
3380 if (host->use_dma && host->dma_ops->exit)
3381 host->dma_ops->exit(host);
3382
3383 if (!IS_ERR(host->pdata->rstc))
3384 reset_control_assert(host->pdata->rstc);
3385
3386 err_clk_ciu:
3387 clk_disable_unprepare(host->ciu_clk);
3388
3389 err_clk_biu:
3390 clk_disable_unprepare(host->biu_clk);
3391
3392 return ret;
3393 }
3394 EXPORT_SYMBOL(dw_mci_probe);
3395
3396 void dw_mci_remove(struct dw_mci *host)
3397 {
3398 dev_dbg(host->dev, "remove slot\n");
3399 if (host->slot)
3400 dw_mci_cleanup_slot(host->slot);
3401
3402 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3403 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3404
3405 /* disable clock to CIU */
3406 mci_writel(host, CLKENA, 0);
3407 mci_writel(host, CLKSRC, 0);
3408
3409 if (host->use_dma && host->dma_ops->exit)
3410 host->dma_ops->exit(host);
3411
3412 if (!IS_ERR(host->pdata->rstc))
3413 reset_control_assert(host->pdata->rstc);
3414
3415 clk_disable_unprepare(host->ciu_clk);
3416 clk_disable_unprepare(host->biu_clk);
3417 }
3418 EXPORT_SYMBOL(dw_mci_remove);
3419
3420
3421
3422 #ifdef CONFIG_PM
3423 int dw_mci_runtime_suspend(struct device *dev)
3424 {
3425 struct dw_mci *host = dev_get_drvdata(dev);
3426
3427 if (host->use_dma && host->dma_ops->exit)
3428 host->dma_ops->exit(host);
3429
3430 clk_disable_unprepare(host->ciu_clk);
3431
3432 if (host->slot &&
3433 (mmc_can_gpio_cd(host->slot->mmc) ||
3434 !mmc_card_is_removable(host->slot->mmc)))
3435 clk_disable_unprepare(host->biu_clk);
3436
3437 return 0;
3438 }
3439 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3440
3441 int dw_mci_runtime_resume(struct device *dev)
3442 {
3443 int ret = 0;
3444 struct dw_mci *host = dev_get_drvdata(dev);
3445
3446 if (host->slot &&
3447 (mmc_can_gpio_cd(host->slot->mmc) ||
3448 !mmc_card_is_removable(host->slot->mmc))) {
3449 ret = clk_prepare_enable(host->biu_clk);
3450 if (ret)
3451 return ret;
3452 }
3453
3454 ret = clk_prepare_enable(host->ciu_clk);
3455 if (ret)
3456 goto err;
3457
3458 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3459 clk_disable_unprepare(host->ciu_clk);
3460 ret = -ENODEV;
3461 goto err;
3462 }
3463
3464 if (host->use_dma && host->dma_ops->init)
3465 host->dma_ops->init(host);
3466
3467 /*
3468 * Restore the initial value at FIFOTH register
3469 * And Invalidate the prev_blksz with zero
3470 */
3471 mci_writel(host, FIFOTH, host->fifoth_val);
3472 host->prev_blksz = 0;
3473
3474 /* Put in max timeout */
3475 mci_writel(host, TMOUT, 0xFFFFFFFF);
3476
3477 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3478 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3479 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3480 DW_MCI_ERROR_FLAGS);
3481 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3482
3483
3484 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3485 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3486
3487 /* Force setup bus to guarantee available clock output */
3488 dw_mci_setup_bus(host->slot, true);
3489
3490 /* Now that slots are all setup, we can enable card detect */
3491 dw_mci_enable_cd(host);
3492
3493 return 0;
3494
3495 err:
3496 if (host->slot &&
3497 (mmc_can_gpio_cd(host->slot->mmc) ||
3498 !mmc_card_is_removable(host->slot->mmc)))
3499 clk_disable_unprepare(host->biu_clk);
3500
3501 return ret;
3502 }
3503 EXPORT_SYMBOL(dw_mci_runtime_resume);
3504 #endif /* CONFIG_PM */
3505
3506 static int __init dw_mci_init(void)
3507 {
3508 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3509 return 0;
3510 }
3511
3512 static void __exit dw_mci_exit(void)
3513 {
3514 }
3515
3516 module_init(dw_mci_init);
3517 module_exit(dw_mci_exit);
3518
3519 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3520 MODULE_AUTHOR("NXP Semiconductor VietNam");
3521 MODULE_AUTHOR("Imagination Technologies Ltd");
3522 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support