drivers/mmc/host/renesas_sdhi_core.c

   1 /*
   2  * Renesas SDHI
   3  *
   4  * Copyright (C) 2015-17 Renesas Electronics Corporation
   5  * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
   6  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   7  * Copyright (C) 2009 Magnus Damm
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * Based on "Compaq ASIC3 support":
  14  *
  15  * Copyright 2001 Compaq Computer Corporation.
  16  * Copyright 2004-2005 Phil Blundell
  17  * Copyright 2007-2008 OpenedHand Ltd.
  18  *
  19  * Authors: Phil Blundell <pb@handhelds.org>,
  20  *          Samuel Ortiz <sameo@openedhand.com>
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/of_device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/slot-gpio.h>
  32 #include <linux/mfd/tmio.h>
  33 #include <linux/sh_dma.h>
  34 #include <linux/delay.h>
  35 #include <linux/pinctrl/consumer.h>
  36 #include <linux/pinctrl/pinctrl-state.h>
  37 #include <linux/regulator/consumer.h>
  38
  39 #include "renesas_sdhi.h"
  40 #include "tmio_mmc.h"
  41
  42 #define HOST_MODE               0xe4
  43
  44 #define SDHI_VER_GEN2_SDR50     0x490c
  45 #define SDHI_VER_RZ_A1          0x820b
  46 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  47 #define SDHI_VER_GEN2_SDR104    0xcb0d
  48 #define SDHI_VER_GEN3_SD        0xcc10
  49 #define SDHI_VER_GEN3_SDMMC     0xcd10
  50
  51 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  52 {
  53         u32 val;
  54
  55         /*
  56          * see also
  57          *      renesas_sdhi_of_data :: dma_buswidth
  58          */
  59         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  60         case SDHI_VER_GEN2_SDR50:
  61                 val = (width == 32) ? 0x0001 : 0x0000;
  62                 break;
  63         case SDHI_VER_GEN2_SDR104:
  64                 val = (width == 32) ? 0x0000 : 0x0001;
  65                 break;
  66         case SDHI_VER_GEN3_SD:
  67         case SDHI_VER_GEN3_SDMMC:
  68                 if (width == 64)
  69                         val = 0x0000;
  70                 else if (width == 32)
  71                         val = 0x0101;
  72                 else
  73                         val = 0x0001;
  74                 break;
  75         default:
  76                 /* nothing to do */
  77                 return;
  78         }
  79
  80         sd_ctrl_write16(host, HOST_MODE, val);
  81 }
  82
  83 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  84 {
  85         struct mmc_host *mmc = host->mmc;
  86         struct renesas_sdhi *priv = host_to_priv(host);
  87         int ret = clk_prepare_enable(priv->clk);
  88
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = clk_prepare_enable(priv->clk_cd);
  93         if (ret < 0) {
  94                 clk_disable_unprepare(priv->clk);
  95                 return ret;
  96         }
  97
  98         /*
  99          * The clock driver may not know what maximum frequency
 100          * actually works, so it should be set with the max-frequency
 101          * property which will already have been read to f_max.  If it
 102          * was missing, assume the current frequency is the maximum.
 103          */
 104         if (!mmc->f_max)
 105                 mmc->f_max = clk_get_rate(priv->clk);
 106
 107         /*
 108          * Minimum frequency is the minimum input clock frequency
 109          * divided by our maximum divider.
 110          */
 111         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 112
 113         /* enable 16bit data access on SDBUF as default */
 114         renesas_sdhi_sdbuf_width(host, 16);
 115
 116         return 0;
 117 }
 118
 119 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 120                                             unsigned int new_clock)
 121 {
 122         struct renesas_sdhi *priv = host_to_priv(host);
 123         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 124         int i, ret;
 125
 126         /* tested only on R-Car Gen2+ currently; may work for others */
 127         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 128                 return clk_get_rate(priv->clk);
 129
 130         /*
 131          * We want the bus clock to be as close as possible to, but no
 132          * greater than, new_clock.  As we can divide by 1 << i for
 133          * any i in [0, 9] we want the input clock to be as close as
 134          * possible, but no greater than, new_clock << i.
 135          */
 136         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 137                 freq = clk_round_rate(priv->clk, new_clock << i);
 138                 if (freq > (new_clock << i)) {
 139                         /* Too fast; look for a slightly slower option */
 140                         freq = clk_round_rate(priv->clk,
 141                                               (new_clock << i) / 4 * 3);
 142                         if (freq > (new_clock << i))
 143                                 continue;
 144                 }
 145
 146                 diff = new_clock - (freq >> i);
 147                 if (diff <= diff_min) {
 148                         best_freq = freq;
 149                         diff_min = diff;
 150                 }
 151         }
 152
 153         ret = clk_set_rate(priv->clk, best_freq);
 154
 155         return ret == 0 ? best_freq : clk_get_rate(priv->clk);
 156 }
 157
 158 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 159 {
 160         struct renesas_sdhi *priv = host_to_priv(host);
 161
 162         clk_disable_unprepare(priv->clk);
 163         clk_disable_unprepare(priv->clk_cd);
 164 }
 165
 166 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 167 {
 168         struct tmio_mmc_host *host = mmc_priv(mmc);
 169
 170         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 171                  TMIO_STAT_DAT0);
 172 }
 173
 174 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 175                                                     struct mmc_ios *ios)
 176 {
 177         struct tmio_mmc_host *host = mmc_priv(mmc);
 178         struct renesas_sdhi *priv = host_to_priv(host);
 179         struct pinctrl_state *pin_state;
 180         int ret;
 181
 182         switch (ios->signal_voltage) {
 183         case MMC_SIGNAL_VOLTAGE_330:
 184                 pin_state = priv->pins_default;
 185                 break;
 186         case MMC_SIGNAL_VOLTAGE_180:
 187                 pin_state = priv->pins_uhs;
 188                 break;
 189         default:
 190                 return -EINVAL;
 191         }
 192
 193         /*
 194          * If anything is missing, assume signal voltage is fixed at
 195          * 3.3V and succeed/fail accordingly.
 196          */
 197         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 198                 return ios->signal_voltage ==
 199                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 200
 201         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 202         if (ret)
 203                 return ret;
 204
 205         return pinctrl_select_state(priv->pinctrl, pin_state);
 206 }
 207
 208 /* SCC registers */
 209 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 210 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 211 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 212 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 213 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 214 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 215
 216 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
 217 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 218 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 219 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 220
 221 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
 222 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 223 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
 224 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 225 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
 226 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 227
 228 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 229                                 struct renesas_sdhi *priv, int addr)
 230 {
 231         return readl(priv->scc_ctl + (addr << host->bus_shift));
 232 }
 233
 234 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 235                                   struct renesas_sdhi *priv,
 236                                   int addr, u32 val)
 237 {
 238         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 239 }
 240
 241 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 242 {
 243         struct renesas_sdhi *priv;
 244
 245         priv = host_to_priv(host);
 246
 247         /* set sampling clock selection range */
 248         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 249                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 250
 251         /* Initialize SCC */
 252         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 253
 254         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 255                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 256                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
 257
 258         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 259                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 260
 261         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 262                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 263                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 264
 265         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 266                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 267
 268         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 269                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 270                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 271
 272         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 273
 274         /* Read TAPNUM */
 275         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 276                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 277                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 278 }
 279
 280 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
 281                                         unsigned long tap)
 282 {
 283         struct renesas_sdhi *priv = host_to_priv(host);
 284
 285         /* Set sampling clock position */
 286         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
 287 }
 288
 289 #define SH_MOBILE_SDHI_MAX_TAP 3
 290
 291 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 292 {
 293         struct renesas_sdhi *priv = host_to_priv(host);
 294         unsigned long tap_cnt;  /* counter of tuning success */
 295         unsigned long tap_set;  /* tap position */
 296         unsigned long tap_start;/* start position of tuning success */
 297         unsigned long tap_end;  /* end position of tuning success */
 298         unsigned long ntap;     /* temporary counter of tuning success */
 299         unsigned long i;
 300
 301         /* Clear SCC_RVSREQ */
 302         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 303
 304         /*
 305          * Find the longest consecutive run of successful probes.  If that
 306          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 307          * center index as the tap.
 308          */
 309         tap_cnt = 0;
 310         ntap = 0;
 311         tap_start = 0;
 312         tap_end = 0;
 313         for (i = 0; i < host->tap_num * 2; i++) {
 314                 if (test_bit(i, host->taps)) {
 315                         ntap++;
 316                 } else {
 317                         if (ntap > tap_cnt) {
 318                                 tap_start = i - ntap;
 319                                 tap_end = i - 1;
 320                                 tap_cnt = ntap;
 321                         }
 322                         ntap = 0;
 323                 }
 324         }
 325
 326         if (ntap > tap_cnt) {
 327                 tap_start = i - ntap;
 328                 tap_end = i - 1;
 329                 tap_cnt = ntap;
 330         }
 331
 332         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 333                 tap_set = (tap_start + tap_end) / 2 % host->tap_num;
 334         else
 335                 return -EIO;
 336
 337         /* Set SCC */
 338         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
 339
 340         /* Enable auto re-tuning */
 341         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 342                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 343                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 344
 345         return 0;
 346 }
 347
 348 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 349 {
 350         struct renesas_sdhi *priv = host_to_priv(host);
 351
 352         /* Check SCC error */
 353         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 354             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
 355             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 356             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 357                 /* Clear SCC error */
 358                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 359                 return true;
 360         }
 361
 362         return false;
 363 }
 364
 365 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
 366 {
 367         struct renesas_sdhi *priv;
 368
 369         priv = host_to_priv(host);
 370
 371         /* Reset SCC */
 372         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 373                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 374
 375         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 376                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 377                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 378
 379         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 380                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 381
 382         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 383                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 384                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 385
 386         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 387                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 388                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 389 }
 390
 391 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 392 {
 393         int timeout = 1000;
 394         /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 395         u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 396
 397         while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 398                               & bit) == wait_state)
 399                 udelay(1);
 400
 401         if (!timeout) {
 402                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 403                 return -EBUSY;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 410 {
 411         u32 bit = TMIO_STAT_SCLKDIVEN;
 412
 413         switch (addr) {
 414         case CTL_SD_CMD:
 415         case CTL_STOP_INTERNAL_ACTION:
 416         case CTL_XFER_BLK_COUNT:
 417         case CTL_SD_XFER_LEN:
 418         case CTL_SD_MEM_CARD_OPT:
 419         case CTL_TRANSACTION_CTL:
 420         case CTL_DMA_ENABLE:
 421         case HOST_MODE:
 422                 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 423                         bit = TMIO_STAT_CMD_BUSY;
 424                 /* fallthrough */
 425         case CTL_SD_CARD_CLK_CTL:
 426                 return renesas_sdhi_wait_idle(host, bit);
 427         }
 428
 429         return 0;
 430 }
 431
 432 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 433                                        unsigned int direction, int blk_size)
 434 {
 435         /*
 436          * In Renesas controllers, when performing a
 437          * multiple block read of one or two blocks,
 438          * depending on the timing with which the
 439          * response register is read, the response
 440          * value may not be read properly.
 441          * Use single block read for this HW bug
 442          */
 443         if ((direction == MMC_DATA_READ) &&
 444             blk_size == 2)
 445                 return 1;
 446
 447         return blk_size;
 448 }
 449
 450 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 451 {
 452         /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 453         int width = (host->bus_shift == 2) ? 64 : 32;
 454
 455         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 456         renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 457 }
 458
 459 int renesas_sdhi_probe(struct platform_device *pdev,
 460                        const struct tmio_mmc_dma_ops *dma_ops)
 461 {
 462         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 463         const struct renesas_sdhi_of_data *of_data;
 464         struct tmio_mmc_data *mmc_data;
 465         struct tmio_mmc_dma *dma_priv;
 466         struct tmio_mmc_host *host;
 467         struct renesas_sdhi *priv;
 468         struct resource *res;
 469         int irq, ret, i;
 470
 471         of_data = of_device_get_match_data(&pdev->dev);
 472
 473         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 474         if (!res)
 475                 return -EINVAL;
 476
 477         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 478                             GFP_KERNEL);
 479         if (!priv)
 480                 return -ENOMEM;
 481
 482         mmc_data = &priv->mmc_data;
 483         dma_priv = &priv->dma_priv;
 484
 485         priv->clk = devm_clk_get(&pdev->dev, NULL);
 486         if (IS_ERR(priv->clk)) {
 487                 ret = PTR_ERR(priv->clk);
 488                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 489                 return ret;
 490         }
 491
 492         /*
 493          * Some controllers provide a 2nd clock just to run the internal card
 494          * detection logic. Unfortunately, the existing driver architecture does
 495          * not support a separation of clocks for runtime PM usage. When
 496          * native hotplug is used, the tmio driver assumes that the core
 497          * must continue to run for card detect to stay active, so we cannot
 498          * disable it.
 499          * Additionally, it is prohibited to supply a clock to the core but not
 500          * to the card detect circuit. That leaves us with if separate clocks
 501          * are presented, we must treat them both as virtually 1 clock.
 502          */
 503         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 504         if (IS_ERR(priv->clk_cd))
 505                 priv->clk_cd = NULL;
 506
 507         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 508         if (!IS_ERR(priv->pinctrl)) {
 509                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 510                                                 PINCTRL_STATE_DEFAULT);
 511                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 512                                                 "state_uhs");
 513         }
 514
 515         host = tmio_mmc_host_alloc(pdev, mmc_data);
 516         if (IS_ERR(host))
 517                 return PTR_ERR(host);
 518
 519         if (of_data) {
 520                 mmc_data->flags |= of_data->tmio_flags;
 521                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 522                 mmc_data->capabilities |= of_data->capabilities;
 523                 mmc_data->capabilities2 |= of_data->capabilities2;
 524                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 525                 mmc_data->max_blk_count = of_data->max_blk_count;
 526                 mmc_data->max_segs = of_data->max_segs;
 527                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 528                 host->bus_shift = of_data->bus_shift;
 529         }
 530
 531         host->write16_hook      = renesas_sdhi_write16_hook;
 532         host->clk_enable        = renesas_sdhi_clk_enable;
 533         host->clk_update        = renesas_sdhi_clk_update;
 534         host->clk_disable       = renesas_sdhi_clk_disable;
 535         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 536         host->dma_ops           = dma_ops;
 537
 538         /* For some SoC, we disable internal WP. GPIO may override this */
 539         if (mmc_can_gpio_ro(host->mmc))
 540                 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
 541
 542         /* SDR speeds are only available on Gen2+ */
 543         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 544                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 545                 host->ops.card_busy = renesas_sdhi_card_busy;
 546                 host->ops.start_signal_voltage_switch =
 547                         renesas_sdhi_start_signal_voltage_switch;
 548         }
 549
 550         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 551         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 552                 host->bus_shift = 1;
 553
 554         if (mmd)
 555                 *mmc_data = *mmd;
 556
 557         dma_priv->filter = shdma_chan_filter;
 558         dma_priv->enable = renesas_sdhi_enable_dma;
 559
 560         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 561         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 562
 563         /*
 564          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 565          * bus width mode.
 566          */
 567         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 568
 569         /*
 570          * All SDHI blocks support SDIO IRQ signalling.
 571          */
 572         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 573
 574         /* All SDHI have CMD12 control bit */
 575         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 576
 577         /* All SDHI have SDIO status bits which must be 1 */
 578         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 579
 580         ret = renesas_sdhi_clk_enable(host);
 581         if (ret)
 582                 goto efree;
 583
 584         ret = tmio_mmc_host_probe(host);
 585         if (ret < 0)
 586                 goto edisclk;
 587
 588         /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
 589         if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50)
 590                 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
 591
 592         /* Enable tuning iff we have an SCC and a supported mode */
 593         if (of_data && of_data->scc_offset &&
 594             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 595              host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) {
 596                 const struct renesas_sdhi_scc *taps = of_data->taps;
 597                 bool hit = false;
 598
 599                 host->mmc->caps |= MMC_CAP_HW_RESET;
 600
 601                 for (i = 0; i < of_data->taps_num; i++) {
 602                         if (taps[i].clk_rate == 0 ||
 603                             taps[i].clk_rate == host->mmc->f_max) {
 604                                 priv->scc_tappos = taps->tap;
 605                                 hit = true;
 606                                 break;
 607                         }
 608                 }
 609
 610                 if (!hit)
 611                         dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
 612
 613                 priv->scc_ctl = host->ctl + of_data->scc_offset;
 614                 host->init_tuning = renesas_sdhi_init_tuning;
 615                 host->prepare_tuning = renesas_sdhi_prepare_tuning;
 616                 host->select_tuning = renesas_sdhi_select_tuning;
 617                 host->check_scc_error = renesas_sdhi_check_scc_error;
 618                 host->hw_reset = renesas_sdhi_hw_reset;
 619         }
 620
 621         i = 0;
 622         while (1) {
 623                 irq = platform_get_irq(pdev, i);
 624                 if (irq < 0)
 625                         break;
 626                 i++;
 627                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 628                                        dev_name(&pdev->dev), host);
 629                 if (ret)
 630                         goto eirq;
 631         }
 632
 633         /* There must be at least one IRQ source */
 634         if (!i) {
 635                 ret = irq;
 636                 goto eirq;
 637         }
 638
 639         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 640                  mmc_hostname(host->mmc), (unsigned long)
 641                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 642                  host->mmc->f_max / 1000000);
 643
 644         return ret;
 645
 646 eirq:
 647         tmio_mmc_host_remove(host);
 648 edisclk:
 649         renesas_sdhi_clk_disable(host);
 650 efree:
 651         tmio_mmc_host_free(host);
 652
 653         return ret;
 654 }
 655 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
 656
 657 int renesas_sdhi_remove(struct platform_device *pdev)
 658 {
 659         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
 660
 661         tmio_mmc_host_remove(host);
 662         renesas_sdhi_clk_disable(host);
 663
 664         return 0;
 665 }
 666 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
 667
 668 MODULE_LICENSE("GPL v2");