include/media/omap3isp.h

   1 /*
   2  * omap3isp.h
   3  *
   4  * TI OMAP3 ISP - Platform data
   5  *
   6  * Copyright (C) 2011 Nokia Corporation
   7  *
   8  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   9  *           Sakari Ailus <sakari.ailus@iki.fi>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23  * 02110-1301 USA
  24  */
  25
  26 #ifndef __MEDIA_OMAP3ISP_H__
  27 #define __MEDIA_OMAP3ISP_H__
  28
  29 struct i2c_board_info;
  30 struct isp_device;
  31
  32 #define ISP_XCLK_NONE                   0
  33 #define ISP_XCLK_A                      1
  34 #define ISP_XCLK_B                      2
  35
  36 enum isp_interface_type {
  37         ISP_INTERFACE_PARALLEL,
  38         ISP_INTERFACE_CSI2A_PHY2,
  39         ISP_INTERFACE_CCP2B_PHY1,
  40         ISP_INTERFACE_CCP2B_PHY2,
  41         ISP_INTERFACE_CSI2C_PHY1,
  42 };
  43
  44 enum {
  45         ISP_BRIDGE_DISABLE = 0,
  46         ISP_BRIDGE_LITTLE_ENDIAN = 2,
  47         ISP_BRIDGE_BIG_ENDIAN = 3,
  48 };
  49
  50 enum {
  51         ISP_LANE_SHIFT_0 = 0,
  52         ISP_LANE_SHIFT_2 = 1,
  53         ISP_LANE_SHIFT_4 = 2,
  54         ISP_LANE_SHIFT_6 = 3,
  55 };
  56
  57 /**
  58  * struct isp_parallel_platform_data - Parallel interface platform data
  59  * @data_lane_shift: Data lane shifter
  60  *              ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
  61  *              ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
  62  *              ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
  63  *              ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
  64  * @clk_pol: Pixel clock polarity
  65  *              0 - Sample on rising edge, 1 - Sample on falling edge
  66  * @hs_pol: Horizontal synchronization polarity
  67  *              0 - Active high, 1 - Active low
  68  * @vs_pol: Vertical synchronization polarity
  69  *              0 - Active high, 1 - Active low
  70  * @bridge: CCDC Bridge input control
  71  *              ISP_BRIDGE_DISABLE - Disable
  72  *              ISP_BRIDGE_LITTLE_ENDIAN - Little endian
  73  *              ISP_BRIDGE_BIG_ENDIAN - Big endian
  74  */
  75 struct isp_parallel_platform_data {
  76         unsigned int data_lane_shift:2;
  77         unsigned int clk_pol:1;
  78         unsigned int hs_pol:1;
  79         unsigned int vs_pol:1;
  80         unsigned int bridge:2;
  81 };
  82
  83 enum {
  84         ISP_CCP2_PHY_DATA_CLOCK = 0,
  85         ISP_CCP2_PHY_DATA_STROBE = 1,
  86 };
  87
  88 enum {
  89         ISP_CCP2_MODE_MIPI = 0,
  90         ISP_CCP2_MODE_CCP2 = 1,
  91 };
  92
  93 /**
  94  * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
  95  * @pos: position of the lane
  96  * @pol: polarity of the lane
  97  */
  98 struct isp_csiphy_lane {
  99         u8 pos;
 100         u8 pol;
 101 };
 102
 103 #define ISP_CSIPHY1_NUM_DATA_LANES      1
 104 #define ISP_CSIPHY2_NUM_DATA_LANES      2
 105
 106 /**
 107  * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
 108  * @data: Configuration of one or two data lanes
 109  * @clk: Clock lane configuration
 110  */
 111 struct isp_csiphy_lanes_cfg {
 112         struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
 113         struct isp_csiphy_lane clk;
 114 };
 115
 116 /**
 117  * struct isp_ccp2_platform_data - CCP2 interface platform data
 118  * @strobe_clk_pol: Strobe/clock polarity
 119  *              0 - Non Inverted, 1 - Inverted
 120  * @crc: Enable the cyclic redundancy check
 121  * @ccp2_mode: Enable CCP2 compatibility mode
 122  *              ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
 123  *              ISP_CCP2_MODE_CCP2 - CCP2 mode
 124  * @phy_layer: Physical layer selection
 125  *              ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
 126  *              ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
 127  * @vpclk_div: Video port output clock control
 128  */
 129 struct isp_ccp2_platform_data {
 130         unsigned int strobe_clk_pol:1;
 131         unsigned int crc:1;
 132         unsigned int ccp2_mode:1;
 133         unsigned int phy_layer:1;
 134         unsigned int vpclk_div:2;
 135         struct isp_csiphy_lanes_cfg lanecfg;
 136 };
 137
 138 /**
 139  * struct isp_csi2_platform_data - CSI2 interface platform data
 140  * @crc: Enable the cyclic redundancy check
 141  * @vpclk_div: Video port output clock control
 142  */
 143 struct isp_csi2_platform_data {
 144         unsigned crc:1;
 145         unsigned vpclk_div:2;
 146         struct isp_csiphy_lanes_cfg lanecfg;
 147 };
 148
 149 struct isp_subdev_i2c_board_info {
 150         struct i2c_board_info *board_info;
 151         int i2c_adapter_id;
 152 };
 153
 154 struct isp_v4l2_subdevs_group {
 155         struct isp_subdev_i2c_board_info *subdevs;
 156         enum isp_interface_type interface;
 157         union {
 158                 struct isp_parallel_platform_data parallel;
 159                 struct isp_ccp2_platform_data ccp2;
 160                 struct isp_csi2_platform_data csi2;
 161         } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
 162 };
 163
 164 struct isp_platform_data {
 165         struct isp_v4l2_subdevs_group *subdevs;
 166         void (*set_constraints)(struct isp_device *isp, bool enable);
 167 };
 168
 169 #endif  /* __MEDIA_OMAP3ISP_H__ */