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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / gpu / drm / exynos / exynos5433_drm_decon.c
blobaef487dd873153d77fd602726ab6bd92256ab593
1 /* drivers/gpu/drm/exynos5433_drm_decon.c
2 *
3 * Copyright (C) 2015 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Hyungwon Hwang <human.hwang@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundationr
11 */
12
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/iopoll.h>
17 #include <linux/irq.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23
24 #include "exynos_drm_drv.h"
25 #include "exynos_drm_crtc.h"
26 #include "exynos_drm_fb.h"
27 #include "exynos_drm_plane.h"
28 #include "exynos_drm_iommu.h"
29 #include "regs-decon5433.h"
30
31 #define DSD_CFG_MUX 0x1004
32 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
33
34 #define WINDOWS_NR 5
35 #define PRIMARY_WIN 2
36 #define CURSON_WIN 4
37
38 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
39
40 #define I80_HW_TRG (1 << 0)
41 #define IFTYPE_HDMI (1 << 1)
42
43 static const char * const decon_clks_name[] = {
44 "pclk",
45 "aclk_decon",
46 "aclk_smmu_decon0x",
47 "aclk_xiu_decon0x",
48 "pclk_smmu_decon0x",
49 "aclk_smmu_decon1x",
50 "aclk_xiu_decon1x",
51 "pclk_smmu_decon1x",
52 "sclk_decon_vclk",
53 "sclk_decon_eclk",
54 };
55
56 struct decon_context {
57 struct device *dev;
58 struct drm_device *drm_dev;
59 struct exynos_drm_crtc *crtc;
60 struct exynos_drm_plane planes[WINDOWS_NR];
61 struct exynos_drm_plane_config configs[WINDOWS_NR];
62 void __iomem *addr;
63 struct regmap *sysreg;
64 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
65 unsigned int irq;
66 unsigned int irq_vsync;
67 unsigned int irq_lcd_sys;
68 unsigned int te_irq;
69 unsigned long out_type;
70 int first_win;
71 spinlock_t vblank_lock;
72 u32 frame_id;
73 };
74
75 static const uint32_t decon_formats[] = {
76 DRM_FORMAT_XRGB1555,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
83 [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
84 [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
85 };
86
87 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
88 u32 val)
89 {
90 val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
91 writel(val, ctx->addr + reg);
92 }
93
94 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
95 {
96 struct decon_context *ctx = crtc->ctx;
97 u32 val;
98
99 val = VIDINTCON0_INTEN;
100 if (crtc->i80_mode)
101 val |= VIDINTCON0_FRAMEDONE;
102 else
103 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
104
105 writel(val, ctx->addr + DECON_VIDINTCON0);
106
107 enable_irq(ctx->irq);
108 if (!(ctx->out_type & I80_HW_TRG))
109 enable_irq(ctx->te_irq);
110
111 return 0;
112 }
113
114 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
115 {
116 struct decon_context *ctx = crtc->ctx;
117
118 if (!(ctx->out_type & I80_HW_TRG))
119 disable_irq_nosync(ctx->te_irq);
120 disable_irq_nosync(ctx->irq);
121
122 writel(0, ctx->addr + DECON_VIDINTCON0);
123 }
124
125 /* return number of starts/ends of frame transmissions since reset */
126 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
127 {
128 u32 frm, pfrm, status, cnt = 2;
129
130 /* To get consistent result repeat read until frame id is stable.
131 * Usually the loop will be executed once, in rare cases when the loop
132 * is executed at frame change time 2nd pass will be needed.
133 */
134 frm = readl(ctx->addr + DECON_CRFMID);
135 do {
136 status = readl(ctx->addr + DECON_VIDCON1);
137 pfrm = frm;
138 frm = readl(ctx->addr + DECON_CRFMID);
139 } while (frm != pfrm && --cnt);
140
141 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
142 * of RGB, it should be taken into account.
143 */
144 if (!frm)
145 return 0;
146
147 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
148 case VIDCON1_VSTATUS_VS:
149 if (!(ctx->crtc->i80_mode))
150 --frm;
151 break;
152 case VIDCON1_VSTATUS_BP:
153 --frm;
154 break;
155 case VIDCON1_I80_ACTIVE:
156 case VIDCON1_VSTATUS_AC:
157 if (end)
158 --frm;
159 break;
160 default:
161 break;
162 }
163
164 return frm;
165 }
166
167 static void decon_setup_trigger(struct decon_context *ctx)
168 {
169 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
170 return;
171
172 if (!(ctx->out_type & I80_HW_TRG)) {
173 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
174 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
175 ctx->addr + DECON_TRIGCON);
176 return;
177 }
178
179 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
180 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
181
182 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
183 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
184 DRM_ERROR("Cannot update sysreg.\n");
185 }
186
187 static void decon_commit(struct exynos_drm_crtc *crtc)
188 {
189 struct decon_context *ctx = crtc->ctx;
190 struct drm_display_mode *m = &crtc->base.mode;
191 bool interlaced = false;
192 u32 val;
193
194 if (ctx->out_type & IFTYPE_HDMI) {
195 m->crtc_hsync_start = m->crtc_hdisplay + 10;
196 m->crtc_hsync_end = m->crtc_htotal - 92;
197 m->crtc_vsync_start = m->crtc_vdisplay + 1;
198 m->crtc_vsync_end = m->crtc_vsync_start + 1;
199 if (m->flags & DRM_MODE_FLAG_INTERLACE)
200 interlaced = true;
201 }
202
203 decon_setup_trigger(ctx);
204
205 /* lcd on and use command if */
206 val = VIDOUT_LCD_ON;
207 if (interlaced)
208 val |= VIDOUT_INTERLACE_EN_F;
209 if (crtc->i80_mode) {
210 val |= VIDOUT_COMMAND_IF;
211 } else {
212 val |= VIDOUT_RGB_IF;
213 }
214
215 writel(val, ctx->addr + DECON_VIDOUTCON0);
216
217 if (interlaced)
218 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
219 VIDTCON2_HOZVAL(m->hdisplay - 1);
220 else
221 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
222 VIDTCON2_HOZVAL(m->hdisplay - 1);
223 writel(val, ctx->addr + DECON_VIDTCON2);
224
225 if (!crtc->i80_mode) {
226 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
227 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
228
229 if (interlaced)
230 vbp = vbp / 2 - 1;
231 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
232 writel(val, ctx->addr + DECON_VIDTCON00);
233
234 val = VIDTCON01_VSPW_F(
235 m->crtc_vsync_end - m->crtc_vsync_start - 1);
236 writel(val, ctx->addr + DECON_VIDTCON01);
237
238 val = VIDTCON10_HBPD_F(
239 m->crtc_htotal - m->crtc_hsync_end - 1) |
240 VIDTCON10_HFPD_F(
241 m->crtc_hsync_start - m->crtc_hdisplay - 1);
242 writel(val, ctx->addr + DECON_VIDTCON10);
243
244 val = VIDTCON11_HSPW_F(
245 m->crtc_hsync_end - m->crtc_hsync_start - 1);
246 writel(val, ctx->addr + DECON_VIDTCON11);
247 }
248
249 /* enable output and display signal */
250 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
251
252 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
253 }
254
255 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
256 struct drm_framebuffer *fb)
257 {
258 unsigned long val;
259
260 val = readl(ctx->addr + DECON_WINCONx(win));
261 val &= WINCONx_ENWIN_F;
262
263 switch (fb->format->format) {
264 case DRM_FORMAT_XRGB1555:
265 val |= WINCONx_BPPMODE_16BPP_I1555;
266 val |= WINCONx_HAWSWP_F;
267 val |= WINCONx_BURSTLEN_16WORD;
268 break;
269 case DRM_FORMAT_RGB565:
270 val |= WINCONx_BPPMODE_16BPP_565;
271 val |= WINCONx_HAWSWP_F;
272 val |= WINCONx_BURSTLEN_16WORD;
273 break;
274 case DRM_FORMAT_XRGB8888:
275 val |= WINCONx_BPPMODE_24BPP_888;
276 val |= WINCONx_WSWP_F;
277 val |= WINCONx_BURSTLEN_16WORD;
278 break;
279 case DRM_FORMAT_ARGB8888:
280 default:
281 val |= WINCONx_BPPMODE_32BPP_A8888;
282 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
283 val |= WINCONx_BURSTLEN_16WORD;
284 break;
285 }
286
287 DRM_DEBUG_KMS("cpp = %u\n", fb->format->cpp[0]);
288
289 /*
290 * In case of exynos, setting dma-burst to 16Word causes permanent
291 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
292 * switching which is based on plane size is not recommended as
293 * plane size varies a lot towards the end of the screen and rapid
294 * movement causes unstable DMA which results into iommu crash/tear.
295 */
296
297 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
298 val &= ~WINCONx_BURSTLEN_MASK;
299 val |= WINCONx_BURSTLEN_8WORD;
300 }
301
302 writel(val, ctx->addr + DECON_WINCONx(win));
303 }
304
305 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
306 {
307 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
308 protect ? ~0 : 0);
309 }
310
311 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
312 {
313 struct decon_context *ctx = crtc->ctx;
314
315 decon_shadow_protect(ctx, true);
316 }
317
318 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
319 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
320 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
321
322 static void decon_update_plane(struct exynos_drm_crtc *crtc,
323 struct exynos_drm_plane *plane)
324 {
325 struct exynos_drm_plane_state *state =
326 to_exynos_plane_state(plane->base.state);
327 struct decon_context *ctx = crtc->ctx;
328 struct drm_framebuffer *fb = state->base.fb;
329 unsigned int win = plane->index;
330 unsigned int cpp = fb->format->cpp[0];
331 unsigned int pitch = fb->pitches[0];
332 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
333 u32 val;
334
335 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
336 val = COORDINATE_X(state->crtc.x) |
337 COORDINATE_Y(state->crtc.y / 2);
338 writel(val, ctx->addr + DECON_VIDOSDxA(win));
339
340 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
341 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
342 writel(val, ctx->addr + DECON_VIDOSDxB(win));
343 } else {
344 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
345 writel(val, ctx->addr + DECON_VIDOSDxA(win));
346
347 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
348 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
349 writel(val, ctx->addr + DECON_VIDOSDxB(win));
350 }
351
352 val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
353 VIDOSD_Wx_ALPHA_B_F(0xff);
354 writel(val, ctx->addr + DECON_VIDOSDxC(win));
355
356 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
357 VIDOSD_Wx_ALPHA_B_F(0x0);
358 writel(val, ctx->addr + DECON_VIDOSDxD(win));
359
360 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
361
362 val = dma_addr + pitch * state->src.h;
363 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
364
365 if (!(ctx->out_type & IFTYPE_HDMI))
366 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
367 | BIT_VAL(state->crtc.w * cpp, 13, 0);
368 else
369 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
370 | BIT_VAL(state->crtc.w * cpp, 14, 0);
371 writel(val, ctx->addr + DECON_VIDW0xADD2(win));
372
373 decon_win_set_pixfmt(ctx, win, fb);
374
375 /* window enable */
376 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
377 }
378
379 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
380 struct exynos_drm_plane *plane)
381 {
382 struct decon_context *ctx = crtc->ctx;
383 unsigned int win = plane->index;
384
385 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
386 }
387
388 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
389 {
390 struct decon_context *ctx = crtc->ctx;
391 unsigned long flags;
392
393 spin_lock_irqsave(&ctx->vblank_lock, flags);
394
395 decon_shadow_protect(ctx, false);
396
397 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
398
399 ctx->frame_id = decon_get_frame_count(ctx, true);
400
401 exynos_crtc_handle_event(crtc);
402
403 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
404 }
405
406 static void decon_swreset(struct decon_context *ctx)
407 {
408 unsigned long flags;
409 u32 val;
410 int ret;
411
412 writel(0, ctx->addr + DECON_VIDCON0);
413 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
414 ~val & VIDCON0_STOP_STATUS, 12, 20000);
415
416 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
417 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
418 ~val & VIDCON0_SWRESET, 12, 20000);
419
420 WARN(ret < 0, "failed to software reset DECON\n");
421
422 spin_lock_irqsave(&ctx->vblank_lock, flags);
423 ctx->frame_id = 0;
424 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
425
426 if (!(ctx->out_type & IFTYPE_HDMI))
427 return;
428
429 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
430 decon_set_bits(ctx, DECON_CMU,
431 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
432 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
433 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
434 ctx->addr + DECON_CRCCTRL);
435 }
436
437 static void decon_enable(struct exynos_drm_crtc *crtc)
438 {
439 struct decon_context *ctx = crtc->ctx;
440
441 pm_runtime_get_sync(ctx->dev);
442
443 exynos_drm_pipe_clk_enable(crtc, true);
444
445 decon_swreset(ctx);
446
447 decon_commit(ctx->crtc);
448 }
449
450 static void decon_disable(struct exynos_drm_crtc *crtc)
451 {
452 struct decon_context *ctx = crtc->ctx;
453 int i;
454
455 if (!(ctx->out_type & I80_HW_TRG))
456 synchronize_irq(ctx->te_irq);
457 synchronize_irq(ctx->irq);
458
459 /*
460 * We need to make sure that all windows are disabled before we
461 * suspend that connector. Otherwise we might try to scan from
462 * a destroyed buffer later.
463 */
464 for (i = ctx->first_win; i < WINDOWS_NR; i++)
465 decon_disable_plane(crtc, &ctx->planes[i]);
466
467 decon_swreset(ctx);
468
469 exynos_drm_pipe_clk_enable(crtc, false);
470
471 pm_runtime_put_sync(ctx->dev);
472 }
473
474 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
475 {
476 struct decon_context *ctx = dev_id;
477
478 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
479
480 return IRQ_HANDLED;
481 }
482
483 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
484 {
485 struct decon_context *ctx = crtc->ctx;
486 int win, i, ret;
487
488 DRM_DEBUG_KMS("%s\n", __FILE__);
489
490 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
491 ret = clk_prepare_enable(ctx->clks[i]);
492 if (ret < 0)
493 goto err;
494 }
495
496 decon_shadow_protect(ctx, true);
497 for (win = 0; win < WINDOWS_NR; win++)
498 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
499 decon_shadow_protect(ctx, false);
500
501 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
502
503 /* TODO: wait for possible vsync */
504 msleep(50);
505
506 err:
507 while (--i >= 0)
508 clk_disable_unprepare(ctx->clks[i]);
509 }
510
511 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
512 const struct drm_display_mode *mode)
513 {
514 struct decon_context *ctx = crtc->ctx;
515
516 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
517
518 if (ctx->irq)
519 return MODE_OK;
520
521 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
522 crtc->i80_mode ? "command" : "video");
523
524 return MODE_BAD;
525 }
526
527 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
528 .enable = decon_enable,
529 .disable = decon_disable,
530 .enable_vblank = decon_enable_vblank,
531 .disable_vblank = decon_disable_vblank,
532 .atomic_begin = decon_atomic_begin,
533 .update_plane = decon_update_plane,
534 .disable_plane = decon_disable_plane,
535 .mode_valid = decon_mode_valid,
536 .atomic_flush = decon_atomic_flush,
537 };
538
539 static int decon_bind(struct device *dev, struct device *master, void *data)
540 {
541 struct decon_context *ctx = dev_get_drvdata(dev);
542 struct drm_device *drm_dev = data;
543 struct exynos_drm_plane *exynos_plane;
544 enum exynos_drm_output_type out_type;
545 unsigned int win;
546 int ret;
547
548 ctx->drm_dev = drm_dev;
549
550 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
551 ctx->configs[win].pixel_formats = decon_formats;
552 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
553 ctx->configs[win].zpos = win - ctx->first_win;
554 ctx->configs[win].type = decon_win_types[win];
555
556 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
557 &ctx->configs[win]);
558 if (ret)
559 return ret;
560 }
561
562 exynos_plane = &ctx->planes[PRIMARY_WIN];
563 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
564 : EXYNOS_DISPLAY_TYPE_LCD;
565 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
566 out_type, &decon_crtc_ops, ctx);
567 if (IS_ERR(ctx->crtc))
568 return PTR_ERR(ctx->crtc);
569
570 decon_clear_channels(ctx->crtc);
571
572 return drm_iommu_attach_device(drm_dev, dev);
573 }
574
575 static void decon_unbind(struct device *dev, struct device *master, void *data)
576 {
577 struct decon_context *ctx = dev_get_drvdata(dev);
578
579 decon_disable(ctx->crtc);
580
581 /* detach this sub driver from iommu mapping if supported. */
582 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
583 }
584
585 static const struct component_ops decon_component_ops = {
586 .bind = decon_bind,
587 .unbind = decon_unbind,
588 };
589
590 static void decon_handle_vblank(struct decon_context *ctx)
591 {
592 u32 frm;
593
594 spin_lock(&ctx->vblank_lock);
595
596 frm = decon_get_frame_count(ctx, true);
597
598 if (frm != ctx->frame_id) {
599 /* handle only if incremented, take care of wrap-around */
600 if ((s32)(frm - ctx->frame_id) > 0)
601 drm_crtc_handle_vblank(&ctx->crtc->base);
602 ctx->frame_id = frm;
603 }
604
605 spin_unlock(&ctx->vblank_lock);
606 }
607
608 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
609 {
610 struct decon_context *ctx = dev_id;
611 u32 val;
612
613 val = readl(ctx->addr + DECON_VIDINTCON1);
614 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
615
616 if (val) {
617 writel(val, ctx->addr + DECON_VIDINTCON1);
618 if (ctx->out_type & IFTYPE_HDMI) {
619 val = readl(ctx->addr + DECON_VIDOUTCON0);
620 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
621 if (val ==
622 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
623 return IRQ_HANDLED;
624 }
625 decon_handle_vblank(ctx);
626 }
627
628 return IRQ_HANDLED;
629 }
630
631 #ifdef CONFIG_PM
632 static int exynos5433_decon_suspend(struct device *dev)
633 {
634 struct decon_context *ctx = dev_get_drvdata(dev);
635 int i = ARRAY_SIZE(decon_clks_name);
636
637 while (--i >= 0)
638 clk_disable_unprepare(ctx->clks[i]);
639
640 return 0;
641 }
642
643 static int exynos5433_decon_resume(struct device *dev)
644 {
645 struct decon_context *ctx = dev_get_drvdata(dev);
646 int i, ret;
647
648 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
649 ret = clk_prepare_enable(ctx->clks[i]);
650 if (ret < 0)
651 goto err;
652 }
653
654 return 0;
655
656 err:
657 while (--i >= 0)
658 clk_disable_unprepare(ctx->clks[i]);
659
660 return ret;
661 }
662 #endif
663
664 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
665 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
666 NULL)
667 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
668 pm_runtime_force_resume)
669 };
670
671 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
672 {
673 .compatible = "samsung,exynos5433-decon",
674 .data = (void *)I80_HW_TRG
675 },
676 {
677 .compatible = "samsung,exynos5433-decon-tv",
678 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
679 },
680 {},
681 };
682 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
683
684 static int decon_conf_irq(struct decon_context *ctx, const char *name,
685 irq_handler_t handler, unsigned long int flags)
686 {
687 struct platform_device *pdev = to_platform_device(ctx->dev);
688 int ret, irq = platform_get_irq_byname(pdev, name);
689
690 if (irq < 0) {
691 switch (irq) {
692 case -EPROBE_DEFER:
693 return irq;
694 case -ENODATA:
695 case -ENXIO:
696 return 0;
697 default:
698 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
699 return irq;
700 }
701 }
702 irq_set_status_flags(irq, IRQ_NOAUTOEN);
703 ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
704 if (ret < 0) {
705 dev_err(ctx->dev, "IRQ %s request failed\n", name);
706 return ret;
707 }
708
709 return irq;
710 }
711
712 static int exynos5433_decon_probe(struct platform_device *pdev)
713 {
714 struct device *dev = &pdev->dev;
715 struct decon_context *ctx;
716 struct resource *res;
717 int ret;
718 int i;
719
720 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
721 if (!ctx)
722 return -ENOMEM;
723
724 ctx->dev = dev;
725 ctx->out_type = (unsigned long)of_device_get_match_data(dev);
726 spin_lock_init(&ctx->vblank_lock);
727
728 if (ctx->out_type & IFTYPE_HDMI)
729 ctx->first_win = 1;
730
731 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
732 struct clk *clk;
733
734 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
735 if (IS_ERR(clk))
736 return PTR_ERR(clk);
737
738 ctx->clks[i] = clk;
739 }
740
741 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
742 ctx->addr = devm_ioremap_resource(dev, res);
743 if (IS_ERR(ctx->addr)) {
744 dev_err(dev, "ioremap failed\n");
745 return PTR_ERR(ctx->addr);
746 }
747
748 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
749 if (ret < 0)
750 return ret;
751 ctx->irq_vsync = ret;
752
753 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
754 if (ret < 0)
755 return ret;
756 ctx->irq_lcd_sys = ret;
757
758 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
759 IRQF_TRIGGER_RISING);
760 if (ret < 0)
761 return ret;
762 if (ret) {
763 ctx->te_irq = ret;
764 ctx->out_type &= ~I80_HW_TRG;
765 }
766
767 if (ctx->out_type & I80_HW_TRG) {
768 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
769 "samsung,disp-sysreg");
770 if (IS_ERR(ctx->sysreg)) {
771 dev_err(dev, "failed to get system register\n");
772 return PTR_ERR(ctx->sysreg);
773 }
774 }
775
776 platform_set_drvdata(pdev, ctx);
777
778 pm_runtime_enable(dev);
779
780 ret = component_add(dev, &decon_component_ops);
781 if (ret)
782 goto err_disable_pm_runtime;
783
784 return 0;
785
786 err_disable_pm_runtime:
787 pm_runtime_disable(dev);
788
789 return ret;
790 }
791
792 static int exynos5433_decon_remove(struct platform_device *pdev)
793 {
794 pm_runtime_disable(&pdev->dev);
795
796 component_del(&pdev->dev, &decon_component_ops);
797
798 return 0;
799 }
800
801 struct platform_driver exynos5433_decon_driver = {
802 .probe = exynos5433_decon_probe,
803 .remove = exynos5433_decon_remove,
804 .driver = {
805 .name = "exynos5433-decon",
806 .pm = &exynos5433_decon_pm_ops,
807 .of_match_table = exynos5433_decon_driver_dt_match,
808 },
809 };
Linux with added FPC-III support