drivers/gpu/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/component.h>
  26 #include <drm/i915_component.h>
  27 #include <drm/intel_lpe_audio.h>
  28 #include "intel_drv.h"
  29
  30 #include <drm/drmP.h>
  31 #include <drm/drm_edid.h>
  32 #include "i915_drv.h"
  33
  34 /**
  35  * DOC: High Definition Audio over HDMI and Display Port
  36  *
  37  * The graphics and audio drivers together support High Definition Audio over
  38  * HDMI and Display Port. The audio programming sequences are divided into audio
  39  * codec and controller enable and disable sequences. The graphics driver
  40  * handles the audio codec sequences, while the audio driver handles the audio
  41  * controller sequences.
  42  *
  43  * The disable sequences must be performed before disabling the transcoder or
  44  * port. The enable sequences may only be performed after enabling the
  45  * transcoder and port, and after completed link training. Therefore the audio
  46  * enable/disable sequences are part of the modeset sequence.
  47  *
  48  * The codec and controller sequences could be done either parallel or serial,
  49  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  50  * driver that the controller sequence should start. Indeed, most of the
  51  * co-operation between the graphics and audio drivers is handled via audio
  52  * related registers. (The notable exception is the power management, not
  53  * covered here.)
  54  *
  55  * The struct &i915_audio_component is used to interact between the graphics
  56  * and audio drivers. The struct &i915_audio_component_ops @ops in it is
  57  * defined in graphics driver and called in audio driver. The
  58  * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
  59  */
  60
  61 /* DP N/M table */
  62 #define LC_810M 810000
  63 #define LC_540M 540000
  64 #define LC_270M 270000
  65 #define LC_162M 162000
  66
  67 struct dp_aud_n_m {
  68         int sample_rate;
  69         int clock;
  70         u16 m;
  71         u16 n;
  72 };
  73
  74 /* Values according to DP 1.4 Table 2-104 */
  75 static const struct dp_aud_n_m dp_aud_n_m[] = {
  76         { 32000, LC_162M, 1024, 10125 },
  77         { 44100, LC_162M, 784, 5625 },
  78         { 48000, LC_162M, 512, 3375 },
  79         { 64000, LC_162M, 2048, 10125 },
  80         { 88200, LC_162M, 1568, 5625 },
  81         { 96000, LC_162M, 1024, 3375 },
  82         { 128000, LC_162M, 4096, 10125 },
  83         { 176400, LC_162M, 3136, 5625 },
  84         { 192000, LC_162M, 2048, 3375 },
  85         { 32000, LC_270M, 1024, 16875 },
  86         { 44100, LC_270M, 784, 9375 },
  87         { 48000, LC_270M, 512, 5625 },
  88         { 64000, LC_270M, 2048, 16875 },
  89         { 88200, LC_270M, 1568, 9375 },
  90         { 96000, LC_270M, 1024, 5625 },
  91         { 128000, LC_270M, 4096, 16875 },
  92         { 176400, LC_270M, 3136, 9375 },
  93         { 192000, LC_270M, 2048, 5625 },
  94         { 32000, LC_540M, 1024, 33750 },
  95         { 44100, LC_540M, 784, 18750 },
  96         { 48000, LC_540M, 512, 11250 },
  97         { 64000, LC_540M, 2048, 33750 },
  98         { 88200, LC_540M, 1568, 18750 },
  99         { 96000, LC_540M, 1024, 11250 },
 100         { 128000, LC_540M, 4096, 33750 },
 101         { 176400, LC_540M, 3136, 18750 },
 102         { 192000, LC_540M, 2048, 11250 },
 103         { 32000, LC_810M, 1024, 50625 },
 104         { 44100, LC_810M, 784, 28125 },
 105         { 48000, LC_810M, 512, 16875 },
 106         { 64000, LC_810M, 2048, 50625 },
 107         { 88200, LC_810M, 1568, 28125 },
 108         { 96000, LC_810M, 1024, 16875 },
 109         { 128000, LC_810M, 4096, 50625 },
 110         { 176400, LC_810M, 3136, 28125 },
 111         { 192000, LC_810M, 2048, 16875 },
 112 };
 113
 114 static const struct dp_aud_n_m *
 115 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
 116 {
 117         int i;
 118
 119         for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
 120                 if (rate == dp_aud_n_m[i].sample_rate &&
 121                     crtc_state->port_clock == dp_aud_n_m[i].clock)
 122                         return &dp_aud_n_m[i];
 123         }
 124
 125         return NULL;
 126 }
 127
 128 static const struct {
 129         int clock;
 130         u32 config;
 131 } hdmi_audio_clock[] = {
 132         { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
 133         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
 134         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
 135         { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
 136         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
 137         { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
 138         { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
 139         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
 140         { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
 141         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
 142 };
 143
 144 /* HDMI N/CTS table */
 145 #define TMDS_297M 297000
 146 #define TMDS_296M 296703
 147 #define TMDS_594M 594000
 148 #define TMDS_593M 593407
 149
 150 static const struct {
 151         int sample_rate;
 152         int clock;
 153         int n;
 154         int cts;
 155 } hdmi_aud_ncts[] = {
 156         { 44100, TMDS_296M, 4459, 234375 },
 157         { 44100, TMDS_297M, 4704, 247500 },
 158         { 48000, TMDS_296M, 5824, 281250 },
 159         { 48000, TMDS_297M, 5120, 247500 },
 160         { 32000, TMDS_296M, 5824, 421875 },
 161         { 32000, TMDS_297M, 3072, 222750 },
 162         { 88200, TMDS_296M, 8918, 234375 },
 163         { 88200, TMDS_297M, 9408, 247500 },
 164         { 96000, TMDS_296M, 11648, 281250 },
 165         { 96000, TMDS_297M, 10240, 247500 },
 166         { 176400, TMDS_296M, 17836, 234375 },
 167         { 176400, TMDS_297M, 18816, 247500 },
 168         { 192000, TMDS_296M, 23296, 281250 },
 169         { 192000, TMDS_297M, 20480, 247500 },
 170         { 44100, TMDS_593M, 8918, 937500 },
 171         { 44100, TMDS_594M, 9408, 990000 },
 172         { 48000, TMDS_593M, 5824, 562500 },
 173         { 48000, TMDS_594M, 6144, 594000 },
 174         { 32000, TMDS_593M, 5824, 843750 },
 175         { 32000, TMDS_594M, 3072, 445500 },
 176         { 88200, TMDS_593M, 17836, 937500 },
 177         { 88200, TMDS_594M, 18816, 990000 },
 178         { 96000, TMDS_593M, 11648, 562500 },
 179         { 96000, TMDS_594M, 12288, 594000 },
 180         { 176400, TMDS_593M, 35672, 937500 },
 181         { 176400, TMDS_594M, 37632, 990000 },
 182         { 192000, TMDS_593M, 23296, 562500 },
 183         { 192000, TMDS_594M, 24576, 594000 },
 184 };
 185
 186 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 187 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
 188 {
 189         const struct drm_display_mode *adjusted_mode =
 190                 &crtc_state->base.adjusted_mode;
 191         int i;
 192
 193         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 194                 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 195                         break;
 196         }
 197
 198         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 199                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 200                               adjusted_mode->crtc_clock);
 201                 i = 1;
 202         }
 203
 204         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 205                       hdmi_audio_clock[i].clock,
 206                       hdmi_audio_clock[i].config);
 207
 208         return hdmi_audio_clock[i].config;
 209 }
 210
 211 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
 212                                    int rate)
 213 {
 214         const struct drm_display_mode *adjusted_mode =
 215                 &crtc_state->base.adjusted_mode;
 216         int i;
 217
 218         for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
 219                 if (rate == hdmi_aud_ncts[i].sample_rate &&
 220                     adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
 221                         return hdmi_aud_ncts[i].n;
 222                 }
 223         }
 224         return 0;
 225 }
 226
 227 static bool intel_eld_uptodate(struct drm_connector *connector,
 228                                i915_reg_t reg_eldv, u32 bits_eldv,
 229                                i915_reg_t reg_elda, u32 bits_elda,
 230                                i915_reg_t reg_edid)
 231 {
 232         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 233         const u8 *eld = connector->eld;
 234         u32 tmp;
 235         int i;
 236
 237         tmp = I915_READ(reg_eldv);
 238         tmp &= bits_eldv;
 239
 240         if (!tmp)
 241                 return false;
 242
 243         tmp = I915_READ(reg_elda);
 244         tmp &= ~bits_elda;
 245         I915_WRITE(reg_elda, tmp);
 246
 247         for (i = 0; i < drm_eld_size(eld) / 4; i++)
 248                 if (I915_READ(reg_edid) != *((const u32 *)eld + i))
 249                         return false;
 250
 251         return true;
 252 }
 253
 254 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
 255                                     const struct intel_crtc_state *old_crtc_state,
 256                                     const struct drm_connector_state *old_conn_state)
 257 {
 258         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 259         u32 eldv, tmp;
 260
 261         DRM_DEBUG_KMS("Disable audio codec\n");
 262
 263         tmp = I915_READ(G4X_AUD_VID_DID);
 264         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 265                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 266         else
 267                 eldv = G4X_ELDV_DEVCTG;
 268
 269         /* Invalidate ELD */
 270         tmp = I915_READ(G4X_AUD_CNTL_ST);
 271         tmp &= ~eldv;
 272         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 273 }
 274
 275 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
 276                                    const struct intel_crtc_state *crtc_state,
 277                                    const struct drm_connector_state *conn_state)
 278 {
 279         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 280         struct drm_connector *connector = conn_state->connector;
 281         const u8 *eld = connector->eld;
 282         u32 eldv;
 283         u32 tmp;
 284         int len, i;
 285
 286         DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
 287
 288         tmp = I915_READ(G4X_AUD_VID_DID);
 289         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 290                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 291         else
 292                 eldv = G4X_ELDV_DEVCTG;
 293
 294         if (intel_eld_uptodate(connector,
 295                                G4X_AUD_CNTL_ST, eldv,
 296                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 297                                G4X_HDMIW_HDMIEDID))
 298                 return;
 299
 300         tmp = I915_READ(G4X_AUD_CNTL_ST);
 301         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 302         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 303         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 304
 305         len = min(drm_eld_size(eld) / 4, len);
 306         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 307         for (i = 0; i < len; i++)
 308                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
 309
 310         tmp = I915_READ(G4X_AUD_CNTL_ST);
 311         tmp |= eldv;
 312         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 313 }
 314
 315 static void
 316 hsw_dp_audio_config_update(struct intel_encoder *encoder,
 317                            const struct intel_crtc_state *crtc_state)
 318 {
 319         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 320         struct i915_audio_component *acomp = dev_priv->audio_component;
 321         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 322         enum port port = encoder->port;
 323         enum pipe pipe = crtc->pipe;
 324         const struct dp_aud_n_m *nm;
 325         int rate;
 326         u32 tmp;
 327
 328         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 329         nm = audio_config_dp_get_n_m(crtc_state, rate);
 330         if (nm)
 331                 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
 332         else
 333                 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
 334
 335         tmp = I915_READ(HSW_AUD_CFG(pipe));
 336         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 337         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 338         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 339         tmp |= AUD_CONFIG_N_VALUE_INDEX;
 340
 341         if (nm) {
 342                 tmp &= ~AUD_CONFIG_N_MASK;
 343                 tmp |= AUD_CONFIG_N(nm->n);
 344                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 345         }
 346
 347         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 348
 349         tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
 350         tmp &= ~AUD_CONFIG_M_MASK;
 351         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 352         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 353
 354         if (nm) {
 355                 tmp |= nm->m;
 356                 tmp |= AUD_M_CTS_M_VALUE_INDEX;
 357                 tmp |= AUD_M_CTS_M_PROG_ENABLE;
 358         }
 359
 360         I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
 361 }
 362
 363 static void
 364 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
 365                              const struct intel_crtc_state *crtc_state)
 366 {
 367         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 368         struct i915_audio_component *acomp = dev_priv->audio_component;
 369         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 370         enum port port = encoder->port;
 371         enum pipe pipe = crtc->pipe;
 372         int n, rate;
 373         u32 tmp;
 374
 375         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 376
 377         tmp = I915_READ(HSW_AUD_CFG(pipe));
 378         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 379         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 380         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 381         tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 382
 383         n = audio_config_hdmi_get_n(crtc_state, rate);
 384         if (n != 0) {
 385                 DRM_DEBUG_KMS("using N %d\n", n);
 386
 387                 tmp &= ~AUD_CONFIG_N_MASK;
 388                 tmp |= AUD_CONFIG_N(n);
 389                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 390         } else {
 391                 DRM_DEBUG_KMS("using automatic N\n");
 392         }
 393
 394         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 395
 396         /*
 397          * Let's disable "Enable CTS or M Prog bit"
 398          * and let HW calculate the value
 399          */
 400         tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
 401         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 402         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 403         I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
 404 }
 405
 406 static void
 407 hsw_audio_config_update(struct intel_encoder *encoder,
 408                         const struct intel_crtc_state *crtc_state)
 409 {
 410         if (intel_crtc_has_dp_encoder(crtc_state))
 411                 hsw_dp_audio_config_update(encoder, crtc_state);
 412         else
 413                 hsw_hdmi_audio_config_update(encoder, crtc_state);
 414 }
 415
 416 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
 417                                     const struct intel_crtc_state *old_crtc_state,
 418                                     const struct drm_connector_state *old_conn_state)
 419 {
 420         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 421         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 422         enum pipe pipe = crtc->pipe;
 423         u32 tmp;
 424
 425         DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
 426
 427         mutex_lock(&dev_priv->av_mutex);
 428
 429         /* Disable timestamps */
 430         tmp = I915_READ(HSW_AUD_CFG(pipe));
 431         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 432         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 433         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 434         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 435         if (intel_crtc_has_dp_encoder(old_crtc_state))
 436                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 437         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 438
 439         /* Invalidate ELD */
 440         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 441         tmp &= ~AUDIO_ELD_VALID(pipe);
 442         tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
 443         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 444
 445         mutex_unlock(&dev_priv->av_mutex);
 446 }
 447
 448 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
 449                                    const struct intel_crtc_state *crtc_state,
 450                                    const struct drm_connector_state *conn_state)
 451 {
 452         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 453         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 454         struct drm_connector *connector = conn_state->connector;
 455         enum pipe pipe = crtc->pipe;
 456         const u8 *eld = connector->eld;
 457         u32 tmp;
 458         int len, i;
 459
 460         DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
 461                       pipe_name(pipe), drm_eld_size(eld));
 462
 463         mutex_lock(&dev_priv->av_mutex);
 464
 465         /* Enable audio presence detect, invalidate ELD */
 466         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 467         tmp |= AUDIO_OUTPUT_ENABLE(pipe);
 468         tmp &= ~AUDIO_ELD_VALID(pipe);
 469         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 470
 471         /*
 472          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 473          * disabled during the mode set. The proper fix would be to push the
 474          * rest of the setup into a vblank work item, queued here, but the
 475          * infrastructure is not there yet.
 476          */
 477
 478         /* Reset ELD write address */
 479         tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
 480         tmp &= ~IBX_ELD_ADDRESS_MASK;
 481         I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
 482
 483         /* Up to 84 bytes of hw ELD buffer */
 484         len = min(drm_eld_size(eld), 84);
 485         for (i = 0; i < len / 4; i++)
 486                 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const u32 *)eld + i));
 487
 488         /* ELD valid */
 489         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 490         tmp |= AUDIO_ELD_VALID(pipe);
 491         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 492
 493         /* Enable timestamps */
 494         hsw_audio_config_update(encoder, crtc_state);
 495
 496         mutex_unlock(&dev_priv->av_mutex);
 497 }
 498
 499 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
 500                                     const struct intel_crtc_state *old_crtc_state,
 501                                     const struct drm_connector_state *old_conn_state)
 502 {
 503         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 504         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 505         enum pipe pipe = crtc->pipe;
 506         enum port port = encoder->port;
 507         u32 tmp, eldv;
 508         i915_reg_t aud_config, aud_cntrl_st2;
 509
 510         DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
 511                       port_name(port), pipe_name(pipe));
 512
 513         if (WARN_ON(port == PORT_A))
 514                 return;
 515
 516         if (HAS_PCH_IBX(dev_priv)) {
 517                 aud_config = IBX_AUD_CFG(pipe);
 518                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 519         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 520                 aud_config = VLV_AUD_CFG(pipe);
 521                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 522         } else {
 523                 aud_config = CPT_AUD_CFG(pipe);
 524                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 525         }
 526
 527         /* Disable timestamps */
 528         tmp = I915_READ(aud_config);
 529         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 530         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 531         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 532         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 533         if (intel_crtc_has_dp_encoder(old_crtc_state))
 534                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 535         I915_WRITE(aud_config, tmp);
 536
 537         eldv = IBX_ELD_VALID(port);
 538
 539         /* Invalidate ELD */
 540         tmp = I915_READ(aud_cntrl_st2);
 541         tmp &= ~eldv;
 542         I915_WRITE(aud_cntrl_st2, tmp);
 543 }
 544
 545 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
 546                                    const struct intel_crtc_state *crtc_state,
 547                                    const struct drm_connector_state *conn_state)
 548 {
 549         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 550         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 551         struct drm_connector *connector = conn_state->connector;
 552         enum pipe pipe = crtc->pipe;
 553         enum port port = encoder->port;
 554         const u8 *eld = connector->eld;
 555         u32 tmp, eldv;
 556         int len, i;
 557         i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 558
 559         DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
 560                       port_name(port), pipe_name(pipe), drm_eld_size(eld));
 561
 562         if (WARN_ON(port == PORT_A))
 563                 return;
 564
 565         /*
 566          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 567          * disabled during the mode set. The proper fix would be to push the
 568          * rest of the setup into a vblank work item, queued here, but the
 569          * infrastructure is not there yet.
 570          */
 571
 572         if (HAS_PCH_IBX(dev_priv)) {
 573                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 574                 aud_config = IBX_AUD_CFG(pipe);
 575                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 576                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 577         } else if (IS_VALLEYVIEW(dev_priv) ||
 578                    IS_CHERRYVIEW(dev_priv)) {
 579                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 580                 aud_config = VLV_AUD_CFG(pipe);
 581                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 582                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 583         } else {
 584                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 585                 aud_config = CPT_AUD_CFG(pipe);
 586                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 587                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 588         }
 589
 590         eldv = IBX_ELD_VALID(port);
 591
 592         /* Invalidate ELD */
 593         tmp = I915_READ(aud_cntrl_st2);
 594         tmp &= ~eldv;
 595         I915_WRITE(aud_cntrl_st2, tmp);
 596
 597         /* Reset ELD write address */
 598         tmp = I915_READ(aud_cntl_st);
 599         tmp &= ~IBX_ELD_ADDRESS_MASK;
 600         I915_WRITE(aud_cntl_st, tmp);
 601
 602         /* Up to 84 bytes of hw ELD buffer */
 603         len = min(drm_eld_size(eld), 84);
 604         for (i = 0; i < len / 4; i++)
 605                 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
 606
 607         /* ELD valid */
 608         tmp = I915_READ(aud_cntrl_st2);
 609         tmp |= eldv;
 610         I915_WRITE(aud_cntrl_st2, tmp);
 611
 612         /* Enable timestamps */
 613         tmp = I915_READ(aud_config);
 614         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 615         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 616         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 617         if (intel_crtc_has_dp_encoder(crtc_state))
 618                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 619         else
 620                 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 621         I915_WRITE(aud_config, tmp);
 622 }
 623
 624 /**
 625  * intel_audio_codec_enable - Enable the audio codec for HD audio
 626  * @encoder: encoder on which to enable audio
 627  * @crtc_state: pointer to the current crtc state.
 628  * @conn_state: pointer to the current connector state.
 629  *
 630  * The enable sequences may only be performed after enabling the transcoder and
 631  * port, and after completed link training.
 632  */
 633 void intel_audio_codec_enable(struct intel_encoder *encoder,
 634                               const struct intel_crtc_state *crtc_state,
 635                               const struct drm_connector_state *conn_state)
 636 {
 637         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 638         struct i915_audio_component *acomp = dev_priv->audio_component;
 639         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 640         struct drm_connector *connector = conn_state->connector;
 641         const struct drm_display_mode *adjusted_mode =
 642                 &crtc_state->base.adjusted_mode;
 643         enum port port = encoder->port;
 644         enum pipe pipe = crtc->pipe;
 645
 646         if (!connector->eld[0])
 647                 return;
 648
 649         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 650                          connector->base.id,
 651                          connector->name,
 652                          connector->encoder->base.id,
 653                          connector->encoder->name);
 654
 655         connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 656
 657         if (dev_priv->display.audio_codec_enable)
 658                 dev_priv->display.audio_codec_enable(encoder,
 659                                                      crtc_state,
 660                                                      conn_state);
 661
 662         mutex_lock(&dev_priv->av_mutex);
 663         encoder->audio_connector = connector;
 664
 665         /* referred in audio callbacks */
 666         dev_priv->av_enc_map[pipe] = encoder;
 667         mutex_unlock(&dev_priv->av_mutex);
 668
 669         if (acomp && acomp->base.audio_ops &&
 670             acomp->base.audio_ops->pin_eld_notify) {
 671                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 672                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 673                         pipe = -1;
 674                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 675                                                  (int) port, (int) pipe);
 676         }
 677
 678         intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
 679                                crtc_state->port_clock,
 680                                intel_crtc_has_dp_encoder(crtc_state));
 681 }
 682
 683 /**
 684  * intel_audio_codec_disable - Disable the audio codec for HD audio
 685  * @encoder: encoder on which to disable audio
 686  * @old_crtc_state: pointer to the old crtc state.
 687  * @old_conn_state: pointer to the old connector state.
 688  *
 689  * The disable sequences must be performed before disabling the transcoder or
 690  * port.
 691  */
 692 void intel_audio_codec_disable(struct intel_encoder *encoder,
 693                                const struct intel_crtc_state *old_crtc_state,
 694                                const struct drm_connector_state *old_conn_state)
 695 {
 696         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 697         struct i915_audio_component *acomp = dev_priv->audio_component;
 698         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 699         enum port port = encoder->port;
 700         enum pipe pipe = crtc->pipe;
 701
 702         if (dev_priv->display.audio_codec_disable)
 703                 dev_priv->display.audio_codec_disable(encoder,
 704                                                       old_crtc_state,
 705                                                       old_conn_state);
 706
 707         mutex_lock(&dev_priv->av_mutex);
 708         encoder->audio_connector = NULL;
 709         dev_priv->av_enc_map[pipe] = NULL;
 710         mutex_unlock(&dev_priv->av_mutex);
 711
 712         if (acomp && acomp->base.audio_ops &&
 713             acomp->base.audio_ops->pin_eld_notify) {
 714                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 715                 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
 716                         pipe = -1;
 717                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 718                                                  (int) port, (int) pipe);
 719         }
 720
 721         intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
 722 }
 723
 724 /**
 725  * intel_init_audio_hooks - Set up chip specific audio hooks
 726  * @dev_priv: device private
 727  */
 728 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 729 {
 730         if (IS_G4X(dev_priv)) {
 731                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 732                 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
 733         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 734                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 735                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 736         } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
 737                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 738                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 739         } else if (HAS_PCH_SPLIT(dev_priv)) {
 740                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 741                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 742         }
 743 }
 744
 745 static void i915_audio_component_get_power(struct device *kdev)
 746 {
 747         intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
 748 }
 749
 750 static void i915_audio_component_put_power(struct device *kdev)
 751 {
 752         intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
 753 }
 754
 755 static void i915_audio_component_codec_wake_override(struct device *kdev,
 756                                                      bool enable)
 757 {
 758         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 759         u32 tmp;
 760
 761         if (!IS_GEN9(dev_priv))
 762                 return;
 763
 764         i915_audio_component_get_power(kdev);
 765
 766         /*
 767          * Enable/disable generating the codec wake signal, overriding the
 768          * internal logic to generate the codec wake to controller.
 769          */
 770         tmp = I915_READ(HSW_AUD_CHICKENBIT);
 771         tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
 772         I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 773         usleep_range(1000, 1500);
 774
 775         if (enable) {
 776                 tmp = I915_READ(HSW_AUD_CHICKENBIT);
 777                 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
 778                 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 779                 usleep_range(1000, 1500);
 780         }
 781
 782         i915_audio_component_put_power(kdev);
 783 }
 784
 785 /* Get CDCLK in kHz  */
 786 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
 787 {
 788         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 789
 790         if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
 791                 return -ENODEV;
 792
 793         return dev_priv->cdclk.hw.cdclk;
 794 }
 795
 796 /*
 797  * get the intel_encoder according to the parameter port and pipe
 798  * intel_encoder is saved by the index of pipe
 799  * MST & (pipe >= 0): return the av_enc_map[pipe],
 800  *   when port is matched
 801  * MST & (pipe < 0): this is invalid
 802  * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
 803  *   will get the right intel_encoder with port matched
 804  * Non-MST & (pipe < 0): get the right intel_encoder with port matched
 805  */
 806 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
 807                                                int port, int pipe)
 808 {
 809         struct intel_encoder *encoder;
 810
 811         /* MST */
 812         if (pipe >= 0) {
 813                 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
 814                         return NULL;
 815
 816                 encoder = dev_priv->av_enc_map[pipe];
 817                 /*
 818                  * when bootup, audio driver may not know it is
 819                  * MST or not. So it will poll all the port & pipe
 820                  * combinations
 821                  */
 822                 if (encoder != NULL && encoder->port == port &&
 823                     encoder->type == INTEL_OUTPUT_DP_MST)
 824                         return encoder;
 825         }
 826
 827         /* Non-MST */
 828         if (pipe > 0)
 829                 return NULL;
 830
 831         for_each_pipe(dev_priv, pipe) {
 832                 encoder = dev_priv->av_enc_map[pipe];
 833                 if (encoder == NULL)
 834                         continue;
 835
 836                 if (encoder->type == INTEL_OUTPUT_DP_MST)
 837                         continue;
 838
 839                 if (port == encoder->port)
 840                         return encoder;
 841         }
 842
 843         return NULL;
 844 }
 845
 846 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
 847                                                 int pipe, int rate)
 848 {
 849         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 850         struct i915_audio_component *acomp = dev_priv->audio_component;
 851         struct intel_encoder *encoder;
 852         struct intel_crtc *crtc;
 853         int err = 0;
 854
 855         if (!HAS_DDI(dev_priv))
 856                 return 0;
 857
 858         i915_audio_component_get_power(kdev);
 859         mutex_lock(&dev_priv->av_mutex);
 860
 861         /* 1. get the pipe */
 862         encoder = get_saved_enc(dev_priv, port, pipe);
 863         if (!encoder || !encoder->base.crtc) {
 864                 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
 865                 err = -ENODEV;
 866                 goto unlock;
 867         }
 868
 869         crtc = to_intel_crtc(encoder->base.crtc);
 870
 871         /* port must be valid now, otherwise the pipe will be invalid */
 872         acomp->aud_sample_rate[port] = rate;
 873
 874         hsw_audio_config_update(encoder, crtc->config);
 875
 876  unlock:
 877         mutex_unlock(&dev_priv->av_mutex);
 878         i915_audio_component_put_power(kdev);
 879         return err;
 880 }
 881
 882 static int i915_audio_component_get_eld(struct device *kdev, int port,
 883                                         int pipe, bool *enabled,
 884                                         unsigned char *buf, int max_bytes)
 885 {
 886         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 887         struct intel_encoder *intel_encoder;
 888         const u8 *eld;
 889         int ret = -EINVAL;
 890
 891         mutex_lock(&dev_priv->av_mutex);
 892
 893         intel_encoder = get_saved_enc(dev_priv, port, pipe);
 894         if (!intel_encoder) {
 895                 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
 896                 mutex_unlock(&dev_priv->av_mutex);
 897                 return ret;
 898         }
 899
 900         ret = 0;
 901         *enabled = intel_encoder->audio_connector != NULL;
 902         if (*enabled) {
 903                 eld = intel_encoder->audio_connector->eld;
 904                 ret = drm_eld_size(eld);
 905                 memcpy(buf, eld, min(max_bytes, ret));
 906         }
 907
 908         mutex_unlock(&dev_priv->av_mutex);
 909         return ret;
 910 }
 911
 912 static const struct drm_audio_component_ops i915_audio_component_ops = {
 913         .owner          = THIS_MODULE,
 914         .get_power      = i915_audio_component_get_power,
 915         .put_power      = i915_audio_component_put_power,
 916         .codec_wake_override = i915_audio_component_codec_wake_override,
 917         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
 918         .sync_audio_rate = i915_audio_component_sync_audio_rate,
 919         .get_eld        = i915_audio_component_get_eld,
 920 };
 921
 922 static int i915_audio_component_bind(struct device *i915_kdev,
 923                                      struct device *hda_kdev, void *data)
 924 {
 925         struct i915_audio_component *acomp = data;
 926         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
 927         int i;
 928
 929         if (WARN_ON(acomp->base.ops || acomp->base.dev))
 930                 return -EEXIST;
 931
 932         drm_modeset_lock_all(&dev_priv->drm);
 933         acomp->base.ops = &i915_audio_component_ops;
 934         acomp->base.dev = i915_kdev;
 935         BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
 936         for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
 937                 acomp->aud_sample_rate[i] = 0;
 938         dev_priv->audio_component = acomp;
 939         drm_modeset_unlock_all(&dev_priv->drm);
 940
 941         return 0;
 942 }
 943
 944 static void i915_audio_component_unbind(struct device *i915_kdev,
 945                                         struct device *hda_kdev, void *data)
 946 {
 947         struct i915_audio_component *acomp = data;
 948         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
 949
 950         drm_modeset_lock_all(&dev_priv->drm);
 951         acomp->base.ops = NULL;
 952         acomp->base.dev = NULL;
 953         dev_priv->audio_component = NULL;
 954         drm_modeset_unlock_all(&dev_priv->drm);
 955 }
 956
 957 static const struct component_ops i915_audio_component_bind_ops = {
 958         .bind   = i915_audio_component_bind,
 959         .unbind = i915_audio_component_unbind,
 960 };
 961
 962 /**
 963  * i915_audio_component_init - initialize and register the audio component
 964  * @dev_priv: i915 device instance
 965  *
 966  * This will register with the component framework a child component which
 967  * will bind dynamically to the snd_hda_intel driver's corresponding master
 968  * component when the latter is registered. During binding the child
 969  * initializes an instance of struct i915_audio_component which it receives
 970  * from the master. The master can then start to use the interface defined by
 971  * this struct. Each side can break the binding at any point by deregistering
 972  * its own component after which each side's component unbind callback is
 973  * called.
 974  *
 975  * We ignore any error during registration and continue with reduced
 976  * functionality (i.e. without HDMI audio).
 977  */
 978 void i915_audio_component_init(struct drm_i915_private *dev_priv)
 979 {
 980         int ret;
 981
 982         ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
 983         if (ret < 0) {
 984                 DRM_ERROR("failed to add audio component (%d)\n", ret);
 985                 /* continue with reduced functionality */
 986                 return;
 987         }
 988
 989         dev_priv->audio_component_registered = true;
 990 }
 991
 992 /**
 993  * i915_audio_component_cleanup - deregister the audio component
 994  * @dev_priv: i915 device instance
 995  *
 996  * Deregisters the audio component, breaking any existing binding to the
 997  * corresponding snd_hda_intel driver's master component.
 998  */
 999 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1000 {
1001         if (!dev_priv->audio_component_registered)
1002                 return;
1003
1004         component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1005         dev_priv->audio_component_registered = false;
1006 }
1007
1008 /**
1009  * intel_audio_init() - Initialize the audio driver either using
1010  * component framework or using lpe audio bridge
1011  * @dev_priv: the i915 drm device private data
1012  *
1013  */
1014 void intel_audio_init(struct drm_i915_private *dev_priv)
1015 {
1016         if (intel_lpe_audio_init(dev_priv) < 0)
1017                 i915_audio_component_init(dev_priv);
1018 }
1019
1020 /**
1021  * intel_audio_deinit() - deinitialize the audio driver
1022  * @dev_priv: the i915 drm device private data
1023  *
1024  */
1025 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1026 {
1027         if ((dev_priv)->lpe_audio.platdev != NULL)
1028                 intel_lpe_audio_teardown(dev_priv);
1029         else
1030                 i915_audio_component_cleanup(dev_priv);
1031 }