drivers/gpu/drm/i915/intel_huc_fw.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2018 Intel Corporation
   5  */
   6
   7 #include "intel_huc_fw.h"
   8 #include "i915_drv.h"
   9
  10 /**
  11  * DOC: HuC Firmware
  12  *
  13  * Motivation:
  14  * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
  15  * Efficiency Video Coding) operations. Userspace can use the firmware
  16  * capabilities by adding HuC specific commands to batch buffers.
  17  *
  18  * Implementation:
  19  * The same firmware loader is used as the GuC. However, the actual
  20  * loading to HW is deferred until GEM initialization is done.
  21  *
  22  * Note that HuC firmware loading must be done before GuC loading.
  23  */
  24
  25 #define BXT_HUC_FW_MAJOR 01
  26 #define BXT_HUC_FW_MINOR 07
  27 #define BXT_BLD_NUM 1398
  28
  29 #define SKL_HUC_FW_MAJOR 01
  30 #define SKL_HUC_FW_MINOR 07
  31 #define SKL_BLD_NUM 1398
  32
  33 #define KBL_HUC_FW_MAJOR 02
  34 #define KBL_HUC_FW_MINOR 00
  35 #define KBL_BLD_NUM 1810
  36
  37 #define HUC_FW_PATH(platform, major, minor, bld_num) \
  38         "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
  39         __stringify(minor) "_" __stringify(bld_num) ".bin"
  40
  41 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
  42         SKL_HUC_FW_MINOR, SKL_BLD_NUM)
  43 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
  44
  45 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
  46         BXT_HUC_FW_MINOR, BXT_BLD_NUM)
  47 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
  48
  49 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
  50         KBL_HUC_FW_MINOR, KBL_BLD_NUM)
  51 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
  52
  53 static void huc_fw_select(struct intel_uc_fw *huc_fw)
  54 {
  55         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
  56         struct drm_i915_private *dev_priv = huc_to_i915(huc);
  57
  58         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
  59
  60         if (!HAS_HUC(dev_priv))
  61                 return;
  62
  63         if (i915_modparams.huc_firmware_path) {
  64                 huc_fw->path = i915_modparams.huc_firmware_path;
  65                 huc_fw->major_ver_wanted = 0;
  66                 huc_fw->minor_ver_wanted = 0;
  67         } else if (IS_SKYLAKE(dev_priv)) {
  68                 huc_fw->path = I915_SKL_HUC_UCODE;
  69                 huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
  70                 huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
  71         } else if (IS_BROXTON(dev_priv)) {
  72                 huc_fw->path = I915_BXT_HUC_UCODE;
  73                 huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
  74                 huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
  75         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
  76                 huc_fw->path = I915_KBL_HUC_UCODE;
  77                 huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
  78                 huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
  79         } else {
  80                 DRM_WARN("%s: No firmware known for this platform!\n",
  81                          intel_uc_fw_type_repr(huc_fw->type));
  82         }
  83 }
  84
  85 /**
  86  * intel_huc_fw_init_early() - initializes HuC firmware struct
  87  * @huc: intel_huc struct
  88  *
  89  * On platforms with HuC selects firmware for uploading
  90  */
  91 void intel_huc_fw_init_early(struct intel_huc *huc)
  92 {
  93         struct intel_uc_fw *huc_fw = &huc->fw;
  94
  95         intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC);
  96         huc_fw_select(huc_fw);
  97 }
  98
  99 /**
 100  * huc_fw_xfer() - DMA's the firmware
 101  * @huc_fw: the firmware descriptor
 102  * @vma: the firmware image (bound into the GGTT)
 103  *
 104  * Transfer the firmware image to RAM for execution by the microcontroller.
 105  *
 106  * Return: 0 on success, non-zero on failure
 107  */
 108 static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 109 {
 110         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
 111         struct drm_i915_private *dev_priv = huc_to_i915(huc);
 112         unsigned long offset = 0;
 113         u32 size;
 114         int ret;
 115
 116         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 117
 118         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 119
 120         /* Set the source address for the uCode */
 121         offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
 122                  huc_fw->header_offset;
 123         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 124         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 125
 126         /* Hardware doesn't look at destination address for HuC. Set it to 0,
 127          * but still program the correct address space.
 128          */
 129         I915_WRITE(DMA_ADDR_1_LOW, 0);
 130         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 131
 132         size = huc_fw->header_size + huc_fw->ucode_size;
 133         I915_WRITE(DMA_COPY_SIZE, size);
 134
 135         /* Start the DMA */
 136         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 137
 138         /* Wait for DMA to finish */
 139         ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
 140
 141         DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 142
 143         /* Disable the bits once DMA is over */
 144         I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
 145
 146         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 147
 148         return ret;
 149 }
 150
 151 /**
 152  * intel_huc_fw_upload() - load HuC uCode to device
 153  * @huc: intel_huc structure
 154  *
 155  * Called from intel_uc_init_hw() during driver load, resume from sleep and
 156  * after a GPU reset. Note that HuC must be loaded before GuC.
 157  *
 158  * The firmware image should have already been fetched into memory, so only
 159  * check that fetch succeeded, and then transfer the image to the h/w.
 160  *
 161  * Return:      non-zero code on error
 162  */
 163 int intel_huc_fw_upload(struct intel_huc *huc)
 164 {
 165         return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);
 166 }