drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47 };
  48
  49 struct intel_lvds_pps {
  50         /* 100us units */
  51         int t1_t2;
  52         int t3;
  53         int t4;
  54         int t5;
  55         int tx;
  56
  57         int divider;
  58
  59         int port;
  60         bool powerdown_on_reset;
  61 };
  62
  63 struct intel_lvds_encoder {
  64         struct intel_encoder base;
  65
  66         bool is_dual_link;
  67         i915_reg_t reg;
  68         u32 a3_power;
  69
  70         struct intel_lvds_pps init_pps;
  71         u32 init_lvds_val;
  72
  73         struct intel_lvds_connector *attached_connector;
  74 };
  75
  76 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  77 {
  78         return container_of(encoder, struct intel_lvds_encoder, base.base);
  79 }
  80
  81 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  82 {
  83         return container_of(connector, struct intel_lvds_connector, base.base);
  84 }
  85
  86 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
  87                              i915_reg_t lvds_reg, enum pipe *pipe)
  88 {
  89         u32 val;
  90
  91         val = I915_READ(lvds_reg);
  92
  93         /* asserts want to know the pipe even if the port is disabled */
  94         if (HAS_PCH_CPT(dev_priv))
  95                 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
  96         else
  97                 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
  98
  99         return val & LVDS_PORT_EN;
 100 }
 101
 102 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
 103                                     enum pipe *pipe)
 104 {
 105         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 106         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 107         bool ret;
 108
 109         if (!intel_display_power_get_if_enabled(dev_priv,
 110                                                 encoder->power_domain))
 111                 return false;
 112
 113         ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
 114
 115         intel_display_power_put(dev_priv, encoder->power_domain);
 116
 117         return ret;
 118 }
 119
 120 static void intel_lvds_get_config(struct intel_encoder *encoder,
 121                                   struct intel_crtc_state *pipe_config)
 122 {
 123         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 124         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 125         u32 tmp, flags = 0;
 126
 127         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 128
 129         tmp = I915_READ(lvds_encoder->reg);
 130         if (tmp & LVDS_HSYNC_POLARITY)
 131                 flags |= DRM_MODE_FLAG_NHSYNC;
 132         else
 133                 flags |= DRM_MODE_FLAG_PHSYNC;
 134         if (tmp & LVDS_VSYNC_POLARITY)
 135                 flags |= DRM_MODE_FLAG_NVSYNC;
 136         else
 137                 flags |= DRM_MODE_FLAG_PVSYNC;
 138
 139         pipe_config->base.adjusted_mode.flags |= flags;
 140
 141         if (INTEL_GEN(dev_priv) < 5)
 142                 pipe_config->gmch_pfit.lvds_border_bits =
 143                         tmp & LVDS_BORDER_ENABLE;
 144
 145         /* gen2/3 store dither state in pfit control, needs to match */
 146         if (INTEL_GEN(dev_priv) < 4) {
 147                 tmp = I915_READ(PFIT_CONTROL);
 148
 149                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 150         }
 151
 152         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 153 }
 154
 155 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 156                                         struct intel_lvds_pps *pps)
 157 {
 158         u32 val;
 159
 160         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 161
 162         val = I915_READ(PP_ON_DELAYS(0));
 163         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 164                     PANEL_PORT_SELECT_SHIFT;
 165         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 166                      PANEL_POWER_UP_DELAY_SHIFT;
 167         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 168                   PANEL_LIGHT_ON_DELAY_SHIFT;
 169
 170         val = I915_READ(PP_OFF_DELAYS(0));
 171         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 172                   PANEL_POWER_DOWN_DELAY_SHIFT;
 173         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 174                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 175
 176         val = I915_READ(PP_DIVISOR(0));
 177         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 178                        PP_REFERENCE_DIVIDER_SHIFT;
 179         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 180               PANEL_POWER_CYCLE_DELAY_SHIFT;
 181         /*
 182          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 183          * too short power-cycle delay due to the asynchronous programming of
 184          * the register.
 185          */
 186         if (val)
 187                 val--;
 188         /* Convert from 100ms to 100us units */
 189         pps->t4 = val * 1000;
 190
 191         if (INTEL_GEN(dev_priv) <= 4 &&
 192             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 193                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 194                               "setting defaults\n");
 195                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 196                 pps->t1_t2 = 40 * 10;
 197                 pps->t5 = 200 * 10;
 198                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 199                 pps->t3 = 35 * 10;
 200                 pps->tx = 200 * 10;
 201         }
 202
 203         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 204                          "divider %d port %d powerdown_on_reset %d\n",
 205                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 206                          pps->divider, pps->port, pps->powerdown_on_reset);
 207 }
 208
 209 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 210                                    struct intel_lvds_pps *pps)
 211 {
 212         u32 val;
 213
 214         val = I915_READ(PP_CONTROL(0));
 215         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 216         if (pps->powerdown_on_reset)
 217                 val |= PANEL_POWER_RESET;
 218         I915_WRITE(PP_CONTROL(0), val);
 219
 220         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 221                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 222                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 223         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 224                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 225
 226         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 227         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 228                PANEL_POWER_CYCLE_DELAY_SHIFT;
 229         I915_WRITE(PP_DIVISOR(0), val);
 230 }
 231
 232 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 233                                   const struct intel_crtc_state *pipe_config,
 234                                   const struct drm_connector_state *conn_state)
 235 {
 236         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 237         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 238         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 239         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 240         int pipe = crtc->pipe;
 241         u32 temp;
 242
 243         if (HAS_PCH_SPLIT(dev_priv)) {
 244                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 245                 assert_shared_dpll_disabled(dev_priv,
 246                                             pipe_config->shared_dpll);
 247         } else {
 248                 assert_pll_disabled(dev_priv, pipe);
 249         }
 250
 251         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 252
 253         temp = lvds_encoder->init_lvds_val;
 254         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 255
 256         if (HAS_PCH_CPT(dev_priv)) {
 257                 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 258                 temp |= LVDS_PIPE_SEL_CPT(pipe);
 259         } else {
 260                 temp &= ~LVDS_PIPE_SEL_MASK;
 261                 temp |= LVDS_PIPE_SEL(pipe);
 262         }
 263
 264         /* set the corresponsding LVDS_BORDER bit */
 265         temp &= ~LVDS_BORDER_ENABLE;
 266         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 267
 268         /*
 269          * Set the B0-B3 data pairs corresponding to whether we're going to
 270          * set the DPLLs for dual-channel mode or not.
 271          */
 272         if (lvds_encoder->is_dual_link)
 273                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 274         else
 275                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 276
 277         /*
 278          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 279          * appropriately here, but we need to look more thoroughly into how
 280          * panels behave in the two modes. For now, let's just maintain the
 281          * value we got from the BIOS.
 282          */
 283         temp &= ~LVDS_A3_POWER_MASK;
 284         temp |= lvds_encoder->a3_power;
 285
 286         /*
 287          * Set the dithering flag on LVDS as needed, note that there is no
 288          * special lvds dither control bit on pch-split platforms, dithering is
 289          * only controlled through the PIPECONF reg.
 290          */
 291         if (IS_GEN4(dev_priv)) {
 292                 /*
 293                  * Bspec wording suggests that LVDS port dithering only exists
 294                  * for 18bpp panels.
 295                  */
 296                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 297                         temp |= LVDS_ENABLE_DITHER;
 298                 else
 299                         temp &= ~LVDS_ENABLE_DITHER;
 300         }
 301         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 302         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 303                 temp |= LVDS_HSYNC_POLARITY;
 304         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 305                 temp |= LVDS_VSYNC_POLARITY;
 306
 307         I915_WRITE(lvds_encoder->reg, temp);
 308 }
 309
 310 /*
 311  * Sets the power state for the panel.
 312  */
 313 static void intel_enable_lvds(struct intel_encoder *encoder,
 314                               const struct intel_crtc_state *pipe_config,
 315                               const struct drm_connector_state *conn_state)
 316 {
 317         struct drm_device *dev = encoder->base.dev;
 318         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 319         struct drm_i915_private *dev_priv = to_i915(dev);
 320
 321         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 322
 323         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 324         POSTING_READ(lvds_encoder->reg);
 325
 326         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
 327                 DRM_ERROR("timed out waiting for panel to power on\n");
 328
 329         intel_panel_enable_backlight(pipe_config, conn_state);
 330 }
 331
 332 static void intel_disable_lvds(struct intel_encoder *encoder,
 333                                const struct intel_crtc_state *old_crtc_state,
 334                                const struct drm_connector_state *old_conn_state)
 335 {
 336         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 337         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 338
 339         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 340         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 341                 DRM_ERROR("timed out waiting for panel to power off\n");
 342
 343         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 344         POSTING_READ(lvds_encoder->reg);
 345 }
 346
 347 static void gmch_disable_lvds(struct intel_encoder *encoder,
 348                               const struct intel_crtc_state *old_crtc_state,
 349                               const struct drm_connector_state *old_conn_state)
 350
 351 {
 352         intel_panel_disable_backlight(old_conn_state);
 353
 354         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 355 }
 356
 357 static void pch_disable_lvds(struct intel_encoder *encoder,
 358                              const struct intel_crtc_state *old_crtc_state,
 359                              const struct drm_connector_state *old_conn_state)
 360 {
 361         intel_panel_disable_backlight(old_conn_state);
 362 }
 363
 364 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 365                                   const struct intel_crtc_state *old_crtc_state,
 366                                   const struct drm_connector_state *old_conn_state)
 367 {
 368         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 369 }
 370
 371 static enum drm_mode_status
 372 intel_lvds_mode_valid(struct drm_connector *connector,
 373                       struct drm_display_mode *mode)
 374 {
 375         struct intel_connector *intel_connector = to_intel_connector(connector);
 376         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 377         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 378
 379         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 380                 return MODE_NO_DBLESCAN;
 381         if (mode->hdisplay > fixed_mode->hdisplay)
 382                 return MODE_PANEL;
 383         if (mode->vdisplay > fixed_mode->vdisplay)
 384                 return MODE_PANEL;
 385         if (fixed_mode->clock > max_pixclk)
 386                 return MODE_CLOCK_HIGH;
 387
 388         return MODE_OK;
 389 }
 390
 391 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 392                                       struct intel_crtc_state *pipe_config,
 393                                       struct drm_connector_state *conn_state)
 394 {
 395         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 396         struct intel_lvds_encoder *lvds_encoder =
 397                 to_lvds_encoder(&intel_encoder->base);
 398         struct intel_connector *intel_connector =
 399                 &lvds_encoder->attached_connector->base;
 400         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 401         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 402         unsigned int lvds_bpp;
 403
 404         /* Should never happen!! */
 405         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 406                 DRM_ERROR("Can't support LVDS on pipe A\n");
 407                 return false;
 408         }
 409
 410         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 411                 lvds_bpp = 8*3;
 412         else
 413                 lvds_bpp = 6*3;
 414
 415         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 416                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 417                               pipe_config->pipe_bpp, lvds_bpp);
 418                 pipe_config->pipe_bpp = lvds_bpp;
 419         }
 420
 421         /*
 422          * We have timings from the BIOS for the panel, put them in
 423          * to the adjusted mode.  The CRTC will be set up for this mode,
 424          * with the panel scaling set up to source from the H/VDisplay
 425          * of the original mode.
 426          */
 427         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 428                                adjusted_mode);
 429
 430         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 431                 return false;
 432
 433         if (HAS_PCH_SPLIT(dev_priv)) {
 434                 pipe_config->has_pch_encoder = true;
 435
 436                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 437                                         conn_state->scaling_mode);
 438         } else {
 439                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 440                                          conn_state->scaling_mode);
 441
 442         }
 443
 444         /*
 445          * XXX: It would be nice to support lower refresh rates on the
 446          * panels to reduce power consumption, and perhaps match the
 447          * user's requested refresh rate.
 448          */
 449
 450         return true;
 451 }
 452
 453 static enum drm_connector_status
 454 intel_lvds_detect(struct drm_connector *connector, bool force)
 455 {
 456         return connector_status_connected;
 457 }
 458
 459 /*
 460  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 461  */
 462 static int intel_lvds_get_modes(struct drm_connector *connector)
 463 {
 464         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 465         struct drm_device *dev = connector->dev;
 466         struct drm_display_mode *mode;
 467
 468         /* use cached edid if we have one */
 469         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 470                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 471
 472         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 473         if (mode == NULL)
 474                 return 0;
 475
 476         drm_mode_probed_add(connector, mode);
 477         return 1;
 478 }
 479
 480 /**
 481  * intel_lvds_destroy - unregister and free LVDS structures
 482  * @connector: connector to free
 483  *
 484  * Unregister the DDC bus for this connector then free the driver private
 485  * structure.
 486  */
 487 static void intel_lvds_destroy(struct drm_connector *connector)
 488 {
 489         struct intel_lvds_connector *lvds_connector =
 490                 to_lvds_connector(connector);
 491
 492         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 493                 kfree(lvds_connector->base.edid);
 494
 495         intel_panel_fini(&lvds_connector->base.panel);
 496
 497         drm_connector_cleanup(connector);
 498         kfree(connector);
 499 }
 500
 501 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 502         .get_modes = intel_lvds_get_modes,
 503         .mode_valid = intel_lvds_mode_valid,
 504         .atomic_check = intel_digital_connector_atomic_check,
 505 };
 506
 507 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 508         .detect = intel_lvds_detect,
 509         .fill_modes = drm_helper_probe_single_connector_modes,
 510         .atomic_get_property = intel_digital_connector_atomic_get_property,
 511         .atomic_set_property = intel_digital_connector_atomic_set_property,
 512         .late_register = intel_connector_register,
 513         .early_unregister = intel_connector_unregister,
 514         .destroy = intel_lvds_destroy,
 515         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 516         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 517 };
 518
 519 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 520         .destroy = intel_encoder_destroy,
 521 };
 522
 523 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 524 {
 525         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 526         return 1;
 527 }
 528
 529 /* These systems claim to have LVDS, but really don't */
 530 static const struct dmi_system_id intel_no_lvds[] = {
 531         {
 532                 .callback = intel_no_lvds_dmi_callback,
 533                 .ident = "Apple Mac Mini (Core series)",
 534                 .matches = {
 535                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 536                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 537                 },
 538         },
 539         {
 540                 .callback = intel_no_lvds_dmi_callback,
 541                 .ident = "Apple Mac Mini (Core 2 series)",
 542                 .matches = {
 543                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 544                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 545                 },
 546         },
 547         {
 548                 .callback = intel_no_lvds_dmi_callback,
 549                 .ident = "MSI IM-945GSE-A",
 550                 .matches = {
 551                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 552                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 553                 },
 554         },
 555         {
 556                 .callback = intel_no_lvds_dmi_callback,
 557                 .ident = "Dell Studio Hybrid",
 558                 .matches = {
 559                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 560                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 561                 },
 562         },
 563         {
 564                 .callback = intel_no_lvds_dmi_callback,
 565                 .ident = "Dell OptiPlex FX170",
 566                 .matches = {
 567                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 568                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 569                 },
 570         },
 571         {
 572                 .callback = intel_no_lvds_dmi_callback,
 573                 .ident = "AOpen Mini PC",
 574                 .matches = {
 575                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 576                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 577                 },
 578         },
 579         {
 580                 .callback = intel_no_lvds_dmi_callback,
 581                 .ident = "AOpen Mini PC MP915",
 582                 .matches = {
 583                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 584                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 585                 },
 586         },
 587         {
 588                 .callback = intel_no_lvds_dmi_callback,
 589                 .ident = "AOpen i915GMm-HFS",
 590                 .matches = {
 591                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 592                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 593                 },
 594         },
 595         {
 596                 .callback = intel_no_lvds_dmi_callback,
 597                 .ident = "AOpen i45GMx-I",
 598                 .matches = {
 599                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 600                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 601                 },
 602         },
 603         {
 604                 .callback = intel_no_lvds_dmi_callback,
 605                 .ident = "Aopen i945GTt-VFA",
 606                 .matches = {
 607                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 608                 },
 609         },
 610         {
 611                 .callback = intel_no_lvds_dmi_callback,
 612                 .ident = "Clientron U800",
 613                 .matches = {
 614                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 615                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 616                 },
 617         },
 618         {
 619                 .callback = intel_no_lvds_dmi_callback,
 620                 .ident = "Clientron E830",
 621                 .matches = {
 622                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 623                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 624                 },
 625         },
 626         {
 627                 .callback = intel_no_lvds_dmi_callback,
 628                 .ident = "Asus EeeBox PC EB1007",
 629                 .matches = {
 630                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 631                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 632                 },
 633         },
 634         {
 635                 .callback = intel_no_lvds_dmi_callback,
 636                 .ident = "Asus AT5NM10T-I",
 637                 .matches = {
 638                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 639                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 640                 },
 641         },
 642         {
 643                 .callback = intel_no_lvds_dmi_callback,
 644                 .ident = "Hewlett-Packard HP t5740",
 645                 .matches = {
 646                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 647                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 648                 },
 649         },
 650         {
 651                 .callback = intel_no_lvds_dmi_callback,
 652                 .ident = "Hewlett-Packard t5745",
 653                 .matches = {
 654                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 655                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 656                 },
 657         },
 658         {
 659                 .callback = intel_no_lvds_dmi_callback,
 660                 .ident = "Hewlett-Packard st5747",
 661                 .matches = {
 662                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 663                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 664                 },
 665         },
 666         {
 667                 .callback = intel_no_lvds_dmi_callback,
 668                 .ident = "MSI Wind Box DC500",
 669                 .matches = {
 670                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 671                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 672                 },
 673         },
 674         {
 675                 .callback = intel_no_lvds_dmi_callback,
 676                 .ident = "Gigabyte GA-D525TUD",
 677                 .matches = {
 678                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 679                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 680                 },
 681         },
 682         {
 683                 .callback = intel_no_lvds_dmi_callback,
 684                 .ident = "Supermicro X7SPA-H",
 685                 .matches = {
 686                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 687                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 688                 },
 689         },
 690         {
 691                 .callback = intel_no_lvds_dmi_callback,
 692                 .ident = "Fujitsu Esprimo Q900",
 693                 .matches = {
 694                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 695                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 696                 },
 697         },
 698         {
 699                 .callback = intel_no_lvds_dmi_callback,
 700                 .ident = "Intel D410PT",
 701                 .matches = {
 702                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 703                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 704                 },
 705         },
 706         {
 707                 .callback = intel_no_lvds_dmi_callback,
 708                 .ident = "Intel D425KT",
 709                 .matches = {
 710                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 711                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 712                 },
 713         },
 714         {
 715                 .callback = intel_no_lvds_dmi_callback,
 716                 .ident = "Intel D510MO",
 717                 .matches = {
 718                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 719                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 720                 },
 721         },
 722         {
 723                 .callback = intel_no_lvds_dmi_callback,
 724                 .ident = "Intel D525MW",
 725                 .matches = {
 726                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 727                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 728                 },
 729         },
 730         {
 731                 .callback = intel_no_lvds_dmi_callback,
 732                 .ident = "Radiant P845",
 733                 .matches = {
 734                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 735                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 736                 },
 737         },
 738
 739         { }     /* terminating entry */
 740 };
 741
 742 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 743 {
 744         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 745         return 1;
 746 }
 747
 748 static const struct dmi_system_id intel_dual_link_lvds[] = {
 749         {
 750                 .callback = intel_dual_link_lvds_callback,
 751                 .ident = "Apple MacBook Pro 15\" (2010)",
 752                 .matches = {
 753                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 754                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 755                 },
 756         },
 757         {
 758                 .callback = intel_dual_link_lvds_callback,
 759                 .ident = "Apple MacBook Pro 15\" (2011)",
 760                 .matches = {
 761                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 762                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 763                 },
 764         },
 765         {
 766                 .callback = intel_dual_link_lvds_callback,
 767                 .ident = "Apple MacBook Pro 15\" (2012)",
 768                 .matches = {
 769                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 770                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 771                 },
 772         },
 773         { }     /* terminating entry */
 774 };
 775
 776 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 777 {
 778         struct intel_encoder *intel_encoder;
 779
 780         for_each_intel_encoder(dev, intel_encoder)
 781                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 782                         return intel_encoder;
 783
 784         return NULL;
 785 }
 786
 787 bool intel_is_dual_link_lvds(struct drm_device *dev)
 788 {
 789         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 790
 791         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 792 }
 793
 794 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 795 {
 796         struct drm_device *dev = lvds_encoder->base.base.dev;
 797         unsigned int val;
 798         struct drm_i915_private *dev_priv = to_i915(dev);
 799
 800         /* use the module option value if specified */
 801         if (i915_modparams.lvds_channel_mode > 0)
 802                 return i915_modparams.lvds_channel_mode == 2;
 803
 804         /* single channel LVDS is limited to 112 MHz */
 805         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 806             > 112999)
 807                 return true;
 808
 809         if (dmi_check_system(intel_dual_link_lvds))
 810                 return true;
 811
 812         /*
 813          * BIOS should set the proper LVDS register value at boot, but
 814          * in reality, it doesn't set the value when the lid is closed;
 815          * we need to check "the value to be set" in VBT when LVDS
 816          * register is uninitialized.
 817          */
 818         val = I915_READ(lvds_encoder->reg);
 819         if (HAS_PCH_CPT(dev_priv))
 820                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 821         else
 822                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 823         if (val == 0)
 824                 val = dev_priv->vbt.bios_lvds_val;
 825
 826         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 827 }
 828
 829 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 830 {
 831         /*
 832          * With the introduction of the PCH we gained a dedicated
 833          * LVDS presence pin, use it.
 834          */
 835         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 836                 return true;
 837
 838         /*
 839          * Otherwise LVDS was only attached to mobile products,
 840          * except for the inglorious 830gm
 841          */
 842         if (INTEL_GEN(dev_priv) <= 4 &&
 843             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 844                 return true;
 845
 846         return false;
 847 }
 848
 849 /**
 850  * intel_lvds_init - setup LVDS connectors on this device
 851  * @dev_priv: i915 device
 852  *
 853  * Create the connector, register the LVDS DDC bus, and try to figure out what
 854  * modes we can display on the LVDS panel (if present).
 855  */
 856 void intel_lvds_init(struct drm_i915_private *dev_priv)
 857 {
 858         struct drm_device *dev = &dev_priv->drm;
 859         struct intel_lvds_encoder *lvds_encoder;
 860         struct intel_encoder *intel_encoder;
 861         struct intel_lvds_connector *lvds_connector;
 862         struct intel_connector *intel_connector;
 863         struct drm_connector *connector;
 864         struct drm_encoder *encoder;
 865         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 866         struct drm_display_mode *fixed_mode = NULL;
 867         struct drm_display_mode *downclock_mode = NULL;
 868         struct edid *edid;
 869         i915_reg_t lvds_reg;
 870         u32 lvds;
 871         u8 pin;
 872         u32 allowed_scalers;
 873
 874         if (!intel_lvds_supported(dev_priv))
 875                 return;
 876
 877         /* Skip init on machines we know falsely report LVDS */
 878         if (dmi_check_system(intel_no_lvds)) {
 879                 WARN(!dev_priv->vbt.int_lvds_support,
 880                      "Useless DMI match. Internal LVDS support disabled by VBT\n");
 881                 return;
 882         }
 883
 884         if (!dev_priv->vbt.int_lvds_support) {
 885                 DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n");
 886                 return;
 887         }
 888
 889         if (HAS_PCH_SPLIT(dev_priv))
 890                 lvds_reg = PCH_LVDS;
 891         else
 892                 lvds_reg = LVDS;
 893
 894         lvds = I915_READ(lvds_reg);
 895
 896         if (HAS_PCH_SPLIT(dev_priv)) {
 897                 if ((lvds & LVDS_DETECTED) == 0)
 898                         return;
 899         }
 900
 901         pin = GMBUS_PIN_PANEL;
 902         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 903                 if ((lvds & LVDS_PORT_EN) == 0) {
 904                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 905                         return;
 906                 }
 907                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 908         }
 909
 910         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 911         if (!lvds_encoder)
 912                 return;
 913
 914         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
 915         if (!lvds_connector) {
 916                 kfree(lvds_encoder);
 917                 return;
 918         }
 919
 920         if (intel_connector_init(&lvds_connector->base) < 0) {
 921                 kfree(lvds_connector);
 922                 kfree(lvds_encoder);
 923                 return;
 924         }
 925
 926         lvds_encoder->attached_connector = lvds_connector;
 927
 928         intel_encoder = &lvds_encoder->base;
 929         encoder = &intel_encoder->base;
 930         intel_connector = &lvds_connector->base;
 931         connector = &intel_connector->base;
 932         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
 933                            DRM_MODE_CONNECTOR_LVDS);
 934
 935         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
 936                          DRM_MODE_ENCODER_LVDS, "LVDS");
 937
 938         intel_encoder->enable = intel_enable_lvds;
 939         intel_encoder->pre_enable = intel_pre_enable_lvds;
 940         intel_encoder->compute_config = intel_lvds_compute_config;
 941         if (HAS_PCH_SPLIT(dev_priv)) {
 942                 intel_encoder->disable = pch_disable_lvds;
 943                 intel_encoder->post_disable = pch_post_disable_lvds;
 944         } else {
 945                 intel_encoder->disable = gmch_disable_lvds;
 946         }
 947         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 948         intel_encoder->get_config = intel_lvds_get_config;
 949         intel_connector->get_hw_state = intel_connector_get_hw_state;
 950
 951         intel_connector_attach_encoder(intel_connector, intel_encoder);
 952
 953         intel_encoder->type = INTEL_OUTPUT_LVDS;
 954         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 955         intel_encoder->port = PORT_NONE;
 956         intel_encoder->cloneable = 0;
 957         if (HAS_PCH_SPLIT(dev_priv))
 958                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 959         else if (IS_GEN4(dev_priv))
 960                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
 961         else
 962                 intel_encoder->crtc_mask = (1 << 1);
 963
 964         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
 965         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 966         connector->interlace_allowed = false;
 967         connector->doublescan_allowed = false;
 968
 969         lvds_encoder->reg = lvds_reg;
 970
 971         /* create the scaling mode property */
 972         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
 973         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
 974         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
 975         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
 976         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 977
 978         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
 979         lvds_encoder->init_lvds_val = lvds;
 980
 981         /*
 982          * LVDS discovery:
 983          * 1) check for EDID on DDC
 984          * 2) check for VBT data
 985          * 3) check to see if LVDS is already on
 986          *    if none of the above, no panel
 987          */
 988
 989         /*
 990          * Attempt to get the fixed panel mode from DDC.  Assume that the
 991          * preferred mode is the right one.
 992          */
 993         mutex_lock(&dev->mode_config.mutex);
 994         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 995                 edid = drm_get_edid_switcheroo(connector,
 996                                     intel_gmbus_get_adapter(dev_priv, pin));
 997         else
 998                 edid = drm_get_edid(connector,
 999                                     intel_gmbus_get_adapter(dev_priv, pin));
1000         if (edid) {
1001                 if (drm_add_edid_modes(connector, edid)) {
1002                         drm_connector_update_edid_property(connector,
1003                                                                 edid);
1004                 } else {
1005                         kfree(edid);
1006                         edid = ERR_PTR(-EINVAL);
1007                 }
1008         } else {
1009                 edid = ERR_PTR(-ENOENT);
1010         }
1011         lvds_connector->base.edid = edid;
1012
1013         list_for_each_entry(scan, &connector->probed_modes, head) {
1014                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1015                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1016                         drm_mode_debug_printmodeline(scan);
1017
1018                         fixed_mode = drm_mode_duplicate(dev, scan);
1019                         if (fixed_mode)
1020                                 goto out;
1021                 }
1022         }
1023
1024         /* Failed to get EDID, what about VBT? */
1025         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1026                 DRM_DEBUG_KMS("using mode from VBT: ");
1027                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1028
1029                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1030                 if (fixed_mode) {
1031                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1032                         connector->display_info.width_mm = fixed_mode->width_mm;
1033                         connector->display_info.height_mm = fixed_mode->height_mm;
1034                         goto out;
1035                 }
1036         }
1037
1038         /*
1039          * If we didn't get EDID, try checking if the panel is already turned
1040          * on.  If so, assume that whatever is currently programmed is the
1041          * correct mode.
1042          */
1043         fixed_mode = intel_encoder_current_mode(intel_encoder);
1044         if (fixed_mode) {
1045                 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1046                 drm_mode_debug_printmodeline(fixed_mode);
1047                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1048         }
1049
1050         /* If we still don't have a mode after all that, give up. */
1051         if (!fixed_mode)
1052                 goto failed;
1053
1054 out:
1055         mutex_unlock(&dev->mode_config.mutex);
1056
1057         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1058         intel_panel_setup_backlight(connector, INVALID_PIPE);
1059
1060         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1061         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1062                       lvds_encoder->is_dual_link ? "dual" : "single");
1063
1064         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1065
1066         return;
1067
1068 failed:
1069         mutex_unlock(&dev->mode_config.mutex);
1070
1071         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1072         drm_connector_cleanup(connector);
1073         drm_encoder_cleanup(encoder);
1074         kfree(lvds_encoder);
1075         kfree(lvds_connector);
1076         return;
1077 }