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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_sdvo.c
blob1817a5c0c80fd13e28466d8b949410d8402aa2f4
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_sdvo_regs.h"
40
41 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
45
46 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
47 SDVO_TV_MASK)
48
49 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
50 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
51 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
52 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
53 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
54
55
56 static const char * const tv_format_names[] = {
57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64 };
65
66 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
67
68 struct intel_sdvo {
69 struct intel_encoder base;
70
71 struct i2c_adapter *i2c;
72 u8 slave_addr;
73
74 struct i2c_adapter ddc;
75
76 /* Register for the SDVO device: SDVOB or SDVOC */
77 i915_reg_t sdvo_reg;
78
79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
81
82 /*
83 * Capabilities of the SDVO device returned by
84 * intel_sdvo_get_capabilities()
85 */
86 struct intel_sdvo_caps caps;
87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
89 int pixel_clock_min, pixel_clock_max;
90
91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
97 /*
98 * Hotplug activation bits for this device
99 */
100 uint16_t hotplug_active;
101
102 /**
103 * This is set if we're going to treat the device as TV-out.
104 *
105 * While we have these nice friendly flags for output types that ought
106 * to decide this for us, the S-Video output on our HDMI+S-Video card
107 * shows up as RGB1 (VGA).
108 */
109 bool is_tv;
110
111 enum port port;
112
113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
119 bool rgb_quant_range_selectable;
120
121 /**
122 * This is set if we detect output of sdvo device as LVDS and
123 * have a valid fixed mode to use with the panel.
124 */
125 bool is_lvds;
126
127 /**
128 * This is sdvo fixed pannel mode pointer
129 */
130 struct drm_display_mode *sdvo_lvds_fixed_mode;
131
132 /* DDC bus used by this SDVO encoder */
133 uint8_t ddc_bus;
134
135 /*
136 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
137 */
138 uint8_t dtd_sdvo_flags;
139 };
140
141 struct intel_sdvo_connector {
142 struct intel_connector base;
143
144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 /* This contains all current supported TV format */
148 u8 tv_format_supported[TV_FORMAT_NUM];
149 int format_supported_num;
150 struct drm_property *tv_format;
151
152 /* add the property for the SDVO-TV */
153 struct drm_property *left;
154 struct drm_property *right;
155 struct drm_property *top;
156 struct drm_property *bottom;
157 struct drm_property *hpos;
158 struct drm_property *vpos;
159 struct drm_property *contrast;
160 struct drm_property *saturation;
161 struct drm_property *hue;
162 struct drm_property *sharpness;
163 struct drm_property *flicker_filter;
164 struct drm_property *flicker_filter_adaptive;
165 struct drm_property *flicker_filter_2d;
166 struct drm_property *tv_chroma_filter;
167 struct drm_property *tv_luma_filter;
168 struct drm_property *dot_crawl;
169
170 /* add the property for the SDVO-TV/LVDS */
171 struct drm_property *brightness;
172
173 /* this is to get the range of margin.*/
174 u32 max_hscan, max_vscan;
175 };
176
177 struct intel_sdvo_connector_state {
178 /* base.base: tv.saturation/contrast/hue/brightness */
179 struct intel_digital_connector_state base;
180
181 struct {
182 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
183 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
184 unsigned chroma_filter, luma_filter, dot_crawl;
185 } tv;
186 };
187
188 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
189 {
190 return container_of(encoder, struct intel_sdvo, base);
191 }
192
193 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
194 {
195 return to_sdvo(intel_attached_encoder(connector));
196 }
197
198 static struct intel_sdvo_connector *
199 to_intel_sdvo_connector(struct drm_connector *connector)
200 {
201 return container_of(connector, struct intel_sdvo_connector, base.base);
202 }
203
204 #define to_intel_sdvo_connector_state(conn_state) \
205 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
206
207 static bool
208 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
209 static bool
210 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector,
212 int type);
213 static bool
214 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
215 struct intel_sdvo_connector *intel_sdvo_connector);
216
217 /*
218 * Writes the SDVOB or SDVOC with the given value, but always writes both
219 * SDVOB and SDVOC to work around apparent hardware issues (according to
220 * comments in the BIOS).
221 */
222 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
223 {
224 struct drm_device *dev = intel_sdvo->base.base.dev;
225 struct drm_i915_private *dev_priv = to_i915(dev);
226 u32 bval = val, cval = val;
227 int i;
228
229 if (HAS_PCH_SPLIT(dev_priv)) {
230 I915_WRITE(intel_sdvo->sdvo_reg, val);
231 POSTING_READ(intel_sdvo->sdvo_reg);
232 /*
233 * HW workaround, need to write this twice for issue
234 * that may result in first write getting masked.
235 */
236 if (HAS_PCH_IBX(dev_priv)) {
237 I915_WRITE(intel_sdvo->sdvo_reg, val);
238 POSTING_READ(intel_sdvo->sdvo_reg);
239 }
240 return;
241 }
242
243 if (intel_sdvo->port == PORT_B)
244 cval = I915_READ(GEN3_SDVOC);
245 else
246 bval = I915_READ(GEN3_SDVOB);
247
248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++) {
254 I915_WRITE(GEN3_SDVOB, bval);
255 POSTING_READ(GEN3_SDVOB);
256
257 I915_WRITE(GEN3_SDVOC, cval);
258 POSTING_READ(GEN3_SDVOC);
259 }
260 }
261
262 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
263 {
264 struct i2c_msg msgs[] = {
265 {
266 .addr = intel_sdvo->slave_addr,
267 .flags = 0,
268 .len = 1,
269 .buf = &addr,
270 },
271 {
272 .addr = intel_sdvo->slave_addr,
273 .flags = I2C_M_RD,
274 .len = 1,
275 .buf = ch,
276 }
277 };
278 int ret;
279
280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
281 return true;
282
283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
284 return false;
285 }
286
287 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288 /** Mapping of command numbers to names, for debug output */
289 static const struct _sdvo_cmd_name {
290 u8 cmd;
291 const char *name;
292 } __attribute__ ((packed)) sdvo_cmd_names[] = {
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
404 };
405
406 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
407
408 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
409 const void *args, int args_len)
410 {
411 int i, pos = 0;
412 #define BUF_LEN 256
413 char buffer[BUF_LEN];
414
415 #define BUF_PRINT(args...) \
416 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
417
418
419 for (i = 0; i < args_len; i++) {
420 BUF_PRINT("%02X ", ((u8 *)args)[i]);
421 }
422 for (; i < 8; i++) {
423 BUF_PRINT(" ");
424 }
425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
426 if (cmd == sdvo_cmd_names[i].cmd) {
427 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
428 break;
429 }
430 }
431 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
432 BUF_PRINT("(%02X)", cmd);
433 }
434 BUG_ON(pos >= BUF_LEN - 1);
435 #undef BUF_PRINT
436 #undef BUF_LEN
437
438 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
439 }
440
441 static const char * const cmd_status_names[] = {
442 "Power on",
443 "Success",
444 "Not supported",
445 "Invalid arg",
446 "Pending",
447 "Target not specified",
448 "Scaling not supported"
449 };
450
451 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
452 const void *args, int args_len,
453 bool unlocked)
454 {
455 u8 *buf, status;
456 struct i2c_msg *msgs;
457 int i, ret = true;
458
459 /* Would be simpler to allocate both in one go ? */
460 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
461 if (!buf)
462 return false;
463
464 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
465 if (!msgs) {
466 kfree(buf);
467 return false;
468 }
469
470 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
471
472 for (i = 0; i < args_len; i++) {
473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2 *i;
477 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
478 buf[2*i + 1] = ((u8*)args)[i];
479 }
480 msgs[i].addr = intel_sdvo->slave_addr;
481 msgs[i].flags = 0;
482 msgs[i].len = 2;
483 msgs[i].buf = buf + 2*i;
484 buf[2*i + 0] = SDVO_I2C_OPCODE;
485 buf[2*i + 1] = cmd;
486
487 /* the following two are to read the response */
488 status = SDVO_I2C_CMD_STATUS;
489 msgs[i+1].addr = intel_sdvo->slave_addr;
490 msgs[i+1].flags = 0;
491 msgs[i+1].len = 1;
492 msgs[i+1].buf = &status;
493
494 msgs[i+2].addr = intel_sdvo->slave_addr;
495 msgs[i+2].flags = I2C_M_RD;
496 msgs[i+2].len = 1;
497 msgs[i+2].buf = &status;
498
499 if (unlocked)
500 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
501 else
502 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
503 if (ret < 0) {
504 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
505 ret = false;
506 goto out;
507 }
508 if (ret != i+3) {
509 /* failure in I2C transfer */
510 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
511 ret = false;
512 }
513
514 out:
515 kfree(msgs);
516 kfree(buf);
517 return ret;
518 }
519
520 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
521 const void *args, int args_len)
522 {
523 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
524 }
525
526 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
527 void *response, int response_len)
528 {
529 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
530 u8 status;
531 int i, pos = 0;
532 #define BUF_LEN 256
533 char buffer[BUF_LEN];
534
535
536 /*
537 * The documentation states that all commands will be
538 * processed within 15µs, and that we need only poll
539 * the status byte a maximum of 3 times in order for the
540 * command to be complete.
541 *
542 * Check 5 times in case the hardware failed to read the docs.
543 *
544 * Also beware that the first response by many devices is to
545 * reply PENDING and stall for time. TVs are notorious for
546 * requiring longer than specified to complete their replies.
547 * Originally (in the DDX long ago), the delay was only ever 15ms
548 * with an additional delay of 30ms applied for TVs added later after
549 * many experiments. To accommodate both sets of delays, we do a
550 * sequence of slow checks if the device is falling behind and fails
551 * to reply within 5*15µs.
552 */
553 if (!intel_sdvo_read_byte(intel_sdvo,
554 SDVO_I2C_CMD_STATUS,
555 &status))
556 goto log_fail;
557
558 while ((status == SDVO_CMD_STATUS_PENDING ||
559 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
560 if (retry < 10)
561 msleep(15);
562 else
563 udelay(15);
564
565 if (!intel_sdvo_read_byte(intel_sdvo,
566 SDVO_I2C_CMD_STATUS,
567 &status))
568 goto log_fail;
569 }
570
571 #define BUF_PRINT(args...) \
572 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
573
574 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
575 BUF_PRINT("(%s)", cmd_status_names[status]);
576 else
577 BUF_PRINT("(??? %d)", status);
578
579 if (status != SDVO_CMD_STATUS_SUCCESS)
580 goto log_fail;
581
582 /* Read the command response */
583 for (i = 0; i < response_len; i++) {
584 if (!intel_sdvo_read_byte(intel_sdvo,
585 SDVO_I2C_RETURN_0 + i,
586 &((u8 *)response)[i]))
587 goto log_fail;
588 BUF_PRINT(" %02X", ((u8 *)response)[i]);
589 }
590 BUG_ON(pos >= BUF_LEN - 1);
591 #undef BUF_PRINT
592 #undef BUF_LEN
593
594 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
595 return true;
596
597 log_fail:
598 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
599 return false;
600 }
601
602 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
603 {
604 if (adjusted_mode->crtc_clock >= 100000)
605 return 1;
606 else if (adjusted_mode->crtc_clock >= 50000)
607 return 2;
608 else
609 return 4;
610 }
611
612 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
613 u8 ddc_bus)
614 {
615 /* This must be the immediately preceding write before the i2c xfer */
616 return __intel_sdvo_write_cmd(intel_sdvo,
617 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
618 &ddc_bus, 1, false);
619 }
620
621 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
622 {
623 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
624 return false;
625
626 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
627 }
628
629 static bool
630 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
631 {
632 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
633 return false;
634
635 return intel_sdvo_read_response(intel_sdvo, value, len);
636 }
637
638 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
639 {
640 struct intel_sdvo_set_target_input_args targets = {0};
641 return intel_sdvo_set_value(intel_sdvo,
642 SDVO_CMD_SET_TARGET_INPUT,
643 &targets, sizeof(targets));
644 }
645
646 /*
647 * Return whether each input is trained.
648 *
649 * This function is making an assumption about the layout of the response,
650 * which should be checked against the docs.
651 */
652 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
653 {
654 struct intel_sdvo_get_trained_inputs_response response;
655
656 BUILD_BUG_ON(sizeof(response) != 1);
657 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
658 &response, sizeof(response)))
659 return false;
660
661 *input_1 = response.input0_trained;
662 *input_2 = response.input1_trained;
663 return true;
664 }
665
666 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
667 u16 outputs)
668 {
669 return intel_sdvo_set_value(intel_sdvo,
670 SDVO_CMD_SET_ACTIVE_OUTPUTS,
671 &outputs, sizeof(outputs));
672 }
673
674 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
675 u16 *outputs)
676 {
677 return intel_sdvo_get_value(intel_sdvo,
678 SDVO_CMD_GET_ACTIVE_OUTPUTS,
679 outputs, sizeof(*outputs));
680 }
681
682 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
683 int mode)
684 {
685 u8 state = SDVO_ENCODER_STATE_ON;
686
687 switch (mode) {
688 case DRM_MODE_DPMS_ON:
689 state = SDVO_ENCODER_STATE_ON;
690 break;
691 case DRM_MODE_DPMS_STANDBY:
692 state = SDVO_ENCODER_STATE_STANDBY;
693 break;
694 case DRM_MODE_DPMS_SUSPEND:
695 state = SDVO_ENCODER_STATE_SUSPEND;
696 break;
697 case DRM_MODE_DPMS_OFF:
698 state = SDVO_ENCODER_STATE_OFF;
699 break;
700 }
701
702 return intel_sdvo_set_value(intel_sdvo,
703 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
704 }
705
706 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
707 int *clock_min,
708 int *clock_max)
709 {
710 struct intel_sdvo_pixel_clock_range clocks;
711
712 BUILD_BUG_ON(sizeof(clocks) != 4);
713 if (!intel_sdvo_get_value(intel_sdvo,
714 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
715 &clocks, sizeof(clocks)))
716 return false;
717
718 /* Convert the values from units of 10 kHz to kHz. */
719 *clock_min = clocks.min * 10;
720 *clock_max = clocks.max * 10;
721 return true;
722 }
723
724 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
725 u16 outputs)
726 {
727 return intel_sdvo_set_value(intel_sdvo,
728 SDVO_CMD_SET_TARGET_OUTPUT,
729 &outputs, sizeof(outputs));
730 }
731
732 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
733 struct intel_sdvo_dtd *dtd)
734 {
735 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
736 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
737 }
738
739 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
740 struct intel_sdvo_dtd *dtd)
741 {
742 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
743 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
744 }
745
746 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
747 struct intel_sdvo_dtd *dtd)
748 {
749 return intel_sdvo_set_timing(intel_sdvo,
750 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
751 }
752
753 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
754 struct intel_sdvo_dtd *dtd)
755 {
756 return intel_sdvo_set_timing(intel_sdvo,
757 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
758 }
759
760 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
761 struct intel_sdvo_dtd *dtd)
762 {
763 return intel_sdvo_get_timing(intel_sdvo,
764 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
765 }
766
767 static bool
768 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
769 uint16_t clock,
770 uint16_t width,
771 uint16_t height)
772 {
773 struct intel_sdvo_preferred_input_timing_args args;
774
775 memset(&args, 0, sizeof(args));
776 args.clock = clock;
777 args.width = width;
778 args.height = height;
779 args.interlace = 0;
780
781 if (intel_sdvo->is_lvds &&
782 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
783 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
784 args.scaled = 1;
785
786 return intel_sdvo_set_value(intel_sdvo,
787 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
788 &args, sizeof(args));
789 }
790
791 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
792 struct intel_sdvo_dtd *dtd)
793 {
794 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
795 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
796 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
797 &dtd->part1, sizeof(dtd->part1)) &&
798 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
799 &dtd->part2, sizeof(dtd->part2));
800 }
801
802 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
803 {
804 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
805 }
806
807 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
808 const struct drm_display_mode *mode)
809 {
810 uint16_t width, height;
811 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
812 uint16_t h_sync_offset, v_sync_offset;
813 int mode_clock;
814
815 memset(dtd, 0, sizeof(*dtd));
816
817 width = mode->hdisplay;
818 height = mode->vdisplay;
819
820 /* do some mode translations */
821 h_blank_len = mode->htotal - mode->hdisplay;
822 h_sync_len = mode->hsync_end - mode->hsync_start;
823
824 v_blank_len = mode->vtotal - mode->vdisplay;
825 v_sync_len = mode->vsync_end - mode->vsync_start;
826
827 h_sync_offset = mode->hsync_start - mode->hdisplay;
828 v_sync_offset = mode->vsync_start - mode->vdisplay;
829
830 mode_clock = mode->clock;
831 mode_clock /= 10;
832 dtd->part1.clock = mode_clock;
833
834 dtd->part1.h_active = width & 0xff;
835 dtd->part1.h_blank = h_blank_len & 0xff;
836 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
837 ((h_blank_len >> 8) & 0xf);
838 dtd->part1.v_active = height & 0xff;
839 dtd->part1.v_blank = v_blank_len & 0xff;
840 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
841 ((v_blank_len >> 8) & 0xf);
842
843 dtd->part2.h_sync_off = h_sync_offset & 0xff;
844 dtd->part2.h_sync_width = h_sync_len & 0xff;
845 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
846 (v_sync_len & 0xf);
847 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
848 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
849 ((v_sync_len & 0x30) >> 4);
850
851 dtd->part2.dtd_flags = 0x18;
852 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
853 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
854 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
855 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
856 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
857 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
858
859 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
860 }
861
862 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
863 const struct intel_sdvo_dtd *dtd)
864 {
865 struct drm_display_mode mode = {};
866
867 mode.hdisplay = dtd->part1.h_active;
868 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
869 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
870 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
871 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
872 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
873 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
874 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
875
876 mode.vdisplay = dtd->part1.v_active;
877 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
878 mode.vsync_start = mode.vdisplay;
879 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
880 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
881 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
882 mode.vsync_end = mode.vsync_start +
883 (dtd->part2.v_sync_off_width & 0xf);
884 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
885 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
886 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
887
888 mode.clock = dtd->part1.clock * 10;
889
890 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
891 mode.flags |= DRM_MODE_FLAG_INTERLACE;
892 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
893 mode.flags |= DRM_MODE_FLAG_PHSYNC;
894 else
895 mode.flags |= DRM_MODE_FLAG_NHSYNC;
896 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
897 mode.flags |= DRM_MODE_FLAG_PVSYNC;
898 else
899 mode.flags |= DRM_MODE_FLAG_NVSYNC;
900
901 drm_mode_set_crtcinfo(&mode, 0);
902
903 drm_mode_copy(pmode, &mode);
904 }
905
906 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
907 {
908 struct intel_sdvo_encode encode;
909
910 BUILD_BUG_ON(sizeof(encode) != 2);
911 return intel_sdvo_get_value(intel_sdvo,
912 SDVO_CMD_GET_SUPP_ENCODE,
913 &encode, sizeof(encode));
914 }
915
916 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
917 uint8_t mode)
918 {
919 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
920 }
921
922 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
923 uint8_t mode)
924 {
925 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
926 }
927
928 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
929 u8 audio_state)
930 {
931 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
932 &audio_state, 1);
933 }
934
935 #if 0
936 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
937 {
938 int i, j;
939 uint8_t set_buf_index[2];
940 uint8_t av_split;
941 uint8_t buf_size;
942 uint8_t buf[48];
943 uint8_t *pos;
944
945 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
946
947 for (i = 0; i <= av_split; i++) {
948 set_buf_index[0] = i; set_buf_index[1] = 0;
949 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
950 set_buf_index, 2);
951 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
952 intel_sdvo_read_response(encoder, &buf_size, 1);
953
954 pos = buf;
955 for (j = 0; j <= buf_size; j += 8) {
956 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
957 NULL, 0);
958 intel_sdvo_read_response(encoder, pos, 8);
959 pos += 8;
960 }
961 }
962 }
963 #endif
964
965 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
966 unsigned if_index, uint8_t tx_rate,
967 const uint8_t *data, unsigned length)
968 {
969 uint8_t set_buf_index[2] = { if_index, 0 };
970 uint8_t hbuf_size, tmp[8];
971 int i;
972
973 if (!intel_sdvo_set_value(intel_sdvo,
974 SDVO_CMD_SET_HBUF_INDEX,
975 set_buf_index, 2))
976 return false;
977
978 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
979 &hbuf_size, 1))
980 return false;
981
982 /* Buffer size is 0 based, hooray! */
983 hbuf_size++;
984
985 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
986 if_index, length, hbuf_size);
987
988 for (i = 0; i < hbuf_size; i += 8) {
989 memset(tmp, 0, 8);
990 if (i < length)
991 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
992
993 if (!intel_sdvo_set_value(intel_sdvo,
994 SDVO_CMD_SET_HBUF_DATA,
995 tmp, 8))
996 return false;
997 }
998
999 return intel_sdvo_set_value(intel_sdvo,
1000 SDVO_CMD_SET_HBUF_TXRATE,
1001 &tx_rate, 1);
1002 }
1003
1004 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1005 const struct intel_crtc_state *pipe_config)
1006 {
1007 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1008 union hdmi_infoframe frame;
1009 int ret;
1010 ssize_t len;
1011
1012 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
1013 &pipe_config->base.adjusted_mode,
1014 false);
1015 if (ret < 0) {
1016 DRM_ERROR("couldn't fill AVI infoframe\n");
1017 return false;
1018 }
1019
1020 if (intel_sdvo->rgb_quant_range_selectable) {
1021 if (pipe_config->limited_color_range)
1022 frame.avi.quantization_range =
1023 HDMI_QUANTIZATION_RANGE_LIMITED;
1024 else
1025 frame.avi.quantization_range =
1026 HDMI_QUANTIZATION_RANGE_FULL;
1027 }
1028
1029 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1030 if (len < 0)
1031 return false;
1032
1033 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1034 SDVO_HBUF_TX_VSYNC,
1035 sdvo_data, sizeof(sdvo_data));
1036 }
1037
1038 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1039 const struct drm_connector_state *conn_state)
1040 {
1041 struct intel_sdvo_tv_format format;
1042 uint32_t format_map;
1043
1044 format_map = 1 << conn_state->tv.mode;
1045 memset(&format, 0, sizeof(format));
1046 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1047
1048 BUILD_BUG_ON(sizeof(format) != 6);
1049 return intel_sdvo_set_value(intel_sdvo,
1050 SDVO_CMD_SET_TV_FORMAT,
1051 &format, sizeof(format));
1052 }
1053
1054 static bool
1055 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1056 const struct drm_display_mode *mode)
1057 {
1058 struct intel_sdvo_dtd output_dtd;
1059
1060 if (!intel_sdvo_set_target_output(intel_sdvo,
1061 intel_sdvo->attached_output))
1062 return false;
1063
1064 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1065 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1066 return false;
1067
1068 return true;
1069 }
1070
1071 /*
1072 * Asks the sdvo controller for the preferred input mode given the output mode.
1073 * Unfortunately we have to set up the full output mode to do that.
1074 */
1075 static bool
1076 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1077 const struct drm_display_mode *mode,
1078 struct drm_display_mode *adjusted_mode)
1079 {
1080 struct intel_sdvo_dtd input_dtd;
1081
1082 /* Reset the input timing to the screen. Assume always input 0. */
1083 if (!intel_sdvo_set_target_input(intel_sdvo))
1084 return false;
1085
1086 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1087 mode->clock / 10,
1088 mode->hdisplay,
1089 mode->vdisplay))
1090 return false;
1091
1092 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1093 &input_dtd))
1094 return false;
1095
1096 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1097 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1098
1099 return true;
1100 }
1101
1102 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1103 {
1104 unsigned dotclock = pipe_config->port_clock;
1105 struct dpll *clock = &pipe_config->dpll;
1106
1107 /*
1108 * SDVO TV has fixed PLL values depend on its clock range,
1109 * this mirrors vbios setting.
1110 */
1111 if (dotclock >= 100000 && dotclock < 140500) {
1112 clock->p1 = 2;
1113 clock->p2 = 10;
1114 clock->n = 3;
1115 clock->m1 = 16;
1116 clock->m2 = 8;
1117 } else if (dotclock >= 140500 && dotclock <= 200000) {
1118 clock->p1 = 1;
1119 clock->p2 = 10;
1120 clock->n = 6;
1121 clock->m1 = 12;
1122 clock->m2 = 8;
1123 } else {
1124 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1125 }
1126
1127 pipe_config->clock_set = true;
1128 }
1129
1130 static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1131 struct intel_crtc_state *pipe_config,
1132 struct drm_connector_state *conn_state)
1133 {
1134 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1135 struct intel_sdvo_connector_state *intel_sdvo_state =
1136 to_intel_sdvo_connector_state(conn_state);
1137 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1138 struct drm_display_mode *mode = &pipe_config->base.mode;
1139
1140 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1141 pipe_config->pipe_bpp = 8*3;
1142
1143 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1144 pipe_config->has_pch_encoder = true;
1145
1146 /*
1147 * We need to construct preferred input timings based on our
1148 * output timings. To do that, we have to set the output
1149 * timings, even though this isn't really the right place in
1150 * the sequence to do it. Oh well.
1151 */
1152 if (intel_sdvo->is_tv) {
1153 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1154 return false;
1155
1156 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1157 mode,
1158 adjusted_mode);
1159 pipe_config->sdvo_tv_clock = true;
1160 } else if (intel_sdvo->is_lvds) {
1161 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1162 intel_sdvo->sdvo_lvds_fixed_mode))
1163 return false;
1164
1165 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1166 mode,
1167 adjusted_mode);
1168 }
1169
1170 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1171 return false;
1172
1173 /*
1174 * Make the CRTC code factor in the SDVO pixel multiplier. The
1175 * SDVO device will factor out the multiplier during mode_set.
1176 */
1177 pipe_config->pixel_multiplier =
1178 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1179
1180 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
1181 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1182
1183 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1184 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
1185 pipe_config->has_audio = true;
1186
1187 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1188 /*
1189 * See CEA-861-E - 5.1 Default Encoding Parameters
1190 *
1191 * FIXME: This bit is only valid when using TMDS encoding and 8
1192 * bit per color mode.
1193 */
1194 if (pipe_config->has_hdmi_sink &&
1195 drm_match_cea_mode(adjusted_mode) > 1)
1196 pipe_config->limited_color_range = true;
1197 } else {
1198 if (pipe_config->has_hdmi_sink &&
1199 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
1200 pipe_config->limited_color_range = true;
1201 }
1202
1203 /* Clock computation needs to happen after pixel multiplier. */
1204 if (intel_sdvo->is_tv)
1205 i9xx_adjust_sdvo_tv_clock(pipe_config);
1206
1207 /* Set user selected PAR to incoming mode's member */
1208 if (intel_sdvo->is_hdmi)
1209 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1210
1211 return true;
1212 }
1213
1214 #define UPDATE_PROPERTY(input, NAME) \
1215 do { \
1216 val = input; \
1217 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1218 } while (0)
1219
1220 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1221 const struct intel_sdvo_connector_state *sdvo_state)
1222 {
1223 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1224 struct intel_sdvo_connector *intel_sdvo_conn =
1225 to_intel_sdvo_connector(conn_state->connector);
1226 uint16_t val;
1227
1228 if (intel_sdvo_conn->left)
1229 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1230
1231 if (intel_sdvo_conn->top)
1232 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1233
1234 if (intel_sdvo_conn->hpos)
1235 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1236
1237 if (intel_sdvo_conn->vpos)
1238 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1239
1240 if (intel_sdvo_conn->saturation)
1241 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1242
1243 if (intel_sdvo_conn->contrast)
1244 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1245
1246 if (intel_sdvo_conn->hue)
1247 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1248
1249 if (intel_sdvo_conn->brightness)
1250 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1251
1252 if (intel_sdvo_conn->sharpness)
1253 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1254
1255 if (intel_sdvo_conn->flicker_filter)
1256 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1257
1258 if (intel_sdvo_conn->flicker_filter_2d)
1259 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1260
1261 if (intel_sdvo_conn->flicker_filter_adaptive)
1262 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1263
1264 if (intel_sdvo_conn->tv_chroma_filter)
1265 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1266
1267 if (intel_sdvo_conn->tv_luma_filter)
1268 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1269
1270 if (intel_sdvo_conn->dot_crawl)
1271 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1272
1273 #undef UPDATE_PROPERTY
1274 }
1275
1276 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1277 const struct intel_crtc_state *crtc_state,
1278 const struct drm_connector_state *conn_state)
1279 {
1280 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1281 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1282 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1283 const struct intel_sdvo_connector_state *sdvo_state =
1284 to_intel_sdvo_connector_state(conn_state);
1285 const struct drm_display_mode *mode = &crtc_state->base.mode;
1286 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1287 u32 sdvox;
1288 struct intel_sdvo_in_out_map in_out;
1289 struct intel_sdvo_dtd input_dtd, output_dtd;
1290 int rate;
1291
1292 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1293
1294 /*
1295 * First, set the input mapping for the first input to our controlled
1296 * output. This is only correct if we're a single-input device, in
1297 * which case the first input is the output from the appropriate SDVO
1298 * channel on the motherboard. In a two-input device, the first input
1299 * will be SDVOB and the second SDVOC.
1300 */
1301 in_out.in0 = intel_sdvo->attached_output;
1302 in_out.in1 = 0;
1303
1304 intel_sdvo_set_value(intel_sdvo,
1305 SDVO_CMD_SET_IN_OUT_MAP,
1306 &in_out, sizeof(in_out));
1307
1308 /* Set the output timings to the screen */
1309 if (!intel_sdvo_set_target_output(intel_sdvo,
1310 intel_sdvo->attached_output))
1311 return;
1312
1313 /* lvds has a special fixed output timing. */
1314 if (intel_sdvo->is_lvds)
1315 intel_sdvo_get_dtd_from_mode(&output_dtd,
1316 intel_sdvo->sdvo_lvds_fixed_mode);
1317 else
1318 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1319 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1320 DRM_INFO("Setting output timings on %s failed\n",
1321 SDVO_NAME(intel_sdvo));
1322
1323 /* Set the input timing to the screen. Assume always input 0. */
1324 if (!intel_sdvo_set_target_input(intel_sdvo))
1325 return;
1326
1327 if (crtc_state->has_hdmi_sink) {
1328 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1329 intel_sdvo_set_colorimetry(intel_sdvo,
1330 SDVO_COLORIMETRY_RGB256);
1331 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1332 } else
1333 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1334
1335 if (intel_sdvo->is_tv &&
1336 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1337 return;
1338
1339 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1340
1341 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1342 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1343 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1344 DRM_INFO("Setting input timings on %s failed\n",
1345 SDVO_NAME(intel_sdvo));
1346
1347 switch (crtc_state->pixel_multiplier) {
1348 default:
1349 WARN(1, "unknown pixel multiplier specified\n");
1350 /* fall through */
1351 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1352 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1353 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1354 }
1355 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1356 return;
1357
1358 /* Set the SDVO control regs. */
1359 if (INTEL_GEN(dev_priv) >= 4) {
1360 /* The real mode polarity is set by the SDVO commands, using
1361 * struct intel_sdvo_dtd. */
1362 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1363 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1364 sdvox |= HDMI_COLOR_RANGE_16_235;
1365 if (INTEL_GEN(dev_priv) < 5)
1366 sdvox |= SDVO_BORDER_ENABLE;
1367 } else {
1368 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1369 if (intel_sdvo->port == PORT_B)
1370 sdvox &= SDVOB_PRESERVE_MASK;
1371 else
1372 sdvox &= SDVOC_PRESERVE_MASK;
1373 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1374 }
1375
1376 if (HAS_PCH_CPT(dev_priv))
1377 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1378 else
1379 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1380
1381 if (INTEL_GEN(dev_priv) >= 4) {
1382 /* done in crtc_mode_set as the dpll_md reg must be written early */
1383 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1384 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1385 /* done in crtc_mode_set as it lives inside the dpll register */
1386 } else {
1387 sdvox |= (crtc_state->pixel_multiplier - 1)
1388 << SDVO_PORT_MULTIPLY_SHIFT;
1389 }
1390
1391 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1392 INTEL_GEN(dev_priv) < 5)
1393 sdvox |= SDVO_STALL_SELECT;
1394 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1395 }
1396
1397 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1398 {
1399 struct intel_sdvo_connector *intel_sdvo_connector =
1400 to_intel_sdvo_connector(&connector->base);
1401 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1402 u16 active_outputs = 0;
1403
1404 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1405
1406 return active_outputs & intel_sdvo_connector->output_flag;
1407 }
1408
1409 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1410 i915_reg_t sdvo_reg, enum pipe *pipe)
1411 {
1412 u32 val;
1413
1414 val = I915_READ(sdvo_reg);
1415
1416 /* asserts want to know the pipe even if the port is disabled */
1417 if (HAS_PCH_CPT(dev_priv))
1418 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1419 else if (IS_CHERRYVIEW(dev_priv))
1420 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1421 else
1422 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1423
1424 return val & SDVO_ENABLE;
1425 }
1426
1427 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1428 enum pipe *pipe)
1429 {
1430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1431 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1432 u16 active_outputs = 0;
1433 bool ret;
1434
1435 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1436
1437 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1438
1439 return ret || active_outputs;
1440 }
1441
1442 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1443 struct intel_crtc_state *pipe_config)
1444 {
1445 struct drm_device *dev = encoder->base.dev;
1446 struct drm_i915_private *dev_priv = to_i915(dev);
1447 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1448 struct intel_sdvo_dtd dtd;
1449 int encoder_pixel_multiplier = 0;
1450 int dotclock;
1451 u32 flags = 0, sdvox;
1452 u8 val;
1453 bool ret;
1454
1455 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1456
1457 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1458
1459 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1460 if (!ret) {
1461 /*
1462 * Some sdvo encoders are not spec compliant and don't
1463 * implement the mandatory get_timings function.
1464 */
1465 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1466 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1467 } else {
1468 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1469 flags |= DRM_MODE_FLAG_PHSYNC;
1470 else
1471 flags |= DRM_MODE_FLAG_NHSYNC;
1472
1473 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1474 flags |= DRM_MODE_FLAG_PVSYNC;
1475 else
1476 flags |= DRM_MODE_FLAG_NVSYNC;
1477 }
1478
1479 pipe_config->base.adjusted_mode.flags |= flags;
1480
1481 /*
1482 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1483 * the sdvo port register, on all other platforms it is part of the dpll
1484 * state. Since the general pipe state readout happens before the
1485 * encoder->get_config we so already have a valid pixel multplier on all
1486 * other platfroms.
1487 */
1488 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1489 pipe_config->pixel_multiplier =
1490 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1491 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1492 }
1493
1494 dotclock = pipe_config->port_clock;
1495
1496 if (pipe_config->pixel_multiplier)
1497 dotclock /= pipe_config->pixel_multiplier;
1498
1499 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1500
1501 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1502 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1503 &val, 1)) {
1504 switch (val) {
1505 case SDVO_CLOCK_RATE_MULT_1X:
1506 encoder_pixel_multiplier = 1;
1507 break;
1508 case SDVO_CLOCK_RATE_MULT_2X:
1509 encoder_pixel_multiplier = 2;
1510 break;
1511 case SDVO_CLOCK_RATE_MULT_4X:
1512 encoder_pixel_multiplier = 4;
1513 break;
1514 }
1515 }
1516
1517 if (sdvox & HDMI_COLOR_RANGE_16_235)
1518 pipe_config->limited_color_range = true;
1519
1520 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1521 &val, 1)) {
1522 u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT;
1523
1524 if ((val & mask) == mask)
1525 pipe_config->has_audio = true;
1526 }
1527
1528 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1529 &val, 1)) {
1530 if (val == SDVO_ENCODE_HDMI)
1531 pipe_config->has_hdmi_sink = true;
1532 }
1533
1534 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1535 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1536 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1537 }
1538
1539 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1540 {
1541 intel_sdvo_set_audio_state(intel_sdvo, 0);
1542 }
1543
1544 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1545 const struct intel_crtc_state *crtc_state,
1546 const struct drm_connector_state *conn_state)
1547 {
1548 const struct drm_display_mode *adjusted_mode =
1549 &crtc_state->base.adjusted_mode;
1550 struct drm_connector *connector = conn_state->connector;
1551 u8 *eld = connector->eld;
1552
1553 eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
1554
1555 intel_sdvo_set_audio_state(intel_sdvo, 0);
1556
1557 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1558 SDVO_HBUF_TX_DISABLED,
1559 eld, drm_eld_size(eld));
1560
1561 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1562 SDVO_AUDIO_PRESENCE_DETECT);
1563 }
1564
1565 static void intel_disable_sdvo(struct intel_encoder *encoder,
1566 const struct intel_crtc_state *old_crtc_state,
1567 const struct drm_connector_state *conn_state)
1568 {
1569 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1570 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1571 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1572 u32 temp;
1573
1574 if (old_crtc_state->has_audio)
1575 intel_sdvo_disable_audio(intel_sdvo);
1576
1577 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1578 if (0)
1579 intel_sdvo_set_encoder_power_state(intel_sdvo,
1580 DRM_MODE_DPMS_OFF);
1581
1582 temp = I915_READ(intel_sdvo->sdvo_reg);
1583
1584 temp &= ~SDVO_ENABLE;
1585 intel_sdvo_write_sdvox(intel_sdvo, temp);
1586
1587 /*
1588 * HW workaround for IBX, we need to move the port
1589 * to transcoder A after disabling it to allow the
1590 * matching DP port to be enabled on transcoder A.
1591 */
1592 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1593 /*
1594 * We get CPU/PCH FIFO underruns on the other pipe when
1595 * doing the workaround. Sweep them under the rug.
1596 */
1597 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1598 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1599
1600 temp &= ~SDVO_PIPE_SEL_MASK;
1601 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1602 intel_sdvo_write_sdvox(intel_sdvo, temp);
1603
1604 temp &= ~SDVO_ENABLE;
1605 intel_sdvo_write_sdvox(intel_sdvo, temp);
1606
1607 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1608 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1609 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1610 }
1611 }
1612
1613 static void pch_disable_sdvo(struct intel_encoder *encoder,
1614 const struct intel_crtc_state *old_crtc_state,
1615 const struct drm_connector_state *old_conn_state)
1616 {
1617 }
1618
1619 static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1620 const struct intel_crtc_state *old_crtc_state,
1621 const struct drm_connector_state *old_conn_state)
1622 {
1623 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
1624 }
1625
1626 static void intel_enable_sdvo(struct intel_encoder *encoder,
1627 const struct intel_crtc_state *pipe_config,
1628 const struct drm_connector_state *conn_state)
1629 {
1630 struct drm_device *dev = encoder->base.dev;
1631 struct drm_i915_private *dev_priv = to_i915(dev);
1632 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1633 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1634 u32 temp;
1635 bool input1, input2;
1636 int i;
1637 bool success;
1638
1639 temp = I915_READ(intel_sdvo->sdvo_reg);
1640 temp |= SDVO_ENABLE;
1641 intel_sdvo_write_sdvox(intel_sdvo, temp);
1642
1643 for (i = 0; i < 2; i++)
1644 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
1645
1646 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1647 /*
1648 * Warn if the device reported failure to sync.
1649 *
1650 * A lot of SDVO devices fail to notify of sync, but it's
1651 * a given it the status is a success, we succeeded.
1652 */
1653 if (success && !input1) {
1654 DRM_DEBUG_KMS("First %s output reported failure to "
1655 "sync\n", SDVO_NAME(intel_sdvo));
1656 }
1657
1658 if (0)
1659 intel_sdvo_set_encoder_power_state(intel_sdvo,
1660 DRM_MODE_DPMS_ON);
1661 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1662
1663 if (pipe_config->has_audio)
1664 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
1665 }
1666
1667 static enum drm_mode_status
1668 intel_sdvo_mode_valid(struct drm_connector *connector,
1669 struct drm_display_mode *mode)
1670 {
1671 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1672 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1673
1674 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1675 return MODE_NO_DBLESCAN;
1676
1677 if (intel_sdvo->pixel_clock_min > mode->clock)
1678 return MODE_CLOCK_LOW;
1679
1680 if (intel_sdvo->pixel_clock_max < mode->clock)
1681 return MODE_CLOCK_HIGH;
1682
1683 if (mode->clock > max_dotclk)
1684 return MODE_CLOCK_HIGH;
1685
1686 if (intel_sdvo->is_lvds) {
1687 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1688 return MODE_PANEL;
1689
1690 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1691 return MODE_PANEL;
1692 }
1693
1694 return MODE_OK;
1695 }
1696
1697 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1698 {
1699 BUILD_BUG_ON(sizeof(*caps) != 8);
1700 if (!intel_sdvo_get_value(intel_sdvo,
1701 SDVO_CMD_GET_DEVICE_CAPS,
1702 caps, sizeof(*caps)))
1703 return false;
1704
1705 DRM_DEBUG_KMS("SDVO capabilities:\n"
1706 " vendor_id: %d\n"
1707 " device_id: %d\n"
1708 " device_rev_id: %d\n"
1709 " sdvo_version_major: %d\n"
1710 " sdvo_version_minor: %d\n"
1711 " sdvo_inputs_mask: %d\n"
1712 " smooth_scaling: %d\n"
1713 " sharp_scaling: %d\n"
1714 " up_scaling: %d\n"
1715 " down_scaling: %d\n"
1716 " stall_support: %d\n"
1717 " output_flags: %d\n",
1718 caps->vendor_id,
1719 caps->device_id,
1720 caps->device_rev_id,
1721 caps->sdvo_version_major,
1722 caps->sdvo_version_minor,
1723 caps->sdvo_inputs_mask,
1724 caps->smooth_scaling,
1725 caps->sharp_scaling,
1726 caps->up_scaling,
1727 caps->down_scaling,
1728 caps->stall_support,
1729 caps->output_flags);
1730
1731 return true;
1732 }
1733
1734 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1735 {
1736 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1737 uint16_t hotplug;
1738
1739 if (!I915_HAS_HOTPLUG(dev_priv))
1740 return 0;
1741
1742 /*
1743 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1744 * on the line.
1745 */
1746 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1747 return 0;
1748
1749 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1750 &hotplug, sizeof(hotplug)))
1751 return 0;
1752
1753 return hotplug;
1754 }
1755
1756 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1757 {
1758 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1759
1760 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1761 &intel_sdvo->hotplug_active, 2);
1762 }
1763
1764 static bool intel_sdvo_hotplug(struct intel_encoder *encoder,
1765 struct intel_connector *connector)
1766 {
1767 intel_sdvo_enable_hotplug(encoder);
1768
1769 return intel_encoder_hotplug(encoder, connector);
1770 }
1771
1772 static bool
1773 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1774 {
1775 /* Is there more than one type of output? */
1776 return hweight16(intel_sdvo->caps.output_flags) > 1;
1777 }
1778
1779 static struct edid *
1780 intel_sdvo_get_edid(struct drm_connector *connector)
1781 {
1782 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1783 return drm_get_edid(connector, &sdvo->ddc);
1784 }
1785
1786 /* Mac mini hack -- use the same DDC as the analog connector */
1787 static struct edid *
1788 intel_sdvo_get_analog_edid(struct drm_connector *connector)
1789 {
1790 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1791
1792 return drm_get_edid(connector,
1793 intel_gmbus_get_adapter(dev_priv,
1794 dev_priv->vbt.crt_ddc_pin));
1795 }
1796
1797 static enum drm_connector_status
1798 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1799 {
1800 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1801 enum drm_connector_status status;
1802 struct edid *edid;
1803
1804 edid = intel_sdvo_get_edid(connector);
1805
1806 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1807 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1808
1809 /*
1810 * Don't use the 1 as the argument of DDC bus switch to get
1811 * the EDID. It is used for SDVO SPD ROM.
1812 */
1813 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1814 intel_sdvo->ddc_bus = ddc;
1815 edid = intel_sdvo_get_edid(connector);
1816 if (edid)
1817 break;
1818 }
1819 /*
1820 * If we found the EDID on the other bus,
1821 * assume that is the correct DDC bus.
1822 */
1823 if (edid == NULL)
1824 intel_sdvo->ddc_bus = saved_ddc;
1825 }
1826
1827 /*
1828 * When there is no edid and no monitor is connected with VGA
1829 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1830 */
1831 if (edid == NULL)
1832 edid = intel_sdvo_get_analog_edid(connector);
1833
1834 status = connector_status_unknown;
1835 if (edid != NULL) {
1836 /* DDC bus is shared, match EDID to connector type */
1837 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1838 status = connector_status_connected;
1839 if (intel_sdvo->is_hdmi) {
1840 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1841 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1842 intel_sdvo->rgb_quant_range_selectable =
1843 drm_rgb_quant_range_selectable(edid);
1844 }
1845 } else
1846 status = connector_status_disconnected;
1847 kfree(edid);
1848 }
1849
1850 return status;
1851 }
1852
1853 static bool
1854 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1855 struct edid *edid)
1856 {
1857 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1858 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1859
1860 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1861 connector_is_digital, monitor_is_digital);
1862 return connector_is_digital == monitor_is_digital;
1863 }
1864
1865 static enum drm_connector_status
1866 intel_sdvo_detect(struct drm_connector *connector, bool force)
1867 {
1868 uint16_t response;
1869 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1870 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1871 enum drm_connector_status ret;
1872
1873 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1874 connector->base.id, connector->name);
1875
1876 if (!intel_sdvo_get_value(intel_sdvo,
1877 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1878 &response, 2))
1879 return connector_status_unknown;
1880
1881 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1882 response & 0xff, response >> 8,
1883 intel_sdvo_connector->output_flag);
1884
1885 if (response == 0)
1886 return connector_status_disconnected;
1887
1888 intel_sdvo->attached_output = response;
1889
1890 intel_sdvo->has_hdmi_monitor = false;
1891 intel_sdvo->has_hdmi_audio = false;
1892 intel_sdvo->rgb_quant_range_selectable = false;
1893
1894 if ((intel_sdvo_connector->output_flag & response) == 0)
1895 ret = connector_status_disconnected;
1896 else if (IS_TMDS(intel_sdvo_connector))
1897 ret = intel_sdvo_tmds_sink_detect(connector);
1898 else {
1899 struct edid *edid;
1900
1901 /* if we have an edid check it matches the connection */
1902 edid = intel_sdvo_get_edid(connector);
1903 if (edid == NULL)
1904 edid = intel_sdvo_get_analog_edid(connector);
1905 if (edid != NULL) {
1906 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1907 edid))
1908 ret = connector_status_connected;
1909 else
1910 ret = connector_status_disconnected;
1911
1912 kfree(edid);
1913 } else
1914 ret = connector_status_connected;
1915 }
1916
1917 /* May update encoder flag for like clock for SDVO TV, etc.*/
1918 if (ret == connector_status_connected) {
1919 intel_sdvo->is_tv = false;
1920 intel_sdvo->is_lvds = false;
1921
1922 if (response & SDVO_TV_MASK)
1923 intel_sdvo->is_tv = true;
1924 if (response & SDVO_LVDS_MASK)
1925 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1926 }
1927
1928 return ret;
1929 }
1930
1931 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1932 {
1933 struct edid *edid;
1934
1935 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1936 connector->base.id, connector->name);
1937
1938 /* set the bus switch and get the modes */
1939 edid = intel_sdvo_get_edid(connector);
1940
1941 /*
1942 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1943 * link between analog and digital outputs. So, if the regular SDVO
1944 * DDC fails, check to see if the analog output is disconnected, in
1945 * which case we'll look there for the digital DDC data.
1946 */
1947 if (edid == NULL)
1948 edid = intel_sdvo_get_analog_edid(connector);
1949
1950 if (edid != NULL) {
1951 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1952 edid)) {
1953 drm_connector_update_edid_property(connector, edid);
1954 drm_add_edid_modes(connector, edid);
1955 }
1956
1957 kfree(edid);
1958 }
1959 }
1960
1961 /*
1962 * Set of SDVO TV modes.
1963 * Note! This is in reply order (see loop in get_tv_modes).
1964 * XXX: all 60Hz refresh?
1965 */
1966 static const struct drm_display_mode sdvo_tv_modes[] = {
1967 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1968 416, 0, 200, 201, 232, 233, 0,
1969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1970 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1971 416, 0, 240, 241, 272, 273, 0,
1972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1973 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1974 496, 0, 300, 301, 332, 333, 0,
1975 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1976 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1977 736, 0, 350, 351, 382, 383, 0,
1978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1979 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1980 736, 0, 400, 401, 432, 433, 0,
1981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1982 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1983 736, 0, 480, 481, 512, 513, 0,
1984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1985 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1986 800, 0, 480, 481, 512, 513, 0,
1987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1988 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1989 800, 0, 576, 577, 608, 609, 0,
1990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1991 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1992 816, 0, 350, 351, 382, 383, 0,
1993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1994 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1995 816, 0, 400, 401, 432, 433, 0,
1996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1997 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1998 816, 0, 480, 481, 512, 513, 0,
1999 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2000 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2001 816, 0, 540, 541, 572, 573, 0,
2002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2003 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2004 816, 0, 576, 577, 608, 609, 0,
2005 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2006 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2007 864, 0, 576, 577, 608, 609, 0,
2008 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2009 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2010 896, 0, 600, 601, 632, 633, 0,
2011 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2012 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2013 928, 0, 624, 625, 656, 657, 0,
2014 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2015 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2016 1016, 0, 766, 767, 798, 799, 0,
2017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2018 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2019 1120, 0, 768, 769, 800, 801, 0,
2020 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2021 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2022 1376, 0, 1024, 1025, 1056, 1057, 0,
2023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2024 };
2025
2026 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
2027 {
2028 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2029 const struct drm_connector_state *conn_state = connector->state;
2030 struct intel_sdvo_sdtv_resolution_request tv_res;
2031 uint32_t reply = 0, format_map = 0;
2032 int i;
2033
2034 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2035 connector->base.id, connector->name);
2036
2037 /*
2038 * Read the list of supported input resolutions for the selected TV
2039 * format.
2040 */
2041 format_map = 1 << conn_state->tv.mode;
2042 memcpy(&tv_res, &format_map,
2043 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2044
2045 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2046 return;
2047
2048 BUILD_BUG_ON(sizeof(tv_res) != 3);
2049 if (!intel_sdvo_write_cmd(intel_sdvo,
2050 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2051 &tv_res, sizeof(tv_res)))
2052 return;
2053 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2054 return;
2055
2056 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
2057 if (reply & (1 << i)) {
2058 struct drm_display_mode *nmode;
2059 nmode = drm_mode_duplicate(connector->dev,
2060 &sdvo_tv_modes[i]);
2061 if (nmode)
2062 drm_mode_probed_add(connector, nmode);
2063 }
2064 }
2065
2066 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2067 {
2068 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2069 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2070 struct drm_display_mode *newmode;
2071
2072 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2073 connector->base.id, connector->name);
2074
2075 /*
2076 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2077 * SDVO->LVDS transcoders can't cope with the EDID mode.
2078 */
2079 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2080 newmode = drm_mode_duplicate(connector->dev,
2081 dev_priv->vbt.sdvo_lvds_vbt_mode);
2082 if (newmode != NULL) {
2083 /* Guarantee the mode is preferred */
2084 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2085 DRM_MODE_TYPE_DRIVER);
2086 drm_mode_probed_add(connector, newmode);
2087 }
2088 }
2089
2090 /*
2091 * Attempt to get the mode list from DDC.
2092 * Assume that the preferred modes are
2093 * arranged in priority order.
2094 */
2095 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2096
2097 list_for_each_entry(newmode, &connector->probed_modes, head) {
2098 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
2099 intel_sdvo->sdvo_lvds_fixed_mode =
2100 drm_mode_duplicate(connector->dev, newmode);
2101
2102 intel_sdvo->is_lvds = true;
2103 break;
2104 }
2105 }
2106 }
2107
2108 static int intel_sdvo_get_modes(struct drm_connector *connector)
2109 {
2110 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2111
2112 if (IS_TV(intel_sdvo_connector))
2113 intel_sdvo_get_tv_modes(connector);
2114 else if (IS_LVDS(intel_sdvo_connector))
2115 intel_sdvo_get_lvds_modes(connector);
2116 else
2117 intel_sdvo_get_ddc_modes(connector);
2118
2119 return !list_empty(&connector->probed_modes);
2120 }
2121
2122 static void intel_sdvo_destroy(struct drm_connector *connector)
2123 {
2124 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2125
2126 drm_connector_cleanup(connector);
2127 kfree(intel_sdvo_connector);
2128 }
2129
2130 static int
2131 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2132 const struct drm_connector_state *state,
2133 struct drm_property *property,
2134 uint64_t *val)
2135 {
2136 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2137 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2138
2139 if (property == intel_sdvo_connector->tv_format) {
2140 int i;
2141
2142 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2143 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2144 *val = i;
2145
2146 return 0;
2147 }
2148
2149 WARN_ON(1);
2150 *val = 0;
2151 } else if (property == intel_sdvo_connector->top ||
2152 property == intel_sdvo_connector->bottom)
2153 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2154 else if (property == intel_sdvo_connector->left ||
2155 property == intel_sdvo_connector->right)
2156 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2157 else if (property == intel_sdvo_connector->hpos)
2158 *val = sdvo_state->tv.hpos;
2159 else if (property == intel_sdvo_connector->vpos)
2160 *val = sdvo_state->tv.vpos;
2161 else if (property == intel_sdvo_connector->saturation)
2162 *val = state->tv.saturation;
2163 else if (property == intel_sdvo_connector->contrast)
2164 *val = state->tv.contrast;
2165 else if (property == intel_sdvo_connector->hue)
2166 *val = state->tv.hue;
2167 else if (property == intel_sdvo_connector->brightness)
2168 *val = state->tv.brightness;
2169 else if (property == intel_sdvo_connector->sharpness)
2170 *val = sdvo_state->tv.sharpness;
2171 else if (property == intel_sdvo_connector->flicker_filter)
2172 *val = sdvo_state->tv.flicker_filter;
2173 else if (property == intel_sdvo_connector->flicker_filter_2d)
2174 *val = sdvo_state->tv.flicker_filter_2d;
2175 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2176 *val = sdvo_state->tv.flicker_filter_adaptive;
2177 else if (property == intel_sdvo_connector->tv_chroma_filter)
2178 *val = sdvo_state->tv.chroma_filter;
2179 else if (property == intel_sdvo_connector->tv_luma_filter)
2180 *val = sdvo_state->tv.luma_filter;
2181 else if (property == intel_sdvo_connector->dot_crawl)
2182 *val = sdvo_state->tv.dot_crawl;
2183 else
2184 return intel_digital_connector_atomic_get_property(connector, state, property, val);
2185
2186 return 0;
2187 }
2188
2189 static int
2190 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2191 struct drm_connector_state *state,
2192 struct drm_property *property,
2193 uint64_t val)
2194 {
2195 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2196 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2197
2198 if (property == intel_sdvo_connector->tv_format) {
2199 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
2200
2201 if (state->crtc) {
2202 struct drm_crtc_state *crtc_state =
2203 drm_atomic_get_new_crtc_state(state->state, state->crtc);
2204
2205 crtc_state->connectors_changed = true;
2206 }
2207 } else if (property == intel_sdvo_connector->top ||
2208 property == intel_sdvo_connector->bottom)
2209 /* Cannot set these independent from each other */
2210 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2211 else if (property == intel_sdvo_connector->left ||
2212 property == intel_sdvo_connector->right)
2213 /* Cannot set these independent from each other */
2214 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2215 else if (property == intel_sdvo_connector->hpos)
2216 sdvo_state->tv.hpos = val;
2217 else if (property == intel_sdvo_connector->vpos)
2218 sdvo_state->tv.vpos = val;
2219 else if (property == intel_sdvo_connector->saturation)
2220 state->tv.saturation = val;
2221 else if (property == intel_sdvo_connector->contrast)
2222 state->tv.contrast = val;
2223 else if (property == intel_sdvo_connector->hue)
2224 state->tv.hue = val;
2225 else if (property == intel_sdvo_connector->brightness)
2226 state->tv.brightness = val;
2227 else if (property == intel_sdvo_connector->sharpness)
2228 sdvo_state->tv.sharpness = val;
2229 else if (property == intel_sdvo_connector->flicker_filter)
2230 sdvo_state->tv.flicker_filter = val;
2231 else if (property == intel_sdvo_connector->flicker_filter_2d)
2232 sdvo_state->tv.flicker_filter_2d = val;
2233 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2234 sdvo_state->tv.flicker_filter_adaptive = val;
2235 else if (property == intel_sdvo_connector->tv_chroma_filter)
2236 sdvo_state->tv.chroma_filter = val;
2237 else if (property == intel_sdvo_connector->tv_luma_filter)
2238 sdvo_state->tv.luma_filter = val;
2239 else if (property == intel_sdvo_connector->dot_crawl)
2240 sdvo_state->tv.dot_crawl = val;
2241 else
2242 return intel_digital_connector_atomic_set_property(connector, state, property, val);
2243
2244 return 0;
2245 }
2246
2247 static int
2248 intel_sdvo_connector_register(struct drm_connector *connector)
2249 {
2250 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2251 int ret;
2252
2253 ret = intel_connector_register(connector);
2254 if (ret)
2255 return ret;
2256
2257 return sysfs_create_link(&connector->kdev->kobj,
2258 &sdvo->ddc.dev.kobj,
2259 sdvo->ddc.dev.kobj.name);
2260 }
2261
2262 static void
2263 intel_sdvo_connector_unregister(struct drm_connector *connector)
2264 {
2265 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2266
2267 sysfs_remove_link(&connector->kdev->kobj,
2268 sdvo->ddc.dev.kobj.name);
2269 intel_connector_unregister(connector);
2270 }
2271
2272 static struct drm_connector_state *
2273 intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2274 {
2275 struct intel_sdvo_connector_state *state;
2276
2277 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2278 if (!state)
2279 return NULL;
2280
2281 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2282 return &state->base.base;
2283 }
2284
2285 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2286 .detect = intel_sdvo_detect,
2287 .fill_modes = drm_helper_probe_single_connector_modes,
2288 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2289 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
2290 .late_register = intel_sdvo_connector_register,
2291 .early_unregister = intel_sdvo_connector_unregister,
2292 .destroy = intel_sdvo_destroy,
2293 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2294 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2295 };
2296
2297 static int intel_sdvo_atomic_check(struct drm_connector *conn,
2298 struct drm_connector_state *new_conn_state)
2299 {
2300 struct drm_atomic_state *state = new_conn_state->state;
2301 struct drm_connector_state *old_conn_state =
2302 drm_atomic_get_old_connector_state(state, conn);
2303 struct intel_sdvo_connector_state *old_state =
2304 to_intel_sdvo_connector_state(old_conn_state);
2305 struct intel_sdvo_connector_state *new_state =
2306 to_intel_sdvo_connector_state(new_conn_state);
2307
2308 if (new_conn_state->crtc &&
2309 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2310 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2311 struct drm_crtc_state *crtc_state =
2312 drm_atomic_get_new_crtc_state(new_conn_state->state,
2313 new_conn_state->crtc);
2314
2315 crtc_state->connectors_changed = true;
2316 }
2317
2318 return intel_digital_connector_atomic_check(conn, new_conn_state);
2319 }
2320
2321 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2322 .get_modes = intel_sdvo_get_modes,
2323 .mode_valid = intel_sdvo_mode_valid,
2324 .atomic_check = intel_sdvo_atomic_check,
2325 };
2326
2327 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2328 {
2329 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2330
2331 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2332 drm_mode_destroy(encoder->dev,
2333 intel_sdvo->sdvo_lvds_fixed_mode);
2334
2335 i2c_del_adapter(&intel_sdvo->ddc);
2336 intel_encoder_destroy(encoder);
2337 }
2338
2339 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2340 .destroy = intel_sdvo_enc_destroy,
2341 };
2342
2343 static void
2344 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2345 {
2346 uint16_t mask = 0;
2347 unsigned int num_bits;
2348
2349 /*
2350 * Make a mask of outputs less than or equal to our own priority in the
2351 * list.
2352 */
2353 switch (sdvo->controlled_output) {
2354 case SDVO_OUTPUT_LVDS1:
2355 mask |= SDVO_OUTPUT_LVDS1;
2356 /* fall through */
2357 case SDVO_OUTPUT_LVDS0:
2358 mask |= SDVO_OUTPUT_LVDS0;
2359 /* fall through */
2360 case SDVO_OUTPUT_TMDS1:
2361 mask |= SDVO_OUTPUT_TMDS1;
2362 /* fall through */
2363 case SDVO_OUTPUT_TMDS0:
2364 mask |= SDVO_OUTPUT_TMDS0;
2365 /* fall through */
2366 case SDVO_OUTPUT_RGB1:
2367 mask |= SDVO_OUTPUT_RGB1;
2368 /* fall through */
2369 case SDVO_OUTPUT_RGB0:
2370 mask |= SDVO_OUTPUT_RGB0;
2371 break;
2372 }
2373
2374 /* Count bits to find what number we are in the priority list. */
2375 mask &= sdvo->caps.output_flags;
2376 num_bits = hweight16(mask);
2377 /* If more than 3 outputs, default to DDC bus 3 for now. */
2378 if (num_bits > 3)
2379 num_bits = 3;
2380
2381 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2382 sdvo->ddc_bus = 1 << num_bits;
2383 }
2384
2385 /*
2386 * Choose the appropriate DDC bus for control bus switch command for this
2387 * SDVO output based on the controlled output.
2388 *
2389 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2390 * outputs, then LVDS outputs.
2391 */
2392 static void
2393 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2394 struct intel_sdvo *sdvo)
2395 {
2396 struct sdvo_device_mapping *mapping;
2397
2398 if (sdvo->port == PORT_B)
2399 mapping = &dev_priv->vbt.sdvo_mappings[0];
2400 else
2401 mapping = &dev_priv->vbt.sdvo_mappings[1];
2402
2403 if (mapping->initialized)
2404 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2405 else
2406 intel_sdvo_guess_ddc_bus(sdvo);
2407 }
2408
2409 static void
2410 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2411 struct intel_sdvo *sdvo)
2412 {
2413 struct sdvo_device_mapping *mapping;
2414 u8 pin;
2415
2416 if (sdvo->port == PORT_B)
2417 mapping = &dev_priv->vbt.sdvo_mappings[0];
2418 else
2419 mapping = &dev_priv->vbt.sdvo_mappings[1];
2420
2421 if (mapping->initialized &&
2422 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2423 pin = mapping->i2c_pin;
2424 else
2425 pin = GMBUS_PIN_DPB;
2426
2427 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2428
2429 /*
2430 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2431 * our code totally fails once we start using gmbus. Hence fall back to
2432 * bit banging for now.
2433 */
2434 intel_gmbus_force_bit(sdvo->i2c, true);
2435 }
2436
2437 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2438 static void
2439 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2440 {
2441 intel_gmbus_force_bit(sdvo->i2c, false);
2442 }
2443
2444 static bool
2445 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2446 {
2447 return intel_sdvo_check_supp_encode(intel_sdvo);
2448 }
2449
2450 static u8
2451 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2452 struct intel_sdvo *sdvo)
2453 {
2454 struct sdvo_device_mapping *my_mapping, *other_mapping;
2455
2456 if (sdvo->port == PORT_B) {
2457 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2458 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
2459 } else {
2460 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2461 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
2462 }
2463
2464 /* If the BIOS described our SDVO device, take advantage of it. */
2465 if (my_mapping->slave_addr)
2466 return my_mapping->slave_addr;
2467
2468 /*
2469 * If the BIOS only described a different SDVO device, use the
2470 * address that it isn't using.
2471 */
2472 if (other_mapping->slave_addr) {
2473 if (other_mapping->slave_addr == 0x70)
2474 return 0x72;
2475 else
2476 return 0x70;
2477 }
2478
2479 /*
2480 * No SDVO device info is found for another DVO port,
2481 * so use mapping assumption we had before BIOS parsing.
2482 */
2483 if (sdvo->port == PORT_B)
2484 return 0x70;
2485 else
2486 return 0x72;
2487 }
2488
2489 static int
2490 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2491 struct intel_sdvo *encoder)
2492 {
2493 struct drm_connector *drm_connector;
2494 int ret;
2495
2496 drm_connector = &connector->base.base;
2497 ret = drm_connector_init(encoder->base.base.dev,
2498 drm_connector,
2499 &intel_sdvo_connector_funcs,
2500 connector->base.base.connector_type);
2501 if (ret < 0)
2502 return ret;
2503
2504 drm_connector_helper_add(drm_connector,
2505 &intel_sdvo_connector_helper_funcs);
2506
2507 connector->base.base.interlace_allowed = 1;
2508 connector->base.base.doublescan_allowed = 0;
2509 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2510 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2511
2512 intel_connector_attach_encoder(&connector->base, &encoder->base);
2513
2514 return 0;
2515 }
2516
2517 static void
2518 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2519 struct intel_sdvo_connector *connector)
2520 {
2521 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
2522
2523 intel_attach_force_audio_property(&connector->base.base);
2524 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
2525 intel_attach_broadcast_rgb_property(&connector->base.base);
2526 }
2527 intel_attach_aspect_ratio_property(&connector->base.base);
2528 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2529 }
2530
2531 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2532 {
2533 struct intel_sdvo_connector *sdvo_connector;
2534 struct intel_sdvo_connector_state *conn_state;
2535
2536 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2537 if (!sdvo_connector)
2538 return NULL;
2539
2540 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2541 if (!conn_state) {
2542 kfree(sdvo_connector);
2543 return NULL;
2544 }
2545
2546 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2547 &conn_state->base.base);
2548
2549 return sdvo_connector;
2550 }
2551
2552 static bool
2553 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2554 {
2555 struct drm_encoder *encoder = &intel_sdvo->base.base;
2556 struct drm_connector *connector;
2557 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2558 struct intel_connector *intel_connector;
2559 struct intel_sdvo_connector *intel_sdvo_connector;
2560
2561 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2562
2563 intel_sdvo_connector = intel_sdvo_connector_alloc();
2564 if (!intel_sdvo_connector)
2565 return false;
2566
2567 if (device == 0) {
2568 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2569 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2570 } else if (device == 1) {
2571 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2572 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2573 }
2574
2575 intel_connector = &intel_sdvo_connector->base;
2576 connector = &intel_connector->base;
2577 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2578 intel_sdvo_connector->output_flag) {
2579 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2580 /*
2581 * Some SDVO devices have one-shot hotplug interrupts.
2582 * Ensure that they get re-enabled when an interrupt happens.
2583 */
2584 intel_encoder->hotplug = intel_sdvo_hotplug;
2585 intel_sdvo_enable_hotplug(intel_encoder);
2586 } else {
2587 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2588 }
2589 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2590 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2591
2592 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2593 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2594 intel_sdvo->is_hdmi = true;
2595 }
2596
2597 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2598 kfree(intel_sdvo_connector);
2599 return false;
2600 }
2601
2602 if (intel_sdvo->is_hdmi)
2603 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2604
2605 return true;
2606 }
2607
2608 static bool
2609 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2610 {
2611 struct drm_encoder *encoder = &intel_sdvo->base.base;
2612 struct drm_connector *connector;
2613 struct intel_connector *intel_connector;
2614 struct intel_sdvo_connector *intel_sdvo_connector;
2615
2616 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2617
2618 intel_sdvo_connector = intel_sdvo_connector_alloc();
2619 if (!intel_sdvo_connector)
2620 return false;
2621
2622 intel_connector = &intel_sdvo_connector->base;
2623 connector = &intel_connector->base;
2624 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2625 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2626
2627 intel_sdvo->controlled_output |= type;
2628 intel_sdvo_connector->output_flag = type;
2629
2630 intel_sdvo->is_tv = true;
2631
2632 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2633 kfree(intel_sdvo_connector);
2634 return false;
2635 }
2636
2637 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2638 goto err;
2639
2640 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2641 goto err;
2642
2643 return true;
2644
2645 err:
2646 intel_sdvo_destroy(connector);
2647 return false;
2648 }
2649
2650 static bool
2651 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2652 {
2653 struct drm_encoder *encoder = &intel_sdvo->base.base;
2654 struct drm_connector *connector;
2655 struct intel_connector *intel_connector;
2656 struct intel_sdvo_connector *intel_sdvo_connector;
2657
2658 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2659
2660 intel_sdvo_connector = intel_sdvo_connector_alloc();
2661 if (!intel_sdvo_connector)
2662 return false;
2663
2664 intel_connector = &intel_sdvo_connector->base;
2665 connector = &intel_connector->base;
2666 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2667 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2668 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2669
2670 if (device == 0) {
2671 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2672 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2673 } else if (device == 1) {
2674 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2675 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2676 }
2677
2678 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2679 kfree(intel_sdvo_connector);
2680 return false;
2681 }
2682
2683 return true;
2684 }
2685
2686 static bool
2687 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2688 {
2689 struct drm_encoder *encoder = &intel_sdvo->base.base;
2690 struct drm_connector *connector;
2691 struct intel_connector *intel_connector;
2692 struct intel_sdvo_connector *intel_sdvo_connector;
2693
2694 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2695
2696 intel_sdvo_connector = intel_sdvo_connector_alloc();
2697 if (!intel_sdvo_connector)
2698 return false;
2699
2700 intel_connector = &intel_sdvo_connector->base;
2701 connector = &intel_connector->base;
2702 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2703 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2704
2705 if (device == 0) {
2706 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2707 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2708 } else if (device == 1) {
2709 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2710 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2711 }
2712
2713 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2714 kfree(intel_sdvo_connector);
2715 return false;
2716 }
2717
2718 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2719 goto err;
2720
2721 return true;
2722
2723 err:
2724 intel_sdvo_destroy(connector);
2725 return false;
2726 }
2727
2728 static bool
2729 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2730 {
2731 intel_sdvo->is_tv = false;
2732 intel_sdvo->is_lvds = false;
2733
2734 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2735
2736 if (flags & SDVO_OUTPUT_TMDS0)
2737 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2738 return false;
2739
2740 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2741 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2742 return false;
2743
2744 /* TV has no XXX1 function block */
2745 if (flags & SDVO_OUTPUT_SVID0)
2746 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2747 return false;
2748
2749 if (flags & SDVO_OUTPUT_CVBS0)
2750 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2751 return false;
2752
2753 if (flags & SDVO_OUTPUT_YPRPB0)
2754 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2755 return false;
2756
2757 if (flags & SDVO_OUTPUT_RGB0)
2758 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2759 return false;
2760
2761 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2762 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2763 return false;
2764
2765 if (flags & SDVO_OUTPUT_LVDS0)
2766 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2767 return false;
2768
2769 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2770 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2771 return false;
2772
2773 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2774 unsigned char bytes[2];
2775
2776 intel_sdvo->controlled_output = 0;
2777 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2778 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2779 SDVO_NAME(intel_sdvo),
2780 bytes[0], bytes[1]);
2781 return false;
2782 }
2783 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2784
2785 return true;
2786 }
2787
2788 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2789 {
2790 struct drm_device *dev = intel_sdvo->base.base.dev;
2791 struct drm_connector *connector, *tmp;
2792
2793 list_for_each_entry_safe(connector, tmp,
2794 &dev->mode_config.connector_list, head) {
2795 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2796 drm_connector_unregister(connector);
2797 intel_sdvo_destroy(connector);
2798 }
2799 }
2800 }
2801
2802 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2803 struct intel_sdvo_connector *intel_sdvo_connector,
2804 int type)
2805 {
2806 struct drm_device *dev = intel_sdvo->base.base.dev;
2807 struct intel_sdvo_tv_format format;
2808 uint32_t format_map, i;
2809
2810 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2811 return false;
2812
2813 BUILD_BUG_ON(sizeof(format) != 6);
2814 if (!intel_sdvo_get_value(intel_sdvo,
2815 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2816 &format, sizeof(format)))
2817 return false;
2818
2819 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2820
2821 if (format_map == 0)
2822 return false;
2823
2824 intel_sdvo_connector->format_supported_num = 0;
2825 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2826 if (format_map & (1 << i))
2827 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2828
2829
2830 intel_sdvo_connector->tv_format =
2831 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2832 "mode", intel_sdvo_connector->format_supported_num);
2833 if (!intel_sdvo_connector->tv_format)
2834 return false;
2835
2836 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2837 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
2838 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2839
2840 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
2841 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2842 intel_sdvo_connector->tv_format, 0);
2843 return true;
2844
2845 }
2846
2847 #define _ENHANCEMENT(state_assignment, name, NAME) do { \
2848 if (enhancements.name) { \
2849 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2850 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2851 return false; \
2852 intel_sdvo_connector->name = \
2853 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2854 if (!intel_sdvo_connector->name) return false; \
2855 state_assignment = response; \
2856 drm_object_attach_property(&connector->base, \
2857 intel_sdvo_connector->name, 0); \
2858 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2859 data_value[0], data_value[1], response); \
2860 } \
2861 } while (0)
2862
2863 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2864
2865 static bool
2866 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2867 struct intel_sdvo_connector *intel_sdvo_connector,
2868 struct intel_sdvo_enhancements_reply enhancements)
2869 {
2870 struct drm_device *dev = intel_sdvo->base.base.dev;
2871 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2872 struct drm_connector_state *conn_state = connector->state;
2873 struct intel_sdvo_connector_state *sdvo_state =
2874 to_intel_sdvo_connector_state(conn_state);
2875 uint16_t response, data_value[2];
2876
2877 /* when horizontal overscan is supported, Add the left/right property */
2878 if (enhancements.overscan_h) {
2879 if (!intel_sdvo_get_value(intel_sdvo,
2880 SDVO_CMD_GET_MAX_OVERSCAN_H,
2881 &data_value, 4))
2882 return false;
2883
2884 if (!intel_sdvo_get_value(intel_sdvo,
2885 SDVO_CMD_GET_OVERSCAN_H,
2886 &response, 2))
2887 return false;
2888
2889 sdvo_state->tv.overscan_h = response;
2890
2891 intel_sdvo_connector->max_hscan = data_value[0];
2892 intel_sdvo_connector->left =
2893 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2894 if (!intel_sdvo_connector->left)
2895 return false;
2896
2897 drm_object_attach_property(&connector->base,
2898 intel_sdvo_connector->left, 0);
2899
2900 intel_sdvo_connector->right =
2901 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2902 if (!intel_sdvo_connector->right)
2903 return false;
2904
2905 drm_object_attach_property(&connector->base,
2906 intel_sdvo_connector->right, 0);
2907 DRM_DEBUG_KMS("h_overscan: max %d, "
2908 "default %d, current %d\n",
2909 data_value[0], data_value[1], response);
2910 }
2911
2912 if (enhancements.overscan_v) {
2913 if (!intel_sdvo_get_value(intel_sdvo,
2914 SDVO_CMD_GET_MAX_OVERSCAN_V,
2915 &data_value, 4))
2916 return false;
2917
2918 if (!intel_sdvo_get_value(intel_sdvo,
2919 SDVO_CMD_GET_OVERSCAN_V,
2920 &response, 2))
2921 return false;
2922
2923 sdvo_state->tv.overscan_v = response;
2924
2925 intel_sdvo_connector->max_vscan = data_value[0];
2926 intel_sdvo_connector->top =
2927 drm_property_create_range(dev, 0,
2928 "top_margin", 0, data_value[0]);
2929 if (!intel_sdvo_connector->top)
2930 return false;
2931
2932 drm_object_attach_property(&connector->base,
2933 intel_sdvo_connector->top, 0);
2934
2935 intel_sdvo_connector->bottom =
2936 drm_property_create_range(dev, 0,
2937 "bottom_margin", 0, data_value[0]);
2938 if (!intel_sdvo_connector->bottom)
2939 return false;
2940
2941 drm_object_attach_property(&connector->base,
2942 intel_sdvo_connector->bottom, 0);
2943 DRM_DEBUG_KMS("v_overscan: max %d, "
2944 "default %d, current %d\n",
2945 data_value[0], data_value[1], response);
2946 }
2947
2948 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
2949 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
2950 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
2951 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
2952 ENHANCEMENT(&conn_state->tv, hue, HUE);
2953 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
2954 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
2955 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
2956 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2957 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
2958 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
2959 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
2960
2961 if (enhancements.dot_crawl) {
2962 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2963 return false;
2964
2965 sdvo_state->tv.dot_crawl = response & 0x1;
2966 intel_sdvo_connector->dot_crawl =
2967 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2968 if (!intel_sdvo_connector->dot_crawl)
2969 return false;
2970
2971 drm_object_attach_property(&connector->base,
2972 intel_sdvo_connector->dot_crawl, 0);
2973 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2974 }
2975
2976 return true;
2977 }
2978
2979 static bool
2980 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2981 struct intel_sdvo_connector *intel_sdvo_connector,
2982 struct intel_sdvo_enhancements_reply enhancements)
2983 {
2984 struct drm_device *dev = intel_sdvo->base.base.dev;
2985 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2986 uint16_t response, data_value[2];
2987
2988 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
2989
2990 return true;
2991 }
2992 #undef ENHANCEMENT
2993 #undef _ENHANCEMENT
2994
2995 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2996 struct intel_sdvo_connector *intel_sdvo_connector)
2997 {
2998 union {
2999 struct intel_sdvo_enhancements_reply reply;
3000 uint16_t response;
3001 } enhancements;
3002
3003 BUILD_BUG_ON(sizeof(enhancements) != 2);
3004
3005 if (!intel_sdvo_get_value(intel_sdvo,
3006 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3007 &enhancements, sizeof(enhancements)) ||
3008 enhancements.response == 0) {
3009 DRM_DEBUG_KMS("No enhancement is supported\n");
3010 return true;
3011 }
3012
3013 if (IS_TV(intel_sdvo_connector))
3014 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3015 else if (IS_LVDS(intel_sdvo_connector))
3016 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3017 else
3018 return true;
3019 }
3020
3021 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3022 struct i2c_msg *msgs,
3023 int num)
3024 {
3025 struct intel_sdvo *sdvo = adapter->algo_data;
3026
3027 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
3028 return -EIO;
3029
3030 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3031 }
3032
3033 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3034 {
3035 struct intel_sdvo *sdvo = adapter->algo_data;
3036 return sdvo->i2c->algo->functionality(sdvo->i2c);
3037 }
3038
3039 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3040 .master_xfer = intel_sdvo_ddc_proxy_xfer,
3041 .functionality = intel_sdvo_ddc_proxy_func
3042 };
3043
3044 static void proxy_lock_bus(struct i2c_adapter *adapter,
3045 unsigned int flags)
3046 {
3047 struct intel_sdvo *sdvo = adapter->algo_data;
3048 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3049 }
3050
3051 static int proxy_trylock_bus(struct i2c_adapter *adapter,
3052 unsigned int flags)
3053 {
3054 struct intel_sdvo *sdvo = adapter->algo_data;
3055 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3056 }
3057
3058 static void proxy_unlock_bus(struct i2c_adapter *adapter,
3059 unsigned int flags)
3060 {
3061 struct intel_sdvo *sdvo = adapter->algo_data;
3062 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3063 }
3064
3065 static const struct i2c_lock_operations proxy_lock_ops = {
3066 .lock_bus = proxy_lock_bus,
3067 .trylock_bus = proxy_trylock_bus,
3068 .unlock_bus = proxy_unlock_bus,
3069 };
3070
3071 static bool
3072 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
3073 struct drm_i915_private *dev_priv)
3074 {
3075 struct pci_dev *pdev = dev_priv->drm.pdev;
3076
3077 sdvo->ddc.owner = THIS_MODULE;
3078 sdvo->ddc.class = I2C_CLASS_DDC;
3079 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
3080 sdvo->ddc.dev.parent = &pdev->dev;
3081 sdvo->ddc.algo_data = sdvo;
3082 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
3083 sdvo->ddc.lock_ops = &proxy_lock_ops;
3084
3085 return i2c_add_adapter(&sdvo->ddc) == 0;
3086 }
3087
3088 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3089 enum port port)
3090 {
3091 if (HAS_PCH_SPLIT(dev_priv))
3092 WARN_ON(port != PORT_B);
3093 else
3094 WARN_ON(port != PORT_B && port != PORT_C);
3095 }
3096
3097 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3098 i915_reg_t sdvo_reg, enum port port)
3099 {
3100 struct intel_encoder *intel_encoder;
3101 struct intel_sdvo *intel_sdvo;
3102 int i;
3103
3104 assert_sdvo_port_valid(dev_priv, port);
3105
3106 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3107 if (!intel_sdvo)
3108 return false;
3109
3110 intel_sdvo->sdvo_reg = sdvo_reg;
3111 intel_sdvo->port = port;
3112 intel_sdvo->slave_addr =
3113 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3114 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3115 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3116 goto err_i2c_bus;
3117
3118 /* encoder type will be decided later */
3119 intel_encoder = &intel_sdvo->base;
3120 intel_encoder->type = INTEL_OUTPUT_SDVO;
3121 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3122 intel_encoder->port = port;
3123 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3124 &intel_sdvo_enc_funcs, 0,
3125 "SDVO %c", port_name(port));
3126
3127 /* Read the regs to test if we can talk to the device */
3128 for (i = 0; i < 0x40; i++) {
3129 u8 byte;
3130
3131 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3132 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3133 SDVO_NAME(intel_sdvo));
3134 goto err;
3135 }
3136 }
3137
3138 intel_encoder->compute_config = intel_sdvo_compute_config;
3139 if (HAS_PCH_SPLIT(dev_priv)) {
3140 intel_encoder->disable = pch_disable_sdvo;
3141 intel_encoder->post_disable = pch_post_disable_sdvo;
3142 } else {
3143 intel_encoder->disable = intel_disable_sdvo;
3144 }
3145 intel_encoder->pre_enable = intel_sdvo_pre_enable;
3146 intel_encoder->enable = intel_enable_sdvo;
3147 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3148 intel_encoder->get_config = intel_sdvo_get_config;
3149
3150 /* In default case sdvo lvds is false */
3151 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3152 goto err;
3153
3154 if (intel_sdvo_output_setup(intel_sdvo,
3155 intel_sdvo->caps.output_flags) != true) {
3156 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3157 SDVO_NAME(intel_sdvo));
3158 /* Output_setup can leave behind connectors! */
3159 goto err_output;
3160 }
3161
3162 /*
3163 * Only enable the hotplug irq if we need it, to work around noisy
3164 * hotplug lines.
3165 */
3166 if (intel_sdvo->hotplug_active) {
3167 if (intel_sdvo->port == PORT_B)
3168 intel_encoder->hpd_pin = HPD_SDVO_B;
3169 else
3170 intel_encoder->hpd_pin = HPD_SDVO_C;
3171 }
3172
3173 /*
3174 * Cloning SDVO with anything is often impossible, since the SDVO
3175 * encoder can request a special input timing mode. And even if that's
3176 * not the case we have evidence that cloning a plain unscaled mode with
3177 * VGA doesn't really work. Furthermore the cloning flags are way too
3178 * simplistic anyway to express such constraints, so just give up on
3179 * cloning for SDVO encoders.
3180 */
3181 intel_sdvo->base.cloneable = 0;
3182
3183 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
3184
3185 /* Set the input timing to the screen. Assume always input 0. */
3186 if (!intel_sdvo_set_target_input(intel_sdvo))
3187 goto err_output;
3188
3189 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3190 &intel_sdvo->pixel_clock_min,
3191 &intel_sdvo->pixel_clock_max))
3192 goto err_output;
3193
3194 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
3195 "clock range %dMHz - %dMHz, "
3196 "input 1: %c, input 2: %c, "
3197 "output 1: %c, output 2: %c\n",
3198 SDVO_NAME(intel_sdvo),
3199 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3200 intel_sdvo->caps.device_rev_id,
3201 intel_sdvo->pixel_clock_min / 1000,
3202 intel_sdvo->pixel_clock_max / 1000,
3203 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3204 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3205 /* check currently supported outputs */
3206 intel_sdvo->caps.output_flags &
3207 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
3208 intel_sdvo->caps.output_flags &
3209 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
3210 return true;
3211
3212 err_output:
3213 intel_sdvo_output_cleanup(intel_sdvo);
3214
3215 err:
3216 drm_encoder_cleanup(&intel_encoder->base);
3217 i2c_del_adapter(&intel_sdvo->ddc);
3218 err_i2c_bus:
3219 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3220 kfree(intel_sdvo);
3221
3222 return false;
3223 }
Linux with added FPC-III support