drivers/gpu/drm/i915/intel_sideband.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "i915_drv.h"
  26 #include "intel_drv.h"
  27
  28 /*
  29  * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
  30  * VLV_VLV2_PUNIT_HAS_0.8.docx
  31  */
  32
  33 /* Standard MMIO read, non-posted */
  34 #define SB_MRD_NP       0x00
  35 /* Standard MMIO write, non-posted */
  36 #define SB_MWR_NP       0x01
  37 /* Private register read, double-word addressing, non-posted */
  38 #define SB_CRRDDA_NP    0x06
  39 /* Private register write, double-word addressing, non-posted */
  40 #define SB_CRWRDA_NP    0x07
  41
  42 static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
  43                            u32 port, u32 opcode, u32 addr, u32 *val)
  44 {
  45         u32 cmd, be = 0xf, bar = 0;
  46         bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
  47
  48         cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
  49                 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
  50                 (bar << IOSF_BAR_SHIFT);
  51
  52         WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
  53
  54         if (intel_wait_for_register(dev_priv,
  55                                     VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
  56                                     5)) {
  57                 DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
  58                                  is_read ? "read" : "write");
  59                 return -EAGAIN;
  60         }
  61
  62         I915_WRITE(VLV_IOSF_ADDR, addr);
  63         I915_WRITE(VLV_IOSF_DATA, is_read ? 0 : *val);
  64         I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
  65
  66         if (intel_wait_for_register(dev_priv,
  67                                     VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
  68                                     5)) {
  69                 DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
  70                                  is_read ? "read" : "write");
  71                 return -ETIMEDOUT;
  72         }
  73
  74         if (is_read)
  75                 *val = I915_READ(VLV_IOSF_DATA);
  76
  77         return 0;
  78 }
  79
  80 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
  81 {
  82         u32 val = 0;
  83
  84         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
  85
  86         mutex_lock(&dev_priv->sb_lock);
  87         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
  88                         SB_CRRDDA_NP, addr, &val);
  89         mutex_unlock(&dev_priv->sb_lock);
  90
  91         return val;
  92 }
  93
  94 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
  95 {
  96         int err;
  97
  98         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
  99
 100         mutex_lock(&dev_priv->sb_lock);
 101         err = vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
 102                               SB_CRWRDA_NP, addr, &val);
 103         mutex_unlock(&dev_priv->sb_lock);
 104
 105         return err;
 106 }
 107
 108 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
 109 {
 110         u32 val = 0;
 111
 112         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
 113                         SB_CRRDDA_NP, reg, &val);
 114
 115         return val;
 116 }
 117
 118 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 119 {
 120         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
 121                         SB_CRWRDA_NP, reg, &val);
 122 }
 123
 124 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 125 {
 126         u32 val = 0;
 127
 128         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
 129
 130         mutex_lock(&dev_priv->sb_lock);
 131         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
 132                         SB_CRRDDA_NP, addr, &val);
 133         mutex_unlock(&dev_priv->sb_lock);
 134
 135         return val;
 136 }
 137
 138 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
 139 {
 140         u32 val = 0;
 141         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
 142                         SB_CRRDDA_NP, reg, &val);
 143         return val;
 144 }
 145
 146 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
 147                        u8 port, u32 reg, u32 val)
 148 {
 149         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
 150                         SB_CRWRDA_NP, reg, &val);
 151 }
 152
 153 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
 154 {
 155         u32 val = 0;
 156         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
 157                         SB_CRRDDA_NP, reg, &val);
 158         return val;
 159 }
 160
 161 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 162 {
 163         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
 164                         SB_CRWRDA_NP, reg, &val);
 165 }
 166
 167 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
 168 {
 169         u32 val = 0;
 170         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
 171                         SB_CRRDDA_NP, reg, &val);
 172         return val;
 173 }
 174
 175 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 176 {
 177         vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
 178                         SB_CRWRDA_NP, reg, &val);
 179 }
 180
 181 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
 182 {
 183         u32 val = 0;
 184
 185         vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
 186                         SB_MRD_NP, reg, &val);
 187
 188         /*
 189          * FIXME: There might be some registers where all 1's is a valid value,
 190          * so ideally we should check the register offset instead...
 191          */
 192         WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
 193              pipe_name(pipe), reg, val);
 194
 195         return val;
 196 }
 197
 198 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
 199 {
 200         vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
 201                         SB_MWR_NP, reg, &val);
 202 }
 203
 204 /* SBI access */
 205 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
 206                    enum intel_sbi_destination destination)
 207 {
 208         u32 value = 0;
 209         WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 210
 211         if (intel_wait_for_register(dev_priv,
 212                                     SBI_CTL_STAT, SBI_BUSY, 0,
 213                                     100)) {
 214                 DRM_ERROR("timeout waiting for SBI to become ready\n");
 215                 return 0;
 216         }
 217
 218         I915_WRITE(SBI_ADDR, (reg << 16));
 219         I915_WRITE(SBI_DATA, 0);
 220
 221         if (destination == SBI_ICLK)
 222                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
 223         else
 224                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
 225         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
 226
 227         if (intel_wait_for_register(dev_priv,
 228                                     SBI_CTL_STAT,
 229                                     SBI_BUSY,
 230                                     0,
 231                                     100)) {
 232                 DRM_ERROR("timeout waiting for SBI to complete read\n");
 233                 return 0;
 234         }
 235
 236         if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
 237                 DRM_ERROR("error during SBI read of reg %x\n", reg);
 238                 return 0;
 239         }
 240
 241         return I915_READ(SBI_DATA);
 242 }
 243
 244 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 245                      enum intel_sbi_destination destination)
 246 {
 247         u32 tmp;
 248
 249         WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 250
 251         if (intel_wait_for_register(dev_priv,
 252                                     SBI_CTL_STAT, SBI_BUSY, 0,
 253                                     100)) {
 254                 DRM_ERROR("timeout waiting for SBI to become ready\n");
 255                 return;
 256         }
 257
 258         I915_WRITE(SBI_ADDR, (reg << 16));
 259         I915_WRITE(SBI_DATA, value);
 260
 261         if (destination == SBI_ICLK)
 262                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
 263         else
 264                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
 265         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
 266
 267         if (intel_wait_for_register(dev_priv,
 268                                     SBI_CTL_STAT,
 269                                     SBI_BUSY,
 270                                     0,
 271                                     100)) {
 272                 DRM_ERROR("timeout waiting for SBI to complete write\n");
 273                 return;
 274         }
 275
 276         if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
 277                 DRM_ERROR("error during SBI write of %x to reg %x\n",
 278                           value, reg);
 279                 return;
 280         }
 281 }
 282
 283 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
 284 {
 285         u32 val = 0;
 286         vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
 287                         reg, &val);
 288         return val;
 289 }
 290
 291 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 292 {
 293         vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
 294                         reg, &val);
 295 }