2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_UNCORE_H__
26 #define __INTEL_UNCORE_H__
28 #include <linux/spinlock.h>
29 #include <linux/notifier.h>
30 #include <linux/hrtimer.h>
34 struct drm_i915_private
;
36 enum forcewake_domain_id
{
37 FW_DOMAIN_ID_RENDER
= 0,
40 FW_DOMAIN_ID_MEDIA_VDBOX0
,
41 FW_DOMAIN_ID_MEDIA_VDBOX1
,
42 FW_DOMAIN_ID_MEDIA_VDBOX2
,
43 FW_DOMAIN_ID_MEDIA_VDBOX3
,
44 FW_DOMAIN_ID_MEDIA_VEBOX0
,
45 FW_DOMAIN_ID_MEDIA_VEBOX1
,
50 enum forcewake_domains
{
51 FORCEWAKE_RENDER
= BIT(FW_DOMAIN_ID_RENDER
),
52 FORCEWAKE_BLITTER
= BIT(FW_DOMAIN_ID_BLITTER
),
53 FORCEWAKE_MEDIA
= BIT(FW_DOMAIN_ID_MEDIA
),
54 FORCEWAKE_MEDIA_VDBOX0
= BIT(FW_DOMAIN_ID_MEDIA_VDBOX0
),
55 FORCEWAKE_MEDIA_VDBOX1
= BIT(FW_DOMAIN_ID_MEDIA_VDBOX1
),
56 FORCEWAKE_MEDIA_VDBOX2
= BIT(FW_DOMAIN_ID_MEDIA_VDBOX2
),
57 FORCEWAKE_MEDIA_VDBOX3
= BIT(FW_DOMAIN_ID_MEDIA_VDBOX3
),
58 FORCEWAKE_MEDIA_VEBOX0
= BIT(FW_DOMAIN_ID_MEDIA_VEBOX0
),
59 FORCEWAKE_MEDIA_VEBOX1
= BIT(FW_DOMAIN_ID_MEDIA_VEBOX1
),
61 FORCEWAKE_ALL
= BIT(FW_DOMAIN_ID_COUNT
) - 1
64 struct intel_uncore_funcs
{
65 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
66 enum forcewake_domains domains
);
67 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
68 enum forcewake_domains domains
);
70 u8 (*mmio_readb
)(struct drm_i915_private
*dev_priv
,
71 i915_reg_t r
, bool trace
);
72 u16 (*mmio_readw
)(struct drm_i915_private
*dev_priv
,
73 i915_reg_t r
, bool trace
);
74 u32 (*mmio_readl
)(struct drm_i915_private
*dev_priv
,
75 i915_reg_t r
, bool trace
);
76 u64 (*mmio_readq
)(struct drm_i915_private
*dev_priv
,
77 i915_reg_t r
, bool trace
);
79 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
,
80 i915_reg_t r
, u8 val
, bool trace
);
81 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
,
82 i915_reg_t r
, u16 val
, bool trace
);
83 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
,
84 i915_reg_t r
, u32 val
, bool trace
);
87 struct intel_forcewake_range
{
91 enum forcewake_domains domains
;
95 spinlock_t lock
; /** lock is also taken in irq contexts. */
97 const struct intel_forcewake_range
*fw_domains_table
;
98 unsigned int fw_domains_table_entries
;
100 struct notifier_block pmic_bus_access_nb
;
101 struct intel_uncore_funcs funcs
;
103 unsigned int fifo_count
;
105 enum forcewake_domains fw_domains
;
106 enum forcewake_domains fw_domains_active
;
107 enum forcewake_domains fw_domains_saved
; /* user domains saved for S3 */
113 struct intel_uncore_forcewake_domain
{
114 enum forcewake_domain_id id
;
115 enum forcewake_domains mask
;
116 unsigned int wake_count
;
118 struct hrtimer timer
;
121 } fw_domain
[FW_DOMAIN_ID_COUNT
];
126 int saved_mmio_check
;
127 int saved_mmio_debug
;
130 int unclaimed_mmio_check
;
133 /* Iterate over initialised fw domains */
134 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
135 for (tmp__ = (mask__); \
136 tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
138 #define for_each_fw_domain(domain__, dev_priv__, tmp__) \
139 for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
142 void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
143 void intel_uncore_init(struct drm_i915_private
*dev_priv
);
144 void intel_uncore_prune(struct drm_i915_private
*dev_priv
);
145 bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
146 bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
147 void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
148 void intel_uncore_suspend(struct drm_i915_private
*dev_priv
);
149 void intel_uncore_resume_early(struct drm_i915_private
*dev_priv
);
150 void intel_uncore_runtime_resume(struct drm_i915_private
*dev_priv
);
152 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
153 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
154 void assert_forcewakes_active(struct drm_i915_private
*dev_priv
,
155 enum forcewake_domains fw_domains
);
156 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
158 enum forcewake_domains
159 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
160 i915_reg_t reg
, unsigned int op
);
161 #define FW_REG_READ (1)
162 #define FW_REG_WRITE (2)
164 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
165 enum forcewake_domains domains
);
166 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
167 enum forcewake_domains domains
);
168 /* Like above but the caller must manage the uncore.lock itself.
169 * Must be used with I915_READ_FW and friends.
171 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
172 enum forcewake_domains domains
);
173 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
174 enum forcewake_domains domains
);
176 void intel_uncore_forcewake_user_get(struct drm_i915_private
*dev_priv
);
177 void intel_uncore_forcewake_user_put(struct drm_i915_private
*dev_priv
);
179 int __intel_wait_for_register(struct drm_i915_private
*dev_priv
,
183 unsigned int fast_timeout_us
,
184 unsigned int slow_timeout_ms
,
187 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
191 unsigned int timeout_ms
)
193 return __intel_wait_for_register(dev_priv
, reg
, mask
, value
, 2,
196 int __intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
200 unsigned int fast_timeout_us
,
201 unsigned int slow_timeout_ms
,
204 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
208 unsigned int timeout_ms
)
210 return __intel_wait_for_register_fw(dev_priv
, reg
, mask
, value
,
211 2, timeout_ms
, NULL
);
214 #define raw_reg_read(base, reg) \
215 readl(base + i915_mmio_reg_offset(reg))
216 #define raw_reg_write(base, reg, value) \
217 writel(value, base + i915_mmio_reg_offset(reg))
219 #endif /* !__INTEL_UNCORE_H__ */