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vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / vlv_dsi.c
blob435a2c35ee8c4acd46d9f3fccd3c6dc700ad8b8d
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <drm/drmP.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_mipi_dsi.h>
32 #include <linux/slab.h>
33 #include <linux/gpio/consumer.h>
34 #include "i915_drv.h"
35 #include "intel_drv.h"
36 #include "intel_dsi.h"
37
38 /* return pixels in terms of txbyteclkhs */
39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
40 u16 burst_mode_ratio)
41 {
42 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
43 8 * 100), lane_count);
44 }
45
46 /* return pixels equvalent to txbyteclkhs */
47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
48 u16 burst_mode_ratio)
49 {
50 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
51 (bpp * burst_mode_ratio));
52 }
53
54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
55 {
56 /* It just so happens the VBT matches register contents. */
57 switch (fmt) {
58 case VID_MODE_FORMAT_RGB888:
59 return MIPI_DSI_FMT_RGB888;
60 case VID_MODE_FORMAT_RGB666:
61 return MIPI_DSI_FMT_RGB666;
62 case VID_MODE_FORMAT_RGB666_PACKED:
63 return MIPI_DSI_FMT_RGB666_PACKED;
64 case VID_MODE_FORMAT_RGB565:
65 return MIPI_DSI_FMT_RGB565;
66 default:
67 MISSING_CASE(fmt);
68 return MIPI_DSI_FMT_RGB666;
69 }
70 }
71
72 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
73 {
74 struct drm_encoder *encoder = &intel_dsi->base.base;
75 struct drm_device *dev = encoder->dev;
76 struct drm_i915_private *dev_priv = to_i915(dev);
77 u32 mask;
78
79 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
80 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
81
82 if (intel_wait_for_register(dev_priv,
83 MIPI_GEN_FIFO_STAT(port), mask, mask,
84 100))
85 DRM_ERROR("DPI FIFOs are not empty\n");
86 }
87
88 static void write_data(struct drm_i915_private *dev_priv,
89 i915_reg_t reg,
90 const u8 *data, u32 len)
91 {
92 u32 i, j;
93
94 for (i = 0; i < len; i += 4) {
95 u32 val = 0;
96
97 for (j = 0; j < min_t(u32, len - i, 4); j++)
98 val |= *data++ << 8 * j;
99
100 I915_WRITE(reg, val);
101 }
102 }
103
104 static void read_data(struct drm_i915_private *dev_priv,
105 i915_reg_t reg,
106 u8 *data, u32 len)
107 {
108 u32 i, j;
109
110 for (i = 0; i < len; i += 4) {
111 u32 val = I915_READ(reg);
112
113 for (j = 0; j < min_t(u32, len - i, 4); j++)
114 *data++ = val >> 8 * j;
115 }
116 }
117
118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
119 const struct mipi_dsi_msg *msg)
120 {
121 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
122 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
123 struct drm_i915_private *dev_priv = to_i915(dev);
124 enum port port = intel_dsi_host->port;
125 struct mipi_dsi_packet packet;
126 ssize_t ret;
127 const u8 *header, *data;
128 i915_reg_t data_reg, ctrl_reg;
129 u32 data_mask, ctrl_mask;
130
131 ret = mipi_dsi_create_packet(&packet, msg);
132 if (ret < 0)
133 return ret;
134
135 header = packet.header;
136 data = packet.payload;
137
138 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
139 data_reg = MIPI_LP_GEN_DATA(port);
140 data_mask = LP_DATA_FIFO_FULL;
141 ctrl_reg = MIPI_LP_GEN_CTRL(port);
142 ctrl_mask = LP_CTRL_FIFO_FULL;
143 } else {
144 data_reg = MIPI_HS_GEN_DATA(port);
145 data_mask = HS_DATA_FIFO_FULL;
146 ctrl_reg = MIPI_HS_GEN_CTRL(port);
147 ctrl_mask = HS_CTRL_FIFO_FULL;
148 }
149
150 /* note: this is never true for reads */
151 if (packet.payload_length) {
152 if (intel_wait_for_register(dev_priv,
153 MIPI_GEN_FIFO_STAT(port),
154 data_mask, 0,
155 50))
156 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
157
158 write_data(dev_priv, data_reg, packet.payload,
159 packet.payload_length);
160 }
161
162 if (msg->rx_len) {
163 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
164 }
165
166 if (intel_wait_for_register(dev_priv,
167 MIPI_GEN_FIFO_STAT(port),
168 ctrl_mask, 0,
169 50)) {
170 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
171 }
172
173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
174
175 /* ->rx_len is set only for reads */
176 if (msg->rx_len) {
177 data_mask = GEN_READ_DATA_AVAIL;
178 if (intel_wait_for_register(dev_priv,
179 MIPI_INTR_STAT(port),
180 data_mask, data_mask,
181 50))
182 DRM_ERROR("Timeout waiting for read data.\n");
183
184 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
185 }
186
187 /* XXX: fix for reads and writes */
188 return 4 + packet.payload_length;
189 }
190
191 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
192 struct mipi_dsi_device *dsi)
193 {
194 return 0;
195 }
196
197 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
198 struct mipi_dsi_device *dsi)
199 {
200 return 0;
201 }
202
203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
204 .attach = intel_dsi_host_attach,
205 .detach = intel_dsi_host_detach,
206 .transfer = intel_dsi_host_transfer,
207 };
208
209 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
210 enum port port)
211 {
212 struct intel_dsi_host *host;
213 struct mipi_dsi_device *device;
214
215 host = kzalloc(sizeof(*host), GFP_KERNEL);
216 if (!host)
217 return NULL;
218
219 host->base.ops = &intel_dsi_host_ops;
220 host->intel_dsi = intel_dsi;
221 host->port = port;
222
223 /*
224 * We should call mipi_dsi_host_register(&host->base) here, but we don't
225 * have a host->dev, and we don't have OF stuff either. So just use the
226 * dsi framework as a library and hope for the best. Create the dsi
227 * devices by ourselves here too. Need to be careful though, because we
228 * don't initialize any of the driver model devices here.
229 */
230 device = kzalloc(sizeof(*device), GFP_KERNEL);
231 if (!device) {
232 kfree(host);
233 return NULL;
234 }
235
236 device->host = &host->base;
237 host->device = device;
238
239 return host;
240 }
241
242 /*
243 * send a video mode command
244 *
245 * XXX: commands with data in MIPI_DPI_DATA?
246 */
247 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
248 enum port port)
249 {
250 struct drm_encoder *encoder = &intel_dsi->base.base;
251 struct drm_device *dev = encoder->dev;
252 struct drm_i915_private *dev_priv = to_i915(dev);
253 u32 mask;
254
255 /* XXX: pipe, hs */
256 if (hs)
257 cmd &= ~DPI_LP_MODE;
258 else
259 cmd |= DPI_LP_MODE;
260
261 /* clear bit */
262 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
263
264 /* XXX: old code skips write if control unchanged */
265 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
266 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
267
268 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
269
270 mask = SPL_PKT_SENT_INTERRUPT;
271 if (intel_wait_for_register(dev_priv,
272 MIPI_INTR_STAT(port), mask, mask,
273 100))
274 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
275
276 return 0;
277 }
278
279 static void band_gap_reset(struct drm_i915_private *dev_priv)
280 {
281 mutex_lock(&dev_priv->sb_lock);
282
283 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
284 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
285 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
286 udelay(150);
287 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
288 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
289
290 mutex_unlock(&dev_priv->sb_lock);
291 }
292
293 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
294 {
295 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
296 }
297
298 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
299 {
300 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
301 }
302
303 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
304 struct intel_crtc_state *pipe_config,
305 struct drm_connector_state *conn_state)
306 {
307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
308 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
309 base);
310 struct intel_connector *intel_connector = intel_dsi->attached_connector;
311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
312 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
313 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
314 int ret;
315
316 DRM_DEBUG_KMS("\n");
317
318 if (fixed_mode) {
319 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
320
321 if (HAS_GMCH_DISPLAY(dev_priv))
322 intel_gmch_panel_fitting(crtc, pipe_config,
323 conn_state->scaling_mode);
324 else
325 intel_pch_panel_fitting(crtc, pipe_config,
326 conn_state->scaling_mode);
327 }
328
329 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
330 return false;
331
332 /* DSI uses short packets for sync events, so clear mode flags for DSI */
333 adjusted_mode->flags = 0;
334
335 if (IS_GEN9_LP(dev_priv)) {
336 /* Enable Frame time stamp based scanline reporting */
337 adjusted_mode->private_flags |=
338 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
339
340 /* Dual link goes to DSI transcoder A. */
341 if (intel_dsi->ports == BIT(PORT_C))
342 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
343 else
344 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
345
346 ret = bxt_dsi_pll_compute(encoder, pipe_config);
347 if (ret)
348 return false;
349 } else {
350 ret = vlv_dsi_pll_compute(encoder, pipe_config);
351 if (ret)
352 return false;
353 }
354
355 pipe_config->clock_set = true;
356
357 return true;
358 }
359
360 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
361 {
362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
364 enum port port;
365 u32 tmp;
366 bool cold_boot = false;
367
368 /* Set the MIPI mode
369 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
370 * Power ON MIPI IO first and then write into IO reset and LP wake bits
371 */
372 for_each_dsi_port(port, intel_dsi->ports) {
373 tmp = I915_READ(MIPI_CTRL(port));
374 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
375 }
376
377 /* Put the IO into reset */
378 tmp = I915_READ(MIPI_CTRL(PORT_A));
379 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
380 I915_WRITE(MIPI_CTRL(PORT_A), tmp);
381
382 /* Program LP Wake */
383 for_each_dsi_port(port, intel_dsi->ports) {
384 tmp = I915_READ(MIPI_CTRL(port));
385 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
386 tmp &= ~GLK_LP_WAKE;
387 else
388 tmp |= GLK_LP_WAKE;
389 I915_WRITE(MIPI_CTRL(port), tmp);
390 }
391
392 /* Wait for Pwr ACK */
393 for_each_dsi_port(port, intel_dsi->ports) {
394 if (intel_wait_for_register(dev_priv,
395 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
396 GLK_MIPIIO_PORT_POWERED, 20))
397 DRM_ERROR("MIPIO port is powergated\n");
398 }
399
400 /* Check for cold boot scenario */
401 for_each_dsi_port(port, intel_dsi->ports) {
402 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
403 DEVICE_READY);
404 }
405
406 return cold_boot;
407 }
408
409 static void glk_dsi_device_ready(struct intel_encoder *encoder)
410 {
411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
412 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
413 enum port port;
414 u32 val;
415
416 /* Wait for MIPI PHY status bit to set */
417 for_each_dsi_port(port, intel_dsi->ports) {
418 if (intel_wait_for_register(dev_priv,
419 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
420 GLK_PHY_STATUS_PORT_READY, 20))
421 DRM_ERROR("PHY is not ON\n");
422 }
423
424 /* Get IO out of reset */
425 val = I915_READ(MIPI_CTRL(PORT_A));
426 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
427
428 /* Get IO out of Low power state*/
429 for_each_dsi_port(port, intel_dsi->ports) {
430 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
431 val = I915_READ(MIPI_DEVICE_READY(port));
432 val &= ~ULPS_STATE_MASK;
433 val |= DEVICE_READY;
434 I915_WRITE(MIPI_DEVICE_READY(port), val);
435 usleep_range(10, 15);
436 } else {
437 /* Enter ULPS */
438 val = I915_READ(MIPI_DEVICE_READY(port));
439 val &= ~ULPS_STATE_MASK;
440 val |= (ULPS_STATE_ENTER | DEVICE_READY);
441 I915_WRITE(MIPI_DEVICE_READY(port), val);
442
443 /* Wait for ULPS active */
444 if (intel_wait_for_register(dev_priv,
445 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
446 DRM_ERROR("ULPS not active\n");
447
448 /* Exit ULPS */
449 val = I915_READ(MIPI_DEVICE_READY(port));
450 val &= ~ULPS_STATE_MASK;
451 val |= (ULPS_STATE_EXIT | DEVICE_READY);
452 I915_WRITE(MIPI_DEVICE_READY(port), val);
453
454 /* Enter Normal Mode */
455 val = I915_READ(MIPI_DEVICE_READY(port));
456 val &= ~ULPS_STATE_MASK;
457 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
458 I915_WRITE(MIPI_DEVICE_READY(port), val);
459
460 val = I915_READ(MIPI_CTRL(port));
461 val &= ~GLK_LP_WAKE;
462 I915_WRITE(MIPI_CTRL(port), val);
463 }
464 }
465
466 /* Wait for Stop state */
467 for_each_dsi_port(port, intel_dsi->ports) {
468 if (intel_wait_for_register(dev_priv,
469 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
470 GLK_DATA_LANE_STOP_STATE, 20))
471 DRM_ERROR("Date lane not in STOP state\n");
472 }
473
474 /* Wait for AFE LATCH */
475 for_each_dsi_port(port, intel_dsi->ports) {
476 if (intel_wait_for_register(dev_priv,
477 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
478 AFE_LATCHOUT, 20))
479 DRM_ERROR("D-PHY not entering LP-11 state\n");
480 }
481 }
482
483 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
484 {
485 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
486 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
487 enum port port;
488 u32 val;
489
490 DRM_DEBUG_KMS("\n");
491
492 /* Enable MIPI PHY transparent latch */
493 for_each_dsi_port(port, intel_dsi->ports) {
494 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
495 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
496 usleep_range(2000, 2500);
497 }
498
499 /* Clear ULPS and set device ready */
500 for_each_dsi_port(port, intel_dsi->ports) {
501 val = I915_READ(MIPI_DEVICE_READY(port));
502 val &= ~ULPS_STATE_MASK;
503 I915_WRITE(MIPI_DEVICE_READY(port), val);
504 usleep_range(2000, 2500);
505 val |= DEVICE_READY;
506 I915_WRITE(MIPI_DEVICE_READY(port), val);
507 }
508 }
509
510 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
511 {
512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
513 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
514 enum port port;
515 u32 val;
516
517 DRM_DEBUG_KMS("\n");
518
519 mutex_lock(&dev_priv->sb_lock);
520 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
521 * needed everytime after power gate */
522 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
523 mutex_unlock(&dev_priv->sb_lock);
524
525 /* bandgap reset is needed after everytime we do power gate */
526 band_gap_reset(dev_priv);
527
528 for_each_dsi_port(port, intel_dsi->ports) {
529
530 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
531 usleep_range(2500, 3000);
532
533 /* Enable MIPI PHY transparent latch
534 * Common bit for both MIPI Port A & MIPI Port C
535 * No similar bit in MIPI Port C reg
536 */
537 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
538 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
539 usleep_range(1000, 1500);
540
541 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
542 usleep_range(2500, 3000);
543
544 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
545 usleep_range(2500, 3000);
546 }
547 }
548
549 static void intel_dsi_device_ready(struct intel_encoder *encoder)
550 {
551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
552
553 if (IS_GEMINILAKE(dev_priv))
554 glk_dsi_device_ready(encoder);
555 else if (IS_GEN9_LP(dev_priv))
556 bxt_dsi_device_ready(encoder);
557 else
558 vlv_dsi_device_ready(encoder);
559 }
560
561 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
562 {
563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
564 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
565 enum port port;
566 u32 val;
567
568 /* Enter ULPS */
569 for_each_dsi_port(port, intel_dsi->ports) {
570 val = I915_READ(MIPI_DEVICE_READY(port));
571 val &= ~ULPS_STATE_MASK;
572 val |= (ULPS_STATE_ENTER | DEVICE_READY);
573 I915_WRITE(MIPI_DEVICE_READY(port), val);
574 }
575
576 /* Wait for MIPI PHY status bit to unset */
577 for_each_dsi_port(port, intel_dsi->ports) {
578 if (intel_wait_for_register(dev_priv,
579 MIPI_CTRL(port),
580 GLK_PHY_STATUS_PORT_READY, 0, 20))
581 DRM_ERROR("PHY is not turning OFF\n");
582 }
583
584 /* Wait for Pwr ACK bit to unset */
585 for_each_dsi_port(port, intel_dsi->ports) {
586 if (intel_wait_for_register(dev_priv,
587 MIPI_CTRL(port),
588 GLK_MIPIIO_PORT_POWERED, 0, 20))
589 DRM_ERROR("MIPI IO Port is not powergated\n");
590 }
591 }
592
593 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
594 {
595 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
596 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
597 enum port port;
598 u32 tmp;
599
600 /* Put the IO into reset */
601 tmp = I915_READ(MIPI_CTRL(PORT_A));
602 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
603 I915_WRITE(MIPI_CTRL(PORT_A), tmp);
604
605 /* Wait for MIPI PHY status bit to unset */
606 for_each_dsi_port(port, intel_dsi->ports) {
607 if (intel_wait_for_register(dev_priv,
608 MIPI_CTRL(port),
609 GLK_PHY_STATUS_PORT_READY, 0, 20))
610 DRM_ERROR("PHY is not turning OFF\n");
611 }
612
613 /* Clear MIPI mode */
614 for_each_dsi_port(port, intel_dsi->ports) {
615 tmp = I915_READ(MIPI_CTRL(port));
616 tmp &= ~GLK_MIPIIO_ENABLE;
617 I915_WRITE(MIPI_CTRL(port), tmp);
618 }
619 }
620
621 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
622 {
623 glk_dsi_enter_low_power_mode(encoder);
624 glk_dsi_disable_mipi_io(encoder);
625 }
626
627 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
628 {
629 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
630 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
631 enum port port;
632
633 DRM_DEBUG_KMS("\n");
634 for_each_dsi_port(port, intel_dsi->ports) {
635 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
636 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
637 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
638 u32 val;
639
640 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
641 ULPS_STATE_ENTER);
642 usleep_range(2000, 2500);
643
644 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
645 ULPS_STATE_EXIT);
646 usleep_range(2000, 2500);
647
648 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
649 ULPS_STATE_ENTER);
650 usleep_range(2000, 2500);
651
652 /*
653 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
654 * Port A only. MIPI Port C has no similar bit for checking.
655 */
656 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
657 intel_wait_for_register(dev_priv,
658 port_ctrl, AFE_LATCHOUT, 0,
659 30))
660 DRM_ERROR("DSI LP not going Low\n");
661
662 /* Disable MIPI PHY transparent latch */
663 val = I915_READ(port_ctrl);
664 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
665 usleep_range(1000, 1500);
666
667 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
668 usleep_range(2000, 2500);
669 }
670 }
671
672 static void intel_dsi_port_enable(struct intel_encoder *encoder,
673 const struct intel_crtc_state *crtc_state)
674 {
675 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
676 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
677 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
678 enum port port;
679
680 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
681 u32 temp;
682 if (IS_GEN9_LP(dev_priv)) {
683 for_each_dsi_port(port, intel_dsi->ports) {
684 temp = I915_READ(MIPI_CTRL(port));
685 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
686 intel_dsi->pixel_overlap <<
687 BXT_PIXEL_OVERLAP_CNT_SHIFT;
688 I915_WRITE(MIPI_CTRL(port), temp);
689 }
690 } else {
691 temp = I915_READ(VLV_CHICKEN_3);
692 temp &= ~PIXEL_OVERLAP_CNT_MASK |
693 intel_dsi->pixel_overlap <<
694 PIXEL_OVERLAP_CNT_SHIFT;
695 I915_WRITE(VLV_CHICKEN_3, temp);
696 }
697 }
698
699 for_each_dsi_port(port, intel_dsi->ports) {
700 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
701 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
702 u32 temp;
703
704 temp = I915_READ(port_ctrl);
705
706 temp &= ~LANE_CONFIGURATION_MASK;
707 temp &= ~DUAL_LINK_MODE_MASK;
708
709 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
710 temp |= (intel_dsi->dual_link - 1)
711 << DUAL_LINK_MODE_SHIFT;
712 if (IS_BROXTON(dev_priv))
713 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
714 else
715 temp |= crtc->pipe ?
716 LANE_CONFIGURATION_DUAL_LINK_B :
717 LANE_CONFIGURATION_DUAL_LINK_A;
718 }
719 /* assert ip_tg_enable signal */
720 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
721 POSTING_READ(port_ctrl);
722 }
723 }
724
725 static void intel_dsi_port_disable(struct intel_encoder *encoder)
726 {
727 struct drm_device *dev = encoder->base.dev;
728 struct drm_i915_private *dev_priv = to_i915(dev);
729 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
730 enum port port;
731
732 for_each_dsi_port(port, intel_dsi->ports) {
733 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
734 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
735 u32 temp;
736
737 /* de-assert ip_tg_enable signal */
738 temp = I915_READ(port_ctrl);
739 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
740 POSTING_READ(port_ctrl);
741 }
742 }
743
744 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
745 const struct intel_crtc_state *pipe_config);
746 static void intel_dsi_unprepare(struct intel_encoder *encoder);
747
748 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
749 {
750 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
751
752 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
753 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
754 return;
755
756 msleep(msec);
757 }
758
759 /*
760 * Panel enable/disable sequences from the VBT spec.
761 *
762 * Note the spec has AssertReset / DeassertReset swapped from their
763 * usual naming. We use the normal names to avoid confusion (so below
764 * they are swapped compared to the spec).
765 *
766 * Steps starting with MIPI refer to VBT sequences, note that for v2
767 * VBTs several steps which have a VBT in v2 are expected to be handled
768 * directly by the driver, by directly driving gpios for example.
769 *
770 * v2 video mode seq v3 video mode seq command mode seq
771 * - power on - MIPIPanelPowerOn - power on
772 * - wait t1+t2 - wait t1+t2
773 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
774 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
775 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
776 * - MIPITearOn
777 * - MIPIDisplayOn
778 * - turn on DPI - turn on DPI - set pipe to dsr mode
779 * - MIPIDisplayOn - MIPIDisplayOn
780 * - wait t5 - wait t5
781 * - backlight on - MIPIBacklightOn - backlight on
782 * ... ... ... issue mem cmds ...
783 * - backlight off - MIPIBacklightOff - backlight off
784 * - wait t6 - wait t6
785 * - MIPIDisplayOff
786 * - turn off DPI - turn off DPI - disable pipe dsr mode
787 * - MIPITearOff
788 * - MIPIDisplayOff - MIPIDisplayOff
789 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
790 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
791 * - wait t3 - wait t3
792 * - power off - MIPIPanelPowerOff - power off
793 * - wait t4 - wait t4
794 */
795
796 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
797 const struct intel_crtc_state *pipe_config,
798 const struct drm_connector_state *conn_state)
799 {
800 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
801 struct drm_crtc *crtc = pipe_config->base.crtc;
802 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
804 int pipe = intel_crtc->pipe;
805 enum port port;
806 u32 val;
807 bool glk_cold_boot = false;
808
809 DRM_DEBUG_KMS("\n");
810
811 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
812
813 /*
814 * The BIOS may leave the PLL in a wonky state where it doesn't
815 * lock. It needs to be fully powered down to fix it.
816 */
817 if (IS_GEN9_LP(dev_priv)) {
818 bxt_dsi_pll_disable(encoder);
819 bxt_dsi_pll_enable(encoder, pipe_config);
820 } else {
821 vlv_dsi_pll_disable(encoder);
822 vlv_dsi_pll_enable(encoder, pipe_config);
823 }
824
825 if (IS_BROXTON(dev_priv)) {
826 /* Add MIPI IO reset programming for modeset */
827 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
828 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
829 val | MIPIO_RST_CTRL);
830
831 /* Power up DSI regulator */
832 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
833 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
834 }
835
836 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
837 u32 val;
838
839 /* Disable DPOunit clock gating, can stall pipe */
840 val = I915_READ(DSPCLK_GATE_D);
841 val |= DPOUNIT_CLOCK_GATE_DISABLE;
842 I915_WRITE(DSPCLK_GATE_D, val);
843 }
844
845 if (!IS_GEMINILAKE(dev_priv))
846 intel_dsi_prepare(encoder, pipe_config);
847
848 /* Power on, try both CRC pmic gpio and VBT */
849 if (intel_dsi->gpio_panel)
850 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
851 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
852 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
853
854 /* Deassert reset */
855 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
856
857 if (IS_GEMINILAKE(dev_priv)) {
858 glk_cold_boot = glk_dsi_enable_io(encoder);
859
860 /* Prepare port in cold boot(s3/s4) scenario */
861 if (glk_cold_boot)
862 intel_dsi_prepare(encoder, pipe_config);
863 }
864
865 /* Put device in ready state (LP-11) */
866 intel_dsi_device_ready(encoder);
867
868 /* Prepare port in normal boot scenario */
869 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
870 intel_dsi_prepare(encoder, pipe_config);
871
872 /* Send initialization commands in LP mode */
873 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
874
875 /* Enable port in pre-enable phase itself because as per hw team
876 * recommendation, port should be enabled befor plane & pipe */
877 if (is_cmd_mode(intel_dsi)) {
878 for_each_dsi_port(port, intel_dsi->ports)
879 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
880 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
881 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
882 } else {
883 msleep(20); /* XXX */
884 for_each_dsi_port(port, intel_dsi->ports)
885 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
886 intel_dsi_msleep(intel_dsi, 100);
887
888 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
889
890 intel_dsi_port_enable(encoder, pipe_config);
891 }
892
893 intel_panel_enable_backlight(pipe_config, conn_state);
894 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
895 }
896
897 /*
898 * DSI port enable has to be done before pipe and plane enable, so we do it in
899 * the pre_enable hook.
900 */
901 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
902 const struct intel_crtc_state *pipe_config,
903 const struct drm_connector_state *conn_state)
904 {
905 DRM_DEBUG_KMS("\n");
906 }
907
908 /*
909 * DSI port disable has to be done after pipe and plane disable, so we do it in
910 * the post_disable hook.
911 */
912 static void intel_dsi_disable(struct intel_encoder *encoder,
913 const struct intel_crtc_state *old_crtc_state,
914 const struct drm_connector_state *old_conn_state)
915 {
916 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
917 enum port port;
918
919 DRM_DEBUG_KMS("\n");
920
921 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
922 intel_panel_disable_backlight(old_conn_state);
923
924 /*
925 * According to the spec we should send SHUTDOWN before
926 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
927 * has shown that the v3 sequence works for v2 VBTs too
928 */
929 if (is_vid_mode(intel_dsi)) {
930 /* Send Shutdown command to the panel in LP mode */
931 for_each_dsi_port(port, intel_dsi->ports)
932 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
933 msleep(10);
934 }
935 }
936
937 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
938 {
939 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
940
941 if (IS_GEMINILAKE(dev_priv))
942 glk_dsi_clear_device_ready(encoder);
943 else
944 vlv_dsi_clear_device_ready(encoder);
945 }
946
947 static void intel_dsi_post_disable(struct intel_encoder *encoder,
948 const struct intel_crtc_state *pipe_config,
949 const struct drm_connector_state *conn_state)
950 {
951 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
952 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
953 enum port port;
954 u32 val;
955
956 DRM_DEBUG_KMS("\n");
957
958 if (is_vid_mode(intel_dsi)) {
959 for_each_dsi_port(port, intel_dsi->ports)
960 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
961
962 intel_dsi_port_disable(encoder);
963 usleep_range(2000, 5000);
964 }
965
966 intel_dsi_unprepare(encoder);
967
968 /*
969 * if disable packets are sent before sending shutdown packet then in
970 * some next enable sequence send turn on packet error is observed
971 */
972 if (is_cmd_mode(intel_dsi))
973 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
974 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
975
976 /* Transition to LP-00 */
977 intel_dsi_clear_device_ready(encoder);
978
979 if (IS_BROXTON(dev_priv)) {
980 /* Power down DSI regulator to save power */
981 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
982 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
983
984 /* Add MIPI IO reset programming for modeset */
985 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
986 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
987 val & ~MIPIO_RST_CTRL);
988 }
989
990 if (IS_GEN9_LP(dev_priv)) {
991 bxt_dsi_pll_disable(encoder);
992 } else {
993 u32 val;
994
995 vlv_dsi_pll_disable(encoder);
996
997 val = I915_READ(DSPCLK_GATE_D);
998 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
999 I915_WRITE(DSPCLK_GATE_D, val);
1000 }
1001
1002 /* Assert reset */
1003 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1004
1005 /* Power off, try both CRC pmic gpio and VBT */
1006 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
1007 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1008 if (intel_dsi->gpio_panel)
1009 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
1010
1011 /*
1012 * FIXME As we do with eDP, just make a note of the time here
1013 * and perform the wait before the next panel power on.
1014 */
1015 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
1016 }
1017
1018 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1019 enum pipe *pipe)
1020 {
1021 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1022 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1023 enum port port;
1024 bool active = false;
1025
1026 DRM_DEBUG_KMS("\n");
1027
1028 if (!intel_display_power_get_if_enabled(dev_priv,
1029 encoder->power_domain))
1030 return false;
1031
1032 /*
1033 * On Broxton the PLL needs to be enabled with a valid divider
1034 * configuration, otherwise accessing DSI registers will hang the
1035 * machine. See BSpec North Display Engine registers/MIPI[BXT].
1036 */
1037 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
1038 goto out_put_power;
1039
1040 /* XXX: this only works for one DSI output */
1041 for_each_dsi_port(port, intel_dsi->ports) {
1042 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
1043 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1044 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
1045
1046 /*
1047 * Due to some hardware limitations on VLV/CHV, the DPI enable
1048 * bit in port C control register does not get set. As a
1049 * workaround, check pipe B conf instead.
1050 */
1051 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1052 port == PORT_C)
1053 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1054
1055 /* Try command mode if video mode not enabled */
1056 if (!enabled) {
1057 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1058 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1059 }
1060
1061 if (!enabled)
1062 continue;
1063
1064 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1065 continue;
1066
1067 if (IS_GEN9_LP(dev_priv)) {
1068 u32 tmp = I915_READ(MIPI_CTRL(port));
1069 tmp &= BXT_PIPE_SELECT_MASK;
1070 tmp >>= BXT_PIPE_SELECT_SHIFT;
1071
1072 if (WARN_ON(tmp > PIPE_C))
1073 continue;
1074
1075 *pipe = tmp;
1076 } else {
1077 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1078 }
1079
1080 active = true;
1081 break;
1082 }
1083
1084 out_put_power:
1085 intel_display_power_put(dev_priv, encoder->power_domain);
1086
1087 return active;
1088 }
1089
1090 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1091 struct intel_crtc_state *pipe_config)
1092 {
1093 struct drm_device *dev = encoder->base.dev;
1094 struct drm_i915_private *dev_priv = to_i915(dev);
1095 struct drm_display_mode *adjusted_mode =
1096 &pipe_config->base.adjusted_mode;
1097 struct drm_display_mode *adjusted_mode_sw;
1098 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1099 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1100 unsigned int lane_count = intel_dsi->lane_count;
1101 unsigned int bpp, fmt;
1102 enum port port;
1103 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1104 u16 hfp_sw, hsync_sw, hbp_sw;
1105 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1106 crtc_hblank_start_sw, crtc_hblank_end_sw;
1107
1108 /* FIXME: hw readout should not depend on SW state */
1109 adjusted_mode_sw = &crtc->config->base.adjusted_mode;
1110
1111 /*
1112 * Atleast one port is active as encoder->get_config called only if
1113 * encoder->get_hw_state() returns true.
1114 */
1115 for_each_dsi_port(port, intel_dsi->ports) {
1116 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1117 break;
1118 }
1119
1120 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1121 pipe_config->pipe_bpp =
1122 mipi_dsi_pixel_format_to_bpp(
1123 pixel_format_from_register_bits(fmt));
1124 bpp = pipe_config->pipe_bpp;
1125
1126 /* Enable Frame time stamo based scanline reporting */
1127 adjusted_mode->private_flags |=
1128 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1129
1130 /* In terms of pixels */
1131 adjusted_mode->crtc_hdisplay =
1132 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1133 adjusted_mode->crtc_vdisplay =
1134 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1135 adjusted_mode->crtc_vtotal =
1136 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1137
1138 hactive = adjusted_mode->crtc_hdisplay;
1139 hfp = I915_READ(MIPI_HFP_COUNT(port));
1140
1141 /*
1142 * Meaningful for video mode non-burst sync pulse mode only,
1143 * can be zero for non-burst sync events and burst modes
1144 */
1145 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1146 hbp = I915_READ(MIPI_HBP_COUNT(port));
1147
1148 /* harizontal values are in terms of high speed byte clock */
1149 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1150 intel_dsi->burst_mode_ratio);
1151 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1152 intel_dsi->burst_mode_ratio);
1153 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1154 intel_dsi->burst_mode_ratio);
1155
1156 if (intel_dsi->dual_link) {
1157 hfp *= 2;
1158 hsync *= 2;
1159 hbp *= 2;
1160 }
1161
1162 /* vertical values are in terms of lines */
1163 vfp = I915_READ(MIPI_VFP_COUNT(port));
1164 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1165 vbp = I915_READ(MIPI_VBP_COUNT(port));
1166
1167 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1168 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1169 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1170 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1171 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1172
1173 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1174 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1175 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1176 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1177
1178 /*
1179 * In BXT DSI there is no regs programmed with few horizontal timings
1180 * in Pixels but txbyteclkhs.. So retrieval process adds some
1181 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1182 * Actually here for the given adjusted_mode, we are calculating the
1183 * value programmed to the port and then back to the horizontal timing
1184 * param in pixels. This is the expected value, including roundup errors
1185 * And if that is same as retrieved value from port, then
1186 * (HW state) adjusted_mode's horizontal timings are corrected to
1187 * match with SW state to nullify the errors.
1188 */
1189 /* Calculating the value programmed to the Port register */
1190 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1191 adjusted_mode_sw->crtc_hdisplay;
1192 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1193 adjusted_mode_sw->crtc_hsync_start;
1194 hbp_sw = adjusted_mode_sw->crtc_htotal -
1195 adjusted_mode_sw->crtc_hsync_end;
1196
1197 if (intel_dsi->dual_link) {
1198 hfp_sw /= 2;
1199 hsync_sw /= 2;
1200 hbp_sw /= 2;
1201 }
1202
1203 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1204 intel_dsi->burst_mode_ratio);
1205 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1206 intel_dsi->burst_mode_ratio);
1207 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1208 intel_dsi->burst_mode_ratio);
1209
1210 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1211 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1212 intel_dsi->burst_mode_ratio);
1213 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1214 intel_dsi->burst_mode_ratio);
1215 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1216 intel_dsi->burst_mode_ratio);
1217
1218 if (intel_dsi->dual_link) {
1219 hfp_sw *= 2;
1220 hsync_sw *= 2;
1221 hbp_sw *= 2;
1222 }
1223
1224 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1225 hsync_sw + hbp_sw;
1226 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1227 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1228 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1229 crtc_hblank_end_sw = crtc_htotal_sw;
1230
1231 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1232 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1233
1234 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1235 adjusted_mode->crtc_hsync_start =
1236 adjusted_mode_sw->crtc_hsync_start;
1237
1238 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1239 adjusted_mode->crtc_hsync_end =
1240 adjusted_mode_sw->crtc_hsync_end;
1241
1242 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1243 adjusted_mode->crtc_hblank_start =
1244 adjusted_mode_sw->crtc_hblank_start;
1245
1246 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1247 adjusted_mode->crtc_hblank_end =
1248 adjusted_mode_sw->crtc_hblank_end;
1249 }
1250
1251 static void intel_dsi_get_config(struct intel_encoder *encoder,
1252 struct intel_crtc_state *pipe_config)
1253 {
1254 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1255 u32 pclk;
1256 DRM_DEBUG_KMS("\n");
1257
1258 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1259
1260 if (IS_GEN9_LP(dev_priv)) {
1261 bxt_dsi_get_pipe_config(encoder, pipe_config);
1262 pclk = bxt_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1263 pipe_config);
1264 } else {
1265 pclk = vlv_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1266 pipe_config);
1267 }
1268
1269 if (pclk) {
1270 pipe_config->base.adjusted_mode.crtc_clock = pclk;
1271 pipe_config->port_clock = pclk;
1272 }
1273 }
1274
1275 static enum drm_mode_status
1276 intel_dsi_mode_valid(struct drm_connector *connector,
1277 struct drm_display_mode *mode)
1278 {
1279 struct intel_connector *intel_connector = to_intel_connector(connector);
1280 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1281 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1282
1283 DRM_DEBUG_KMS("\n");
1284
1285 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1286 return MODE_NO_DBLESCAN;
1287
1288 if (fixed_mode) {
1289 if (mode->hdisplay > fixed_mode->hdisplay)
1290 return MODE_PANEL;
1291 if (mode->vdisplay > fixed_mode->vdisplay)
1292 return MODE_PANEL;
1293 if (fixed_mode->clock > max_dotclk)
1294 return MODE_CLOCK_HIGH;
1295 }
1296
1297 return MODE_OK;
1298 }
1299
1300 /* return txclkesc cycles in terms of divider and duration in us */
1301 static u16 txclkesc(u32 divider, unsigned int us)
1302 {
1303 switch (divider) {
1304 case ESCAPE_CLOCK_DIVIDER_1:
1305 default:
1306 return 20 * us;
1307 case ESCAPE_CLOCK_DIVIDER_2:
1308 return 10 * us;
1309 case ESCAPE_CLOCK_DIVIDER_4:
1310 return 5 * us;
1311 }
1312 }
1313
1314 static void set_dsi_timings(struct drm_encoder *encoder,
1315 const struct drm_display_mode *adjusted_mode)
1316 {
1317 struct drm_device *dev = encoder->dev;
1318 struct drm_i915_private *dev_priv = to_i915(dev);
1319 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1320 enum port port;
1321 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1322 unsigned int lane_count = intel_dsi->lane_count;
1323
1324 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1325
1326 hactive = adjusted_mode->crtc_hdisplay;
1327 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1328 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1329 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1330
1331 if (intel_dsi->dual_link) {
1332 hactive /= 2;
1333 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1334 hactive += intel_dsi->pixel_overlap;
1335 hfp /= 2;
1336 hsync /= 2;
1337 hbp /= 2;
1338 }
1339
1340 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1341 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1342 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1343
1344 /* horizontal values are in terms of high speed byte clock */
1345 hactive = txbyteclkhs(hactive, bpp, lane_count,
1346 intel_dsi->burst_mode_ratio);
1347 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1348 hsync = txbyteclkhs(hsync, bpp, lane_count,
1349 intel_dsi->burst_mode_ratio);
1350 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1351
1352 for_each_dsi_port(port, intel_dsi->ports) {
1353 if (IS_GEN9_LP(dev_priv)) {
1354 /*
1355 * Program hdisplay and vdisplay on MIPI transcoder.
1356 * This is different from calculated hactive and
1357 * vactive, as they are calculated per channel basis,
1358 * whereas these values should be based on resolution.
1359 */
1360 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1361 adjusted_mode->crtc_hdisplay);
1362 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1363 adjusted_mode->crtc_vdisplay);
1364 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1365 adjusted_mode->crtc_vtotal);
1366 }
1367
1368 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1369 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1370
1371 /* meaningful for video mode non-burst sync pulse mode only,
1372 * can be zero for non-burst sync events and burst modes */
1373 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1374 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1375
1376 /* vertical values are in terms of lines */
1377 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1378 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1379 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1380 }
1381 }
1382
1383 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1384 {
1385 switch (fmt) {
1386 case MIPI_DSI_FMT_RGB888:
1387 return VID_MODE_FORMAT_RGB888;
1388 case MIPI_DSI_FMT_RGB666:
1389 return VID_MODE_FORMAT_RGB666;
1390 case MIPI_DSI_FMT_RGB666_PACKED:
1391 return VID_MODE_FORMAT_RGB666_PACKED;
1392 case MIPI_DSI_FMT_RGB565:
1393 return VID_MODE_FORMAT_RGB565;
1394 default:
1395 MISSING_CASE(fmt);
1396 return VID_MODE_FORMAT_RGB666;
1397 }
1398 }
1399
1400 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1401 const struct intel_crtc_state *pipe_config)
1402 {
1403 struct drm_encoder *encoder = &intel_encoder->base;
1404 struct drm_device *dev = encoder->dev;
1405 struct drm_i915_private *dev_priv = to_i915(dev);
1406 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1407 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1408 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1409 enum port port;
1410 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1411 u32 val, tmp;
1412 u16 mode_hdisplay;
1413
1414 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1415
1416 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1417
1418 if (intel_dsi->dual_link) {
1419 mode_hdisplay /= 2;
1420 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1421 mode_hdisplay += intel_dsi->pixel_overlap;
1422 }
1423
1424 for_each_dsi_port(port, intel_dsi->ports) {
1425 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1426 /*
1427 * escape clock divider, 20MHz, shared for A and C.
1428 * device ready must be off when doing this! txclkesc?
1429 */
1430 tmp = I915_READ(MIPI_CTRL(PORT_A));
1431 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1432 I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1433 ESCAPE_CLOCK_DIVIDER_1);
1434
1435 /* read request priority is per pipe */
1436 tmp = I915_READ(MIPI_CTRL(port));
1437 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1438 I915_WRITE(MIPI_CTRL(port), tmp |
1439 READ_REQUEST_PRIORITY_HIGH);
1440 } else if (IS_GEN9_LP(dev_priv)) {
1441 enum pipe pipe = intel_crtc->pipe;
1442
1443 tmp = I915_READ(MIPI_CTRL(port));
1444 tmp &= ~BXT_PIPE_SELECT_MASK;
1445
1446 tmp |= BXT_PIPE_SELECT(pipe);
1447 I915_WRITE(MIPI_CTRL(port), tmp);
1448 }
1449
1450 /* XXX: why here, why like this? handling in irq handler?! */
1451 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1452 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1453
1454 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1455
1456 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1457 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1458 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1459 }
1460
1461 set_dsi_timings(encoder, adjusted_mode);
1462
1463 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1464 if (is_cmd_mode(intel_dsi)) {
1465 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1466 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1467 } else {
1468 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1469 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1470 }
1471
1472 tmp = 0;
1473 if (intel_dsi->eotp_pkt == 0)
1474 tmp |= EOT_DISABLE;
1475 if (intel_dsi->clock_stop)
1476 tmp |= CLOCKSTOP;
1477
1478 if (IS_GEN9_LP(dev_priv)) {
1479 tmp |= BXT_DPHY_DEFEATURE_EN;
1480 if (!is_cmd_mode(intel_dsi))
1481 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1482 }
1483
1484 for_each_dsi_port(port, intel_dsi->ports) {
1485 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1486
1487 /* timeouts for recovery. one frame IIUC. if counter expires,
1488 * EOT and stop state. */
1489
1490 /*
1491 * In burst mode, value greater than one DPI line Time in byte
1492 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1493 * said value is recommended.
1494 *
1495 * In non-burst mode, Value greater than one DPI frame time in
1496 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1497 * said value is recommended.
1498 *
1499 * In DBI only mode, value greater than one DBI frame time in
1500 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1501 * said value is recommended.
1502 */
1503
1504 if (is_vid_mode(intel_dsi) &&
1505 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1506 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1507 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1508 intel_dsi->lane_count,
1509 intel_dsi->burst_mode_ratio) + 1);
1510 } else {
1511 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1512 txbyteclkhs(adjusted_mode->crtc_vtotal *
1513 adjusted_mode->crtc_htotal,
1514 bpp, intel_dsi->lane_count,
1515 intel_dsi->burst_mode_ratio) + 1);
1516 }
1517 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1518 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1519 intel_dsi->turn_arnd_val);
1520 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1521 intel_dsi->rst_timer_val);
1522
1523 /* dphy stuff */
1524
1525 /* in terms of low power clock */
1526 I915_WRITE(MIPI_INIT_COUNT(port),
1527 txclkesc(intel_dsi->escape_clk_div, 100));
1528
1529 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1530 /*
1531 * BXT spec says write MIPI_INIT_COUNT for
1532 * both the ports, even if only one is
1533 * getting used. So write the other port
1534 * if not in dual link mode.
1535 */
1536 I915_WRITE(MIPI_INIT_COUNT(port ==
1537 PORT_A ? PORT_C : PORT_A),
1538 intel_dsi->init_count);
1539 }
1540
1541 /* recovery disables */
1542 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1543
1544 /* in terms of low power clock */
1545 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1546
1547 /* in terms of txbyteclkhs. actual high to low switch +
1548 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1549 *
1550 * XXX: write MIPI_STOP_STATE_STALL?
1551 */
1552 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1553 intel_dsi->hs_to_lp_count);
1554
1555 /* XXX: low power clock equivalence in terms of byte clock.
1556 * the number of byte clocks occupied in one low power clock.
1557 * based on txbyteclkhs and txclkesc.
1558 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1559 * ) / 105.???
1560 */
1561 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1562
1563 if (IS_GEMINILAKE(dev_priv)) {
1564 I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1565 intel_dsi->lp_byte_clk);
1566 /* Shadow of DPHY reg */
1567 I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1568 intel_dsi->dphy_reg);
1569 }
1570
1571 /* the bw essential for transmitting 16 long packets containing
1572 * 252 bytes meant for dcs write memory command is programmed in
1573 * this register in terms of byte clocks. based on dsi transfer
1574 * rate and the number of lanes configured the time taken to
1575 * transmit 16 long packets in a dsi stream varies. */
1576 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1577
1578 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1579 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1580 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1581
1582 if (is_vid_mode(intel_dsi))
1583 /* Some panels might have resolution which is not a
1584 * multiple of 64 like 1366 x 768. Enable RANDOM
1585 * resolution support for such panels by default */
1586 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1587 intel_dsi->video_frmt_cfg_bits |
1588 intel_dsi->video_mode_format |
1589 IP_TG_CONFIG |
1590 RANDOM_DPI_DISPLAY_RESOLUTION);
1591 }
1592 }
1593
1594 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1595 {
1596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1597 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1598 enum port port;
1599 u32 val;
1600
1601 if (IS_GEMINILAKE(dev_priv))
1602 return;
1603
1604 for_each_dsi_port(port, intel_dsi->ports) {
1605 /* Panel commands can be sent when clock is in LP11 */
1606 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1607
1608 if (IS_GEN9_LP(dev_priv))
1609 bxt_dsi_reset_clocks(encoder, port);
1610 else
1611 vlv_dsi_reset_clocks(encoder, port);
1612 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1613
1614 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1615 val &= ~VID_MODE_FORMAT_MASK;
1616 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1617
1618 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1619 }
1620 }
1621
1622 static int intel_dsi_get_modes(struct drm_connector *connector)
1623 {
1624 struct intel_connector *intel_connector = to_intel_connector(connector);
1625 struct drm_display_mode *mode;
1626
1627 DRM_DEBUG_KMS("\n");
1628
1629 if (!intel_connector->panel.fixed_mode) {
1630 DRM_DEBUG_KMS("no fixed mode\n");
1631 return 0;
1632 }
1633
1634 mode = drm_mode_duplicate(connector->dev,
1635 intel_connector->panel.fixed_mode);
1636 if (!mode) {
1637 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1638 return 0;
1639 }
1640
1641 drm_mode_probed_add(connector, mode);
1642 return 1;
1643 }
1644
1645 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1646 {
1647 struct intel_connector *intel_connector = to_intel_connector(connector);
1648
1649 DRM_DEBUG_KMS("\n");
1650 intel_panel_fini(&intel_connector->panel);
1651 drm_connector_cleanup(connector);
1652 kfree(connector);
1653 }
1654
1655 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1656 {
1657 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1658
1659 /* dispose of the gpios */
1660 if (intel_dsi->gpio_panel)
1661 gpiod_put(intel_dsi->gpio_panel);
1662
1663 intel_encoder_destroy(encoder);
1664 }
1665
1666 static const struct drm_encoder_funcs intel_dsi_funcs = {
1667 .destroy = intel_dsi_encoder_destroy,
1668 };
1669
1670 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1671 .get_modes = intel_dsi_get_modes,
1672 .mode_valid = intel_dsi_mode_valid,
1673 .atomic_check = intel_digital_connector_atomic_check,
1674 };
1675
1676 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1677 .late_register = intel_connector_register,
1678 .early_unregister = intel_connector_unregister,
1679 .destroy = intel_dsi_connector_destroy,
1680 .fill_modes = drm_helper_probe_single_connector_modes,
1681 .atomic_get_property = intel_digital_connector_atomic_get_property,
1682 .atomic_set_property = intel_digital_connector_atomic_set_property,
1683 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1684 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1685 };
1686
1687 static int intel_dsi_get_panel_orientation(struct intel_connector *connector)
1688 {
1689 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1690 int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1691 enum i9xx_plane_id i9xx_plane;
1692 u32 val;
1693
1694 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1695 if (connector->encoder->crtc_mask == BIT(PIPE_B))
1696 i9xx_plane = PLANE_B;
1697 else
1698 i9xx_plane = PLANE_A;
1699
1700 val = I915_READ(DSPCNTR(i9xx_plane));
1701 if (val & DISPPLANE_ROTATE_180)
1702 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1703 }
1704
1705 return orientation;
1706 }
1707
1708 static void intel_dsi_add_properties(struct intel_connector *connector)
1709 {
1710 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1711
1712 if (connector->panel.fixed_mode) {
1713 u32 allowed_scalers;
1714
1715 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1716 if (!HAS_GMCH_DISPLAY(dev_priv))
1717 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1718
1719 drm_connector_attach_scaling_mode_property(&connector->base,
1720 allowed_scalers);
1721
1722 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1723
1724 connector->base.display_info.panel_orientation =
1725 intel_dsi_get_panel_orientation(connector);
1726 drm_connector_init_panel_orientation_property(
1727 &connector->base,
1728 connector->panel.fixed_mode->hdisplay,
1729 connector->panel.fixed_mode->vdisplay);
1730 }
1731 }
1732
1733 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1734 {
1735 struct drm_device *dev = &dev_priv->drm;
1736 struct intel_dsi *intel_dsi;
1737 struct intel_encoder *intel_encoder;
1738 struct drm_encoder *encoder;
1739 struct intel_connector *intel_connector;
1740 struct drm_connector *connector;
1741 struct drm_display_mode *scan, *fixed_mode = NULL;
1742 enum port port;
1743
1744 DRM_DEBUG_KMS("\n");
1745
1746 /* There is no detection method for MIPI so rely on VBT */
1747 if (!intel_bios_is_dsi_present(dev_priv, &port))
1748 return;
1749
1750 if (IS_GEN9_LP(dev_priv))
1751 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1752 else
1753 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1754
1755 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1756 if (!intel_dsi)
1757 return;
1758
1759 intel_connector = intel_connector_alloc();
1760 if (!intel_connector) {
1761 kfree(intel_dsi);
1762 return;
1763 }
1764
1765 intel_encoder = &intel_dsi->base;
1766 encoder = &intel_encoder->base;
1767 intel_dsi->attached_connector = intel_connector;
1768
1769 connector = &intel_connector->base;
1770
1771 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1772 "DSI %c", port_name(port));
1773
1774 intel_encoder->compute_config = intel_dsi_compute_config;
1775 intel_encoder->pre_enable = intel_dsi_pre_enable;
1776 intel_encoder->enable = intel_dsi_enable_nop;
1777 intel_encoder->disable = intel_dsi_disable;
1778 intel_encoder->post_disable = intel_dsi_post_disable;
1779 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1780 intel_encoder->get_config = intel_dsi_get_config;
1781
1782 intel_connector->get_hw_state = intel_connector_get_hw_state;
1783
1784 intel_encoder->port = port;
1785
1786 /*
1787 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1788 * port C. BXT isn't limited like this.
1789 */
1790 if (IS_GEN9_LP(dev_priv))
1791 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1792 else if (port == PORT_A)
1793 intel_encoder->crtc_mask = BIT(PIPE_A);
1794 else
1795 intel_encoder->crtc_mask = BIT(PIPE_B);
1796
1797 if (dev_priv->vbt.dsi.config->dual_link)
1798 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1799 else
1800 intel_dsi->ports = BIT(port);
1801
1802 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1803 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1804
1805 /* Create a DSI host (and a device) for each port. */
1806 for_each_dsi_port(port, intel_dsi->ports) {
1807 struct intel_dsi_host *host;
1808
1809 host = intel_dsi_host_init(intel_dsi, port);
1810 if (!host)
1811 goto err;
1812
1813 intel_dsi->dsi_hosts[port] = host;
1814 }
1815
1816 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1817 DRM_DEBUG_KMS("no device found\n");
1818 goto err;
1819 }
1820
1821 /*
1822 * In case of BYT with CRC PMIC, we need to use GPIO for
1823 * Panel control.
1824 */
1825 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1826 (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1827 intel_dsi->gpio_panel =
1828 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1829
1830 if (IS_ERR(intel_dsi->gpio_panel)) {
1831 DRM_ERROR("Failed to own gpio for panel control\n");
1832 intel_dsi->gpio_panel = NULL;
1833 }
1834 }
1835
1836 intel_encoder->type = INTEL_OUTPUT_DSI;
1837 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1838 intel_encoder->cloneable = 0;
1839 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1840 DRM_MODE_CONNECTOR_DSI);
1841
1842 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1843
1844 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1845 connector->interlace_allowed = false;
1846 connector->doublescan_allowed = false;
1847
1848 intel_connector_attach_encoder(intel_connector, intel_encoder);
1849
1850 mutex_lock(&dev->mode_config.mutex);
1851 intel_dsi_vbt_get_modes(intel_dsi);
1852 list_for_each_entry(scan, &connector->probed_modes, head) {
1853 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1854 fixed_mode = drm_mode_duplicate(dev, scan);
1855 break;
1856 }
1857 }
1858 mutex_unlock(&dev->mode_config.mutex);
1859
1860 if (!fixed_mode) {
1861 DRM_DEBUG_KMS("no fixed mode\n");
1862 goto err;
1863 }
1864
1865 connector->display_info.width_mm = fixed_mode->width_mm;
1866 connector->display_info.height_mm = fixed_mode->height_mm;
1867
1868 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1869 intel_panel_setup_backlight(connector, INVALID_PIPE);
1870
1871 intel_dsi_add_properties(intel_connector);
1872
1873 return;
1874
1875 err:
1876 drm_encoder_cleanup(&intel_encoder->base);
1877 kfree(intel_dsi);
1878 kfree(intel_connector);
1879 }
Linux with added FPC-III support