drivers/i2c/busses/i2c-hix5hd2.c

   1 /*
   2  * Copyright (c) 2014 Linaro Ltd.
   3  * Copyright (c) 2014 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Now only support 7 bit address.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/io.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22
  23 /* Register Map */
  24 #define HIX5I2C_CTRL            0x00
  25 #define HIX5I2C_COM             0x04
  26 #define HIX5I2C_ICR             0x08
  27 #define HIX5I2C_SR              0x0c
  28 #define HIX5I2C_SCL_H           0x10
  29 #define HIX5I2C_SCL_L           0x14
  30 #define HIX5I2C_TXR             0x18
  31 #define HIX5I2C_RXR             0x1c
  32
  33 /* I2C_CTRL_REG */
  34 #define I2C_ENABLE              BIT(8)
  35 #define I2C_UNMASK_TOTAL        BIT(7)
  36 #define I2C_UNMASK_START        BIT(6)
  37 #define I2C_UNMASK_END          BIT(5)
  38 #define I2C_UNMASK_SEND         BIT(4)
  39 #define I2C_UNMASK_RECEIVE      BIT(3)
  40 #define I2C_UNMASK_ACK          BIT(2)
  41 #define I2C_UNMASK_ARBITRATE    BIT(1)
  42 #define I2C_UNMASK_OVER         BIT(0)
  43 #define I2C_UNMASK_ALL          (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
  44
  45 /* I2C_COM_REG */
  46 #define I2C_NO_ACK              BIT(4)
  47 #define I2C_START               BIT(3)
  48 #define I2C_READ                BIT(2)
  49 #define I2C_WRITE               BIT(1)
  50 #define I2C_STOP                BIT(0)
  51
  52 /* I2C_ICR_REG */
  53 #define I2C_CLEAR_START         BIT(6)
  54 #define I2C_CLEAR_END           BIT(5)
  55 #define I2C_CLEAR_SEND          BIT(4)
  56 #define I2C_CLEAR_RECEIVE       BIT(3)
  57 #define I2C_CLEAR_ACK           BIT(2)
  58 #define I2C_CLEAR_ARBITRATE     BIT(1)
  59 #define I2C_CLEAR_OVER          BIT(0)
  60 #define I2C_CLEAR_ALL           (I2C_CLEAR_START | I2C_CLEAR_END | \
  61                                 I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
  62                                 I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
  63                                 I2C_CLEAR_OVER)
  64
  65 /* I2C_SR_REG */
  66 #define I2C_BUSY                BIT(7)
  67 #define I2C_START_INTR          BIT(6)
  68 #define I2C_END_INTR            BIT(5)
  69 #define I2C_SEND_INTR           BIT(4)
  70 #define I2C_RECEIVE_INTR        BIT(3)
  71 #define I2C_ACK_INTR            BIT(2)
  72 #define I2C_ARBITRATE_INTR      BIT(1)
  73 #define I2C_OVER_INTR           BIT(0)
  74
  75 #define HIX5I2C_MAX_FREQ        400000          /* 400k */
  76
  77 enum hix5hd2_i2c_state {
  78         HIX5I2C_STAT_RW_ERR = -1,
  79         HIX5I2C_STAT_INIT,
  80         HIX5I2C_STAT_RW,
  81         HIX5I2C_STAT_SND_STOP,
  82         HIX5I2C_STAT_RW_SUCCESS,
  83 };
  84
  85 struct hix5hd2_i2c_priv {
  86         struct i2c_adapter adap;
  87         struct i2c_msg *msg;
  88         struct completion msg_complete;
  89         unsigned int msg_idx;
  90         unsigned int msg_len;
  91         int stop;
  92         void __iomem *regs;
  93         struct clk *clk;
  94         struct device *dev;
  95         spinlock_t lock;        /* IRQ synchronization */
  96         int err;
  97         unsigned int freq;
  98         enum hix5hd2_i2c_state state;
  99 };
 100
 101 static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv)
 102 {
 103         u32 val = readl_relaxed(priv->regs + HIX5I2C_SR);
 104
 105         writel_relaxed(val, priv->regs + HIX5I2C_ICR);
 106
 107         return val;
 108 }
 109
 110 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv)
 111 {
 112         writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
 113 }
 114
 115 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv)
 116 {
 117         writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
 118 }
 119
 120 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv)
 121 {
 122         writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
 123                        priv->regs + HIX5I2C_CTRL);
 124 }
 125
 126 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv)
 127 {
 128         u32 rate, val;
 129         u32 scl, sysclock;
 130
 131         /* close all i2c interrupt */
 132         val = readl_relaxed(priv->regs + HIX5I2C_CTRL);
 133         writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
 134
 135         rate = priv->freq;
 136         sysclock = clk_get_rate(priv->clk);
 137         scl = (sysclock / (rate * 2)) / 2 - 1;
 138         writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
 139         writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
 140
 141         /* restore original interrupt*/
 142         writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
 143
 144         dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n",
 145                 __func__, sysclock, rate, scl);
 146 }
 147
 148 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv)
 149 {
 150         hix5hd2_i2c_disable_irq(priv);
 151         hix5hd2_i2c_drv_setrate(priv);
 152         hix5hd2_i2c_clr_all_irq(priv);
 153         hix5hd2_i2c_enable_irq(priv);
 154 }
 155
 156 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv)
 157 {
 158         clk_disable_unprepare(priv->clk);
 159         msleep(20);
 160         clk_prepare_enable(priv->clk);
 161         hix5hd2_i2c_init(priv);
 162 }
 163
 164 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv)
 165 {
 166         unsigned long stop_time;
 167         u32 int_status;
 168
 169         /* wait for 100 milli seconds for the bus to be idle */
 170         stop_time = jiffies + msecs_to_jiffies(100);
 171         do {
 172                 int_status = hix5hd2_i2c_clr_pend_irq(priv);
 173                 if (!(int_status & I2C_BUSY))
 174                         return 0;
 175
 176                 usleep_range(50, 200);
 177         } while (time_before(jiffies, stop_time));
 178
 179         return -EBUSY;
 180 }
 181
 182 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv)
 183 {
 184         if (priv->state == HIX5I2C_STAT_SND_STOP)
 185                 dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__);
 186         else
 187                 dev_dbg(priv->dev, "%s: have not data to send\n", __func__);
 188
 189         priv->state = HIX5I2C_STAT_RW_SUCCESS;
 190         priv->err = 0;
 191 }
 192
 193 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv)
 194 {
 195         if (priv->stop) {
 196                 priv->state = HIX5I2C_STAT_SND_STOP;
 197                 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
 198         } else {
 199                 hix5hd2_rw_over(priv);
 200         }
 201 }
 202
 203 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv)
 204 {
 205         if (priv->msg_len == 1) {
 206                 /* the last byte don't need send ACK */
 207                 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM);
 208         } else if (priv->msg_len > 1) {
 209                 /* if i2c master receive data will send ACK */
 210                 writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM);
 211         } else {
 212                 hix5hd2_rw_handle_stop(priv);
 213         }
 214 }
 215
 216 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv)
 217 {
 218         u8 data;
 219
 220         if (priv->msg_len > 0) {
 221                 data = priv->msg->buf[priv->msg_idx++];
 222                 writel_relaxed(data, priv->regs + HIX5I2C_TXR);
 223                 writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM);
 224         } else {
 225                 hix5hd2_rw_handle_stop(priv);
 226         }
 227 }
 228
 229 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv)
 230 {
 231         u8 data;
 232
 233         if (priv->state == HIX5I2C_STAT_INIT) {
 234                 priv->state = HIX5I2C_STAT_RW;
 235         } else if (priv->state == HIX5I2C_STAT_RW) {
 236                 if (priv->msg->flags & I2C_M_RD) {
 237                         data = readl_relaxed(priv->regs + HIX5I2C_RXR);
 238                         priv->msg->buf[priv->msg_idx++] = data;
 239                 }
 240                 priv->msg_len--;
 241         } else {
 242                 dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n",
 243                         __func__, priv->state, priv->msg_len);
 244                 return -EAGAIN;
 245         }
 246         return 0;
 247 }
 248
 249 static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id)
 250 {
 251         struct hix5hd2_i2c_priv *priv = dev_id;
 252         u32 int_status;
 253         int ret;
 254
 255         spin_lock(&priv->lock);
 256
 257         int_status = hix5hd2_i2c_clr_pend_irq(priv);
 258
 259         /* handle error */
 260         if (int_status & I2C_ARBITRATE_INTR) {
 261                 /* bus error */
 262                 dev_dbg(priv->dev, "ARB bus loss\n");
 263                 priv->err = -EAGAIN;
 264                 priv->state = HIX5I2C_STAT_RW_ERR;
 265                 goto stop;
 266         } else if (int_status & I2C_ACK_INTR) {
 267                 /* ack error */
 268                 dev_dbg(priv->dev, "No ACK from device\n");
 269                 priv->err = -ENXIO;
 270                 priv->state = HIX5I2C_STAT_RW_ERR;
 271                 goto stop;
 272         }
 273
 274         if (int_status & I2C_OVER_INTR) {
 275                 if (priv->msg_len > 0) {
 276                         ret = hix5hd2_rw_preprocess(priv);
 277                         if (ret) {
 278                                 priv->err = ret;
 279                                 priv->state = HIX5I2C_STAT_RW_ERR;
 280                                 goto stop;
 281                         }
 282                         if (priv->msg->flags & I2C_M_RD)
 283                                 hix5hd2_read_handle(priv);
 284                         else
 285                                 hix5hd2_write_handle(priv);
 286                 } else {
 287                         hix5hd2_rw_over(priv);
 288                 }
 289         }
 290
 291 stop:
 292         if ((priv->state == HIX5I2C_STAT_RW_SUCCESS &&
 293              priv->msg->len == priv->msg_idx) ||
 294             (priv->state == HIX5I2C_STAT_RW_ERR)) {
 295                 hix5hd2_i2c_disable_irq(priv);
 296                 hix5hd2_i2c_clr_pend_irq(priv);
 297                 complete(&priv->msg_complete);
 298         }
 299
 300         spin_unlock(&priv->lock);
 301
 302         return IRQ_HANDLED;
 303 }
 304
 305 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop)
 306 {
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&priv->lock, flags);
 310         hix5hd2_i2c_clr_all_irq(priv);
 311         hix5hd2_i2c_enable_irq(priv);
 312
 313         writel_relaxed(i2c_8bit_addr_from_msg(priv->msg),
 314                        priv->regs + HIX5I2C_TXR);
 315
 316         writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM);
 317         spin_unlock_irqrestore(&priv->lock, flags);
 318 }
 319
 320 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv,
 321                                 struct i2c_msg *msgs, int stop)
 322 {
 323         unsigned long timeout;
 324         int ret;
 325
 326         priv->msg = msgs;
 327         priv->msg_idx = 0;
 328         priv->msg_len = priv->msg->len;
 329         priv->stop = stop;
 330         priv->err = 0;
 331         priv->state = HIX5I2C_STAT_INIT;
 332
 333         reinit_completion(&priv->msg_complete);
 334         hix5hd2_i2c_message_start(priv, stop);
 335
 336         timeout = wait_for_completion_timeout(&priv->msg_complete,
 337                                               priv->adap.timeout);
 338         if (timeout == 0) {
 339                 priv->state = HIX5I2C_STAT_RW_ERR;
 340                 priv->err = -ETIMEDOUT;
 341                 dev_warn(priv->dev, "%s timeout=%d\n",
 342                          msgs->flags & I2C_M_RD ? "rx" : "tx",
 343                          priv->adap.timeout);
 344         }
 345         ret = priv->state;
 346
 347         /*
 348          * If this is the last message to be transfered (stop == 1)
 349          * Then check if the bus can be brought back to idle.
 350          */
 351         if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop)
 352                 ret = hix5hd2_i2c_wait_bus_idle(priv);
 353
 354         if (ret < 0)
 355                 hix5hd2_i2c_reset(priv);
 356
 357         return priv->err;
 358 }
 359
 360 static int hix5hd2_i2c_xfer(struct i2c_adapter *adap,
 361                             struct i2c_msg *msgs, int num)
 362 {
 363         struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap);
 364         int i, ret, stop;
 365
 366         pm_runtime_get_sync(priv->dev);
 367
 368         for (i = 0; i < num; i++, msgs++) {
 369                 stop = (i == num - 1);
 370                 ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop);
 371                 if (ret < 0)
 372                         goto out;
 373         }
 374
 375         ret = num;
 376
 377 out:
 378         pm_runtime_mark_last_busy(priv->dev);
 379         pm_runtime_put_autosuspend(priv->dev);
 380         return ret;
 381 }
 382
 383 static u32 hix5hd2_i2c_func(struct i2c_adapter *adap)
 384 {
 385         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 386 }
 387
 388 static const struct i2c_algorithm hix5hd2_i2c_algorithm = {
 389         .master_xfer            = hix5hd2_i2c_xfer,
 390         .functionality          = hix5hd2_i2c_func,
 391 };
 392
 393 static int hix5hd2_i2c_probe(struct platform_device *pdev)
 394 {
 395         struct device_node *np = pdev->dev.of_node;
 396         struct hix5hd2_i2c_priv *priv;
 397         struct resource *mem;
 398         unsigned int freq;
 399         int irq, ret;
 400
 401         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 402         if (!priv)
 403                 return -ENOMEM;
 404
 405         if (of_property_read_u32(np, "clock-frequency", &freq)) {
 406                 /* use 100k as default value */
 407                 priv->freq = 100000;
 408         } else {
 409                 if (freq > HIX5I2C_MAX_FREQ) {
 410                         priv->freq = HIX5I2C_MAX_FREQ;
 411                         dev_warn(priv->dev, "use max freq %d instead\n",
 412                                  HIX5I2C_MAX_FREQ);
 413                 } else {
 414                         priv->freq = freq;
 415                 }
 416         }
 417
 418         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 419         priv->regs = devm_ioremap_resource(&pdev->dev, mem);
 420         if (IS_ERR(priv->regs))
 421                 return PTR_ERR(priv->regs);
 422
 423         irq = platform_get_irq(pdev, 0);
 424         if (irq <= 0) {
 425                 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
 426                 return irq;
 427         }
 428
 429         priv->clk = devm_clk_get(&pdev->dev, NULL);
 430         if (IS_ERR(priv->clk)) {
 431                 dev_err(&pdev->dev, "cannot get clock\n");
 432                 return PTR_ERR(priv->clk);
 433         }
 434         clk_prepare_enable(priv->clk);
 435
 436         strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
 437         priv->dev = &pdev->dev;
 438         priv->adap.owner = THIS_MODULE;
 439         priv->adap.algo = &hix5hd2_i2c_algorithm;
 440         priv->adap.retries = 3;
 441         priv->adap.dev.of_node = np;
 442         priv->adap.algo_data = priv;
 443         priv->adap.dev.parent = &pdev->dev;
 444         i2c_set_adapdata(&priv->adap, priv);
 445         platform_set_drvdata(pdev, priv);
 446         spin_lock_init(&priv->lock);
 447         init_completion(&priv->msg_complete);
 448
 449         hix5hd2_i2c_init(priv);
 450
 451         ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq,
 452                                IRQF_NO_SUSPEND | IRQF_ONESHOT,
 453                                dev_name(&pdev->dev), priv);
 454         if (ret != 0) {
 455                 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq);
 456                 goto err_clk;
 457         }
 458
 459         pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC);
 460         pm_runtime_use_autosuspend(priv->dev);
 461         pm_runtime_set_active(priv->dev);
 462         pm_runtime_enable(priv->dev);
 463
 464         ret = i2c_add_adapter(&priv->adap);
 465         if (ret < 0)
 466                 goto err_runtime;
 467
 468         return ret;
 469
 470 err_runtime:
 471         pm_runtime_disable(priv->dev);
 472         pm_runtime_set_suspended(priv->dev);
 473 err_clk:
 474         clk_disable_unprepare(priv->clk);
 475         return ret;
 476 }
 477
 478 static int hix5hd2_i2c_remove(struct platform_device *pdev)
 479 {
 480         struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
 481
 482         i2c_del_adapter(&priv->adap);
 483         pm_runtime_disable(priv->dev);
 484         pm_runtime_set_suspended(priv->dev);
 485         clk_disable_unprepare(priv->clk);
 486
 487         return 0;
 488 }
 489
 490 #ifdef CONFIG_PM
 491 static int hix5hd2_i2c_runtime_suspend(struct device *dev)
 492 {
 493         struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
 494
 495         clk_disable_unprepare(priv->clk);
 496
 497         return 0;
 498 }
 499
 500 static int hix5hd2_i2c_runtime_resume(struct device *dev)
 501 {
 502         struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
 503
 504         clk_prepare_enable(priv->clk);
 505         hix5hd2_i2c_init(priv);
 506
 507         return 0;
 508 }
 509 #endif
 510
 511 static const struct dev_pm_ops hix5hd2_i2c_pm_ops = {
 512         SET_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend,
 513                               hix5hd2_i2c_runtime_resume,
 514                               NULL)
 515 };
 516
 517 static const struct of_device_id hix5hd2_i2c_match[] = {
 518         { .compatible = "hisilicon,hix5hd2-i2c" },
 519         {},
 520 };
 521 MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match);
 522
 523 static struct platform_driver hix5hd2_i2c_driver = {
 524         .probe          = hix5hd2_i2c_probe,
 525         .remove         = hix5hd2_i2c_remove,
 526         .driver         = {
 527                 .name   = "hix5hd2-i2c",
 528                 .pm     = &hix5hd2_i2c_pm_ops,
 529                 .of_match_table = hix5hd2_i2c_match,
 530         },
 531 };
 532
 533 module_platform_driver(hix5hd2_i2c_driver);
 534
 535 MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
 536 MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>");
 537 MODULE_LICENSE("GPL");
 538 MODULE_ALIAS("platform:hix5hd2-i2c");