drivers/mmc/host/sdhci-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /*
  15  * iProc SDHCI platform driver
  16  */
  17
  18 #include <linux/delay.h>
  19 #include <linux/module.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include "sdhci-pltfm.h"
  24
  25 struct sdhci_iproc_data {
  26         const struct sdhci_pltfm_data *pdata;
  27         u32 caps;
  28         u32 caps1;
  29         u32 mmc_caps;
  30 };
  31
  32 struct sdhci_iproc_host {
  33         const struct sdhci_iproc_data *data;
  34         u32 shadow_cmd;
  35         u32 shadow_blk;
  36         bool is_cmd_shadowed;
  37         bool is_blk_shadowed;
  38 };
  39
  40 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
  41
  42 static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
  43 {
  44         u32 val = readl(host->ioaddr + reg);
  45
  46         pr_debug("%s: readl [0x%02x] 0x%08x\n",
  47                  mmc_hostname(host->mmc), reg, val);
  48         return val;
  49 }
  50
  51 static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
  52 {
  53         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  54         struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
  55         u32 val;
  56         u16 word;
  57
  58         if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
  59                 /* Get the saved transfer mode */
  60                 val = iproc_host->shadow_cmd;
  61         } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
  62                    iproc_host->is_blk_shadowed) {
  63                 /* Get the saved block info */
  64                 val = iproc_host->shadow_blk;
  65         } else {
  66                 val = sdhci_iproc_readl(host, (reg & ~3));
  67         }
  68         word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
  69         return word;
  70 }
  71
  72 static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
  73 {
  74         u32 val = sdhci_iproc_readl(host, (reg & ~3));
  75         u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
  76         return byte;
  77 }
  78
  79 static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
  80 {
  81         pr_debug("%s: writel [0x%02x] 0x%08x\n",
  82                  mmc_hostname(host->mmc), reg, val);
  83
  84         writel(val, host->ioaddr + reg);
  85
  86         if (host->clock <= 400000) {
  87                 /* Round up to micro-second four SD clock delay */
  88                 if (host->clock)
  89                         udelay((4 * 1000000 + host->clock - 1) / host->clock);
  90                 else
  91                         udelay(10);
  92         }
  93 }
  94
  95 /*
  96  * The Arasan has a bugette whereby it may lose the content of successive
  97  * writes to the same register that are within two SD-card clock cycles of
  98  * each other (a clock domain crossing problem). The data
  99  * register does not have this problem, which is just as well - otherwise we'd
 100  * have to nobble the DMA engine too.
 101  *
 102  * This wouldn't be a problem with the code except that we can only write the
 103  * controller with 32-bit writes.  So two different 16-bit registers are
 104  * written back to back creates the problem.
 105  *
 106  * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
 107  * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
 108  * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
 109  * the work around can be further optimized. We can keep shadow values of
 110  * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
 111  * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
 112  * by the TRANSFER+COMMAND in another 32-bit write.
 113  */
 114 static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
 115 {
 116         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 117         struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
 118         u32 word_shift = REG_OFFSET_IN_BITS(reg);
 119         u32 mask = 0xffff << word_shift;
 120         u32 oldval, newval;
 121
 122         if (reg == SDHCI_COMMAND) {
 123                 /* Write the block now as we are issuing a command */
 124                 if (iproc_host->is_blk_shadowed) {
 125                         sdhci_iproc_writel(host, iproc_host->shadow_blk,
 126                                 SDHCI_BLOCK_SIZE);
 127                         iproc_host->is_blk_shadowed = false;
 128                 }
 129                 oldval = iproc_host->shadow_cmd;
 130                 iproc_host->is_cmd_shadowed = false;
 131         } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
 132                    iproc_host->is_blk_shadowed) {
 133                 /* Block size and count are stored in shadow reg */
 134                 oldval = iproc_host->shadow_blk;
 135         } else {
 136                 /* Read reg, all other registers are not shadowed */
 137                 oldval = sdhci_iproc_readl(host, (reg & ~3));
 138         }
 139         newval = (oldval & ~mask) | (val << word_shift);
 140
 141         if (reg == SDHCI_TRANSFER_MODE) {
 142                 /* Save the transfer mode until the command is issued */
 143                 iproc_host->shadow_cmd = newval;
 144                 iproc_host->is_cmd_shadowed = true;
 145         } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
 146                 /* Save the block info until the command is issued */
 147                 iproc_host->shadow_blk = newval;
 148                 iproc_host->is_blk_shadowed = true;
 149         } else {
 150                 /* Command or other regular 32-bit write */
 151                 sdhci_iproc_writel(host, newval, reg & ~3);
 152         }
 153 }
 154
 155 static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
 156 {
 157         u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
 158         u32 byte_shift = REG_OFFSET_IN_BITS(reg);
 159         u32 mask = 0xff << byte_shift;
 160         u32 newval = (oldval & ~mask) | (val << byte_shift);
 161
 162         sdhci_iproc_writel(host, newval, reg & ~3);
 163 }
 164
 165 static const struct sdhci_ops sdhci_iproc_ops = {
 166         .set_clock = sdhci_set_clock,
 167         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 168         .set_bus_width = sdhci_set_bus_width,
 169         .reset = sdhci_reset,
 170         .set_uhs_signaling = sdhci_set_uhs_signaling,
 171 };
 172
 173 static const struct sdhci_ops sdhci_iproc_32only_ops = {
 174         .read_l = sdhci_iproc_readl,
 175         .read_w = sdhci_iproc_readw,
 176         .read_b = sdhci_iproc_readb,
 177         .write_l = sdhci_iproc_writel,
 178         .write_w = sdhci_iproc_writew,
 179         .write_b = sdhci_iproc_writeb,
 180         .set_clock = sdhci_set_clock,
 181         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 182         .set_bus_width = sdhci_set_bus_width,
 183         .reset = sdhci_reset,
 184         .set_uhs_signaling = sdhci_set_uhs_signaling,
 185 };
 186
 187 static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
 188         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 189                   SDHCI_QUIRK_NO_HISPD_BIT,
 190         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
 191         .ops = &sdhci_iproc_32only_ops,
 192 };
 193
 194 static const struct sdhci_iproc_data iproc_cygnus_data = {
 195         .pdata = &sdhci_iproc_cygnus_pltfm_data,
 196         .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
 197                         & SDHCI_MAX_BLOCK_MASK) |
 198                 SDHCI_CAN_VDD_330 |
 199                 SDHCI_CAN_VDD_180 |
 200                 SDHCI_CAN_DO_SUSPEND |
 201                 SDHCI_CAN_DO_HISPD |
 202                 SDHCI_CAN_DO_ADMA2 |
 203                 SDHCI_CAN_DO_SDMA,
 204         .caps1 = SDHCI_DRIVER_TYPE_C |
 205                  SDHCI_DRIVER_TYPE_D |
 206                  SDHCI_SUPPORT_DDR50,
 207         .mmc_caps = MMC_CAP_1_8V_DDR,
 208 };
 209
 210 static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
 211         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 212                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
 213                   SDHCI_QUIRK_NO_HISPD_BIT,
 214         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
 215         .ops = &sdhci_iproc_ops,
 216 };
 217
 218 static const struct sdhci_iproc_data iproc_data = {
 219         .pdata = &sdhci_iproc_pltfm_data,
 220         .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
 221                         & SDHCI_MAX_BLOCK_MASK) |
 222                 SDHCI_CAN_VDD_330 |
 223                 SDHCI_CAN_VDD_180 |
 224                 SDHCI_CAN_DO_SUSPEND |
 225                 SDHCI_CAN_DO_HISPD |
 226                 SDHCI_CAN_DO_ADMA2 |
 227                 SDHCI_CAN_DO_SDMA,
 228         .caps1 = SDHCI_DRIVER_TYPE_C |
 229                  SDHCI_DRIVER_TYPE_D |
 230                  SDHCI_SUPPORT_DDR50,
 231 };
 232
 233 static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
 234         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 235                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 236                   SDHCI_QUIRK_MISSING_CAPS |
 237                   SDHCI_QUIRK_NO_HISPD_BIT,
 238         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 239         .ops = &sdhci_iproc_32only_ops,
 240 };
 241
 242 static const struct sdhci_iproc_data bcm2835_data = {
 243         .pdata = &sdhci_bcm2835_pltfm_data,
 244         .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
 245                         & SDHCI_MAX_BLOCK_MASK) |
 246                 SDHCI_CAN_VDD_330 |
 247                 SDHCI_CAN_DO_HISPD,
 248         .caps1 = SDHCI_DRIVER_TYPE_A |
 249                  SDHCI_DRIVER_TYPE_C,
 250         .mmc_caps = 0x00000000,
 251 };
 252
 253 static const struct of_device_id sdhci_iproc_of_match[] = {
 254         { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
 255         { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
 256         { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
 257         { }
 258 };
 259 MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
 260
 261 static int sdhci_iproc_probe(struct platform_device *pdev)
 262 {
 263         const struct of_device_id *match;
 264         const struct sdhci_iproc_data *iproc_data;
 265         struct sdhci_host *host;
 266         struct sdhci_iproc_host *iproc_host;
 267         struct sdhci_pltfm_host *pltfm_host;
 268         int ret;
 269
 270         match = of_match_device(sdhci_iproc_of_match, &pdev->dev);
 271         if (!match)
 272                 return -EINVAL;
 273         iproc_data = match->data;
 274
 275         host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
 276         if (IS_ERR(host))
 277                 return PTR_ERR(host);
 278
 279         pltfm_host = sdhci_priv(host);
 280         iproc_host = sdhci_pltfm_priv(pltfm_host);
 281
 282         iproc_host->data = iproc_data;
 283
 284         ret = mmc_of_parse(host->mmc);
 285         if (ret)
 286                 goto err;
 287
 288         sdhci_get_of_property(pdev);
 289
 290         host->mmc->caps |= iproc_host->data->mmc_caps;
 291
 292         pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
 293         if (IS_ERR(pltfm_host->clk)) {
 294                 ret = PTR_ERR(pltfm_host->clk);
 295                 goto err;
 296         }
 297         ret = clk_prepare_enable(pltfm_host->clk);
 298         if (ret) {
 299                 dev_err(&pdev->dev, "failed to enable host clk\n");
 300                 goto err;
 301         }
 302
 303         if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
 304                 host->caps = iproc_host->data->caps;
 305                 host->caps1 = iproc_host->data->caps1;
 306         }
 307
 308         ret = sdhci_add_host(host);
 309         if (ret)
 310                 goto err_clk;
 311
 312         return 0;
 313
 314 err_clk:
 315         clk_disable_unprepare(pltfm_host->clk);
 316 err:
 317         sdhci_pltfm_free(pdev);
 318         return ret;
 319 }
 320
 321 static struct platform_driver sdhci_iproc_driver = {
 322         .driver = {
 323                 .name = "sdhci-iproc",
 324                 .of_match_table = sdhci_iproc_of_match,
 325                 .pm = &sdhci_pltfm_pmops,
 326         },
 327         .probe = sdhci_iproc_probe,
 328         .remove = sdhci_pltfm_unregister,
 329 };
 330 module_platform_driver(sdhci_iproc_driver);
 331
 332 MODULE_AUTHOR("Broadcom");
 333 MODULE_DESCRIPTION("IPROC SDHCI driver");
 334 MODULE_LICENSE("GPL v2");