drivers/mmc/host/sdhci-of-esdhc.c

   1 /*
   2  * Freescale eSDHC controller driver.
   3  *
   4  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
   5  * Copyright (c) 2009 MontaVista Software, Inc.
   6  *
   7  * Authors: Xiaobo Xie <X.Xie@freescale.com>
   8  *          Anton Vorontsov <avorontsov@ru.mvista.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/sys_soc.h>
  23 #include <linux/clk.h>
  24 #include <linux/ktime.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/mmc/host.h>
  27 #include "sdhci-pltfm.h"
  28 #include "sdhci-esdhc.h"
  29
  30 #define VENDOR_V_22     0x12
  31 #define VENDOR_V_23     0x13
  32
  33 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
  34
  35 struct esdhc_clk_fixup {
  36         const unsigned int sd_dflt_max_clk;
  37         const unsigned int max_clk[MMC_TIMING_NUM];
  38 };
  39
  40 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
  41         .sd_dflt_max_clk = 25000000,
  42         .max_clk[MMC_TIMING_MMC_HS] = 46500000,
  43         .max_clk[MMC_TIMING_SD_HS] = 46500000,
  44 };
  45
  46 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
  47         .sd_dflt_max_clk = 25000000,
  48         .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
  49         .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
  50 };
  51
  52 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
  53         .sd_dflt_max_clk = 25000000,
  54         .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
  55         .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
  56 };
  57
  58 static const struct esdhc_clk_fixup p1010_esdhc_clk = {
  59         .sd_dflt_max_clk = 20000000,
  60         .max_clk[MMC_TIMING_LEGACY] = 20000000,
  61         .max_clk[MMC_TIMING_MMC_HS] = 42000000,
  62         .max_clk[MMC_TIMING_SD_HS] = 40000000,
  63 };
  64
  65 static const struct of_device_id sdhci_esdhc_of_match[] = {
  66         { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
  67         { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
  68         { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
  69         { .compatible = "fsl,p1010-esdhc",   .data = &p1010_esdhc_clk},
  70         { .compatible = "fsl,mpc8379-esdhc" },
  71         { .compatible = "fsl,mpc8536-esdhc" },
  72         { .compatible = "fsl,esdhc" },
  73         { }
  74 };
  75 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
  76
  77 struct sdhci_esdhc {
  78         u8 vendor_ver;
  79         u8 spec_ver;
  80         bool quirk_incorrect_hostver;
  81         unsigned int peripheral_clock;
  82         const struct esdhc_clk_fixup *clk_fixup;
  83 };
  84
  85 /**
  86  * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
  87  *                     to make it compatible with SD spec.
  88  *
  89  * @host: pointer to sdhci_host
  90  * @spec_reg: SD spec register address
  91  * @value: 32bit eSDHC register value on spec_reg address
  92  *
  93  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
  94  * registers are 32 bits. There are differences in register size, register
  95  * address, register function, bit position and function between eSDHC spec
  96  * and SD spec.
  97  *
  98  * Return a fixed up register value
  99  */
 100 static u32 esdhc_readl_fixup(struct sdhci_host *host,
 101                                      int spec_reg, u32 value)
 102 {
 103         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 104         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 105         u32 ret;
 106
 107         /*
 108          * The bit of ADMA flag in eSDHC is not compatible with standard
 109          * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
 110          * supported by eSDHC.
 111          * And for many FSL eSDHC controller, the reset value of field
 112          * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
 113          * only these vendor version is greater than 2.2/0x12 support ADMA.
 114          */
 115         if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
 116                 if (esdhc->vendor_ver > VENDOR_V_22) {
 117                         ret = value | SDHCI_CAN_DO_ADMA2;
 118                         return ret;
 119                 }
 120         }
 121         /*
 122          * The DAT[3:0] line signal levels and the CMD line signal level are
 123          * not compatible with standard SDHC register. The line signal levels
 124          * DAT[7:0] are at bits 31:24 and the command line signal level is at
 125          * bit 23. All other bits are the same as in the standard SDHC
 126          * register.
 127          */
 128         if (spec_reg == SDHCI_PRESENT_STATE) {
 129                 ret = value & 0x000fffff;
 130                 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
 131                 ret |= (value << 1) & SDHCI_CMD_LVL;
 132                 return ret;
 133         }
 134
 135         /*
 136          * DTS properties of mmc host are used to enable each speed mode
 137          * according to soc and board capability. So clean up
 138          * SDR50/SDR104/DDR50 support bits here.
 139          */
 140         if (spec_reg == SDHCI_CAPABILITIES_1) {
 141                 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
 142                                 SDHCI_SUPPORT_DDR50);
 143                 return ret;
 144         }
 145
 146         ret = value;
 147         return ret;
 148 }
 149
 150 static u16 esdhc_readw_fixup(struct sdhci_host *host,
 151                                      int spec_reg, u32 value)
 152 {
 153         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 154         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 155         u16 ret;
 156         int shift = (spec_reg & 0x2) * 8;
 157
 158         if (spec_reg == SDHCI_HOST_VERSION)
 159                 ret = value & 0xffff;
 160         else
 161                 ret = (value >> shift) & 0xffff;
 162         /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
 163          * vendor version and spec version information.
 164          */
 165         if ((spec_reg == SDHCI_HOST_VERSION) &&
 166             (esdhc->quirk_incorrect_hostver))
 167                 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
 168         return ret;
 169 }
 170
 171 static u8 esdhc_readb_fixup(struct sdhci_host *host,
 172                                      int spec_reg, u32 value)
 173 {
 174         u8 ret;
 175         u8 dma_bits;
 176         int shift = (spec_reg & 0x3) * 8;
 177
 178         ret = (value >> shift) & 0xff;
 179
 180         /*
 181          * "DMA select" locates at offset 0x28 in SD specification, but on
 182          * P5020 or P3041, it locates at 0x29.
 183          */
 184         if (spec_reg == SDHCI_HOST_CONTROL) {
 185                 /* DMA select is 22,23 bits in Protocol Control Register */
 186                 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
 187                 /* fixup the result */
 188                 ret &= ~SDHCI_CTRL_DMA_MASK;
 189                 ret |= dma_bits;
 190         }
 191         return ret;
 192 }
 193
 194 /**
 195  * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
 196  *                      written into eSDHC register.
 197  *
 198  * @host: pointer to sdhci_host
 199  * @spec_reg: SD spec register address
 200  * @value: 8/16/32bit SD spec register value that would be written
 201  * @old_value: 32bit eSDHC register value on spec_reg address
 202  *
 203  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
 204  * registers are 32 bits. There are differences in register size, register
 205  * address, register function, bit position and function between eSDHC spec
 206  * and SD spec.
 207  *
 208  * Return a fixed up register value
 209  */
 210 static u32 esdhc_writel_fixup(struct sdhci_host *host,
 211                                      int spec_reg, u32 value, u32 old_value)
 212 {
 213         u32 ret;
 214
 215         /*
 216          * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
 217          * when SYSCTL[RSTD] is set for some special operations.
 218          * No any impact on other operation.
 219          */
 220         if (spec_reg == SDHCI_INT_ENABLE)
 221                 ret = value | SDHCI_INT_BLK_GAP;
 222         else
 223                 ret = value;
 224
 225         return ret;
 226 }
 227
 228 static u32 esdhc_writew_fixup(struct sdhci_host *host,
 229                                      int spec_reg, u16 value, u32 old_value)
 230 {
 231         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 232         int shift = (spec_reg & 0x2) * 8;
 233         u32 ret;
 234
 235         switch (spec_reg) {
 236         case SDHCI_TRANSFER_MODE:
 237                 /*
 238                  * Postpone this write, we must do it together with a
 239                  * command write that is down below. Return old value.
 240                  */
 241                 pltfm_host->xfer_mode_shadow = value;
 242                 return old_value;
 243         case SDHCI_COMMAND:
 244                 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
 245                 return ret;
 246         }
 247
 248         ret = old_value & (~(0xffff << shift));
 249         ret |= (value << shift);
 250
 251         if (spec_reg == SDHCI_BLOCK_SIZE) {
 252                 /*
 253                  * Two last DMA bits are reserved, and first one is used for
 254                  * non-standard blksz of 4096 bytes that we don't support
 255                  * yet. So clear the DMA boundary bits.
 256                  */
 257                 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
 258         }
 259         return ret;
 260 }
 261
 262 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
 263                                      int spec_reg, u8 value, u32 old_value)
 264 {
 265         u32 ret;
 266         u32 dma_bits;
 267         u8 tmp;
 268         int shift = (spec_reg & 0x3) * 8;
 269
 270         /*
 271          * eSDHC doesn't have a standard power control register, so we do
 272          * nothing here to avoid incorrect operation.
 273          */
 274         if (spec_reg == SDHCI_POWER_CONTROL)
 275                 return old_value;
 276         /*
 277          * "DMA select" location is offset 0x28 in SD specification, but on
 278          * P5020 or P3041, it's located at 0x29.
 279          */
 280         if (spec_reg == SDHCI_HOST_CONTROL) {
 281                 /*
 282                  * If host control register is not standard, exit
 283                  * this function
 284                  */
 285                 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
 286                         return old_value;
 287
 288                 /* DMA select is 22,23 bits in Protocol Control Register */
 289                 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
 290                 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
 291                 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
 292                       (old_value & SDHCI_CTRL_DMA_MASK);
 293                 ret = (ret & (~0xff)) | tmp;
 294
 295                 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
 296                 ret &= ~ESDHC_HOST_CONTROL_RES;
 297                 return ret;
 298         }
 299
 300         ret = (old_value & (~(0xff << shift))) | (value << shift);
 301         return ret;
 302 }
 303
 304 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
 305 {
 306         u32 ret;
 307         u32 value;
 308
 309         if (reg == SDHCI_CAPABILITIES_1)
 310                 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
 311         else
 312                 value = ioread32be(host->ioaddr + reg);
 313
 314         ret = esdhc_readl_fixup(host, reg, value);
 315
 316         return ret;
 317 }
 318
 319 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
 320 {
 321         u32 ret;
 322         u32 value;
 323
 324         if (reg == SDHCI_CAPABILITIES_1)
 325                 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
 326         else
 327                 value = ioread32(host->ioaddr + reg);
 328
 329         ret = esdhc_readl_fixup(host, reg, value);
 330
 331         return ret;
 332 }
 333
 334 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
 335 {
 336         u16 ret;
 337         u32 value;
 338         int base = reg & ~0x3;
 339
 340         value = ioread32be(host->ioaddr + base);
 341         ret = esdhc_readw_fixup(host, reg, value);
 342         return ret;
 343 }
 344
 345 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
 346 {
 347         u16 ret;
 348         u32 value;
 349         int base = reg & ~0x3;
 350
 351         value = ioread32(host->ioaddr + base);
 352         ret = esdhc_readw_fixup(host, reg, value);
 353         return ret;
 354 }
 355
 356 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
 357 {
 358         u8 ret;
 359         u32 value;
 360         int base = reg & ~0x3;
 361
 362         value = ioread32be(host->ioaddr + base);
 363         ret = esdhc_readb_fixup(host, reg, value);
 364         return ret;
 365 }
 366
 367 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
 368 {
 369         u8 ret;
 370         u32 value;
 371         int base = reg & ~0x3;
 372
 373         value = ioread32(host->ioaddr + base);
 374         ret = esdhc_readb_fixup(host, reg, value);
 375         return ret;
 376 }
 377
 378 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
 379 {
 380         u32 value;
 381
 382         value = esdhc_writel_fixup(host, reg, val, 0);
 383         iowrite32be(value, host->ioaddr + reg);
 384 }
 385
 386 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
 387 {
 388         u32 value;
 389
 390         value = esdhc_writel_fixup(host, reg, val, 0);
 391         iowrite32(value, host->ioaddr + reg);
 392 }
 393
 394 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
 395 {
 396         int base = reg & ~0x3;
 397         u32 value;
 398         u32 ret;
 399
 400         value = ioread32be(host->ioaddr + base);
 401         ret = esdhc_writew_fixup(host, reg, val, value);
 402         if (reg != SDHCI_TRANSFER_MODE)
 403                 iowrite32be(ret, host->ioaddr + base);
 404 }
 405
 406 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
 407 {
 408         int base = reg & ~0x3;
 409         u32 value;
 410         u32 ret;
 411
 412         value = ioread32(host->ioaddr + base);
 413         ret = esdhc_writew_fixup(host, reg, val, value);
 414         if (reg != SDHCI_TRANSFER_MODE)
 415                 iowrite32(ret, host->ioaddr + base);
 416 }
 417
 418 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
 419 {
 420         int base = reg & ~0x3;
 421         u32 value;
 422         u32 ret;
 423
 424         value = ioread32be(host->ioaddr + base);
 425         ret = esdhc_writeb_fixup(host, reg, val, value);
 426         iowrite32be(ret, host->ioaddr + base);
 427 }
 428
 429 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
 430 {
 431         int base = reg & ~0x3;
 432         u32 value;
 433         u32 ret;
 434
 435         value = ioread32(host->ioaddr + base);
 436         ret = esdhc_writeb_fixup(host, reg, val, value);
 437         iowrite32(ret, host->ioaddr + base);
 438 }
 439
 440 /*
 441  * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
 442  * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
 443  * and Block Gap Event(IRQSTAT[BGE]) are also set.
 444  * For Continue, apply soft reset for data(SYSCTL[RSTD]);
 445  * and re-issue the entire read transaction from beginning.
 446  */
 447 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
 448 {
 449         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 450         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 451         bool applicable;
 452         dma_addr_t dmastart;
 453         dma_addr_t dmanow;
 454
 455         applicable = (intmask & SDHCI_INT_DATA_END) &&
 456                      (intmask & SDHCI_INT_BLK_GAP) &&
 457                      (esdhc->vendor_ver == VENDOR_V_23);
 458         if (!applicable)
 459                 return;
 460
 461         host->data->error = 0;
 462         dmastart = sg_dma_address(host->data->sg);
 463         dmanow = dmastart + host->data->bytes_xfered;
 464         /*
 465          * Force update to the next DMA block boundary.
 466          */
 467         dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
 468                 SDHCI_DEFAULT_BOUNDARY_SIZE;
 469         host->data->bytes_xfered = dmanow - dmastart;
 470         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
 471 }
 472
 473 static int esdhc_of_enable_dma(struct sdhci_host *host)
 474 {
 475         u32 value;
 476         struct device *dev = mmc_dev(host->mmc);
 477
 478         if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
 479             of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc"))
 480                 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 481
 482         value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
 483
 484         if (of_dma_is_coherent(dev->of_node))
 485                 value |= ESDHC_DMA_SNOOP;
 486         else
 487                 value &= ~ESDHC_DMA_SNOOP;
 488
 489         sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
 490         return 0;
 491 }
 492
 493 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
 494 {
 495         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 496         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 497
 498         if (esdhc->peripheral_clock)
 499                 return esdhc->peripheral_clock;
 500         else
 501                 return pltfm_host->clock;
 502 }
 503
 504 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
 505 {
 506         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 507         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 508         unsigned int clock;
 509
 510         if (esdhc->peripheral_clock)
 511                 clock = esdhc->peripheral_clock;
 512         else
 513                 clock = pltfm_host->clock;
 514         return clock / 256 / 16;
 515 }
 516
 517 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
 518 {
 519         u32 val;
 520         ktime_t timeout;
 521
 522         val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 523
 524         if (enable)
 525                 val |= ESDHC_CLOCK_SDCLKEN;
 526         else
 527                 val &= ~ESDHC_CLOCK_SDCLKEN;
 528
 529         sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
 530
 531         /* Wait max 20 ms */
 532         timeout = ktime_add_ms(ktime_get(), 20);
 533         val = ESDHC_CLOCK_STABLE;
 534         while  (1) {
 535                 bool timedout = ktime_after(ktime_get(), timeout);
 536
 537                 if (sdhci_readl(host, ESDHC_PRSSTAT) & val)
 538                         break;
 539                 if (timedout) {
 540                         pr_err("%s: Internal clock never stabilised.\n",
 541                                 mmc_hostname(host->mmc));
 542                         break;
 543                 }
 544                 udelay(10);
 545         }
 546 }
 547
 548 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
 549 {
 550         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 551         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 552         int pre_div = 1;
 553         int div = 1;
 554         ktime_t timeout;
 555         long fixup = 0;
 556         u32 temp;
 557
 558         host->mmc->actual_clock = 0;
 559
 560         if (clock == 0) {
 561                 esdhc_clock_enable(host, false);
 562                 return;
 563         }
 564
 565         /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
 566         if (esdhc->vendor_ver < VENDOR_V_23)
 567                 pre_div = 2;
 568
 569         if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
 570                 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
 571                 fixup = esdhc->clk_fixup->sd_dflt_max_clk;
 572         else if (esdhc->clk_fixup)
 573                 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
 574
 575         if (fixup && clock > fixup)
 576                 clock = fixup;
 577
 578         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 579         temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
 580                   ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
 581         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 582
 583         while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
 584                 pre_div *= 2;
 585
 586         while (host->max_clk / pre_div / div > clock && div < 16)
 587                 div++;
 588
 589         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 590                 clock, host->max_clk / pre_div / div);
 591         host->mmc->actual_clock = host->max_clk / pre_div / div;
 592         pre_div >>= 1;
 593         div--;
 594
 595         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 596         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 597                 | (div << ESDHC_DIVIDER_SHIFT)
 598                 | (pre_div << ESDHC_PREDIV_SHIFT));
 599         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 600
 601         /* Wait max 20 ms */
 602         timeout = ktime_add_ms(ktime_get(), 20);
 603         while (1) {
 604                 bool timedout = ktime_after(ktime_get(), timeout);
 605
 606                 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
 607                         break;
 608                 if (timedout) {
 609                         pr_err("%s: Internal clock never stabilised.\n",
 610                                 mmc_hostname(host->mmc));
 611                         return;
 612                 }
 613                 udelay(10);
 614         }
 615
 616         temp |= ESDHC_CLOCK_SDCLKEN;
 617         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 618 }
 619
 620 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 621 {
 622         u32 ctrl;
 623
 624         ctrl = sdhci_readl(host, ESDHC_PROCTL);
 625         ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
 626         switch (width) {
 627         case MMC_BUS_WIDTH_8:
 628                 ctrl |= ESDHC_CTRL_8BITBUS;
 629                 break;
 630
 631         case MMC_BUS_WIDTH_4:
 632                 ctrl |= ESDHC_CTRL_4BITBUS;
 633                 break;
 634
 635         default:
 636                 break;
 637         }
 638
 639         sdhci_writel(host, ctrl, ESDHC_PROCTL);
 640 }
 641
 642 static void esdhc_reset(struct sdhci_host *host, u8 mask)
 643 {
 644         u32 val;
 645
 646         sdhci_reset(host, mask);
 647
 648         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 649         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 650
 651         if (mask & SDHCI_RESET_ALL) {
 652                 val = sdhci_readl(host, ESDHC_TBCTL);
 653                 val &= ~ESDHC_TB_EN;
 654                 sdhci_writel(host, val, ESDHC_TBCTL);
 655         }
 656 }
 657
 658 /* The SCFG, Supplemental Configuration Unit, provides SoC specific
 659  * configuration and status registers for the device. There is a
 660  * SDHC IO VSEL control register on SCFG for some platforms. It's
 661  * used to support SDHC IO voltage switching.
 662  */
 663 static const struct of_device_id scfg_device_ids[] = {
 664         { .compatible = "fsl,t1040-scfg", },
 665         { .compatible = "fsl,ls1012a-scfg", },
 666         { .compatible = "fsl,ls1046a-scfg", },
 667         {}
 668 };
 669
 670 /* SDHC IO VSEL control register definition */
 671 #define SCFG_SDHCIOVSELCR       0x408
 672 #define SDHCIOVSELCR_TGLEN      0x80000000
 673 #define SDHCIOVSELCR_VSELVAL    0x60000000
 674 #define SDHCIOVSELCR_SDHC_VS    0x00000001
 675
 676 static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
 677                                        struct mmc_ios *ios)
 678 {
 679         struct sdhci_host *host = mmc_priv(mmc);
 680         struct device_node *scfg_node;
 681         void __iomem *scfg_base = NULL;
 682         u32 sdhciovselcr;
 683         u32 val;
 684
 685         /*
 686          * Signal Voltage Switching is only applicable for Host Controllers
 687          * v3.00 and above.
 688          */
 689         if (host->version < SDHCI_SPEC_300)
 690                 return 0;
 691
 692         val = sdhci_readl(host, ESDHC_PROCTL);
 693
 694         switch (ios->signal_voltage) {
 695         case MMC_SIGNAL_VOLTAGE_330:
 696                 val &= ~ESDHC_VOLT_SEL;
 697                 sdhci_writel(host, val, ESDHC_PROCTL);
 698                 return 0;
 699         case MMC_SIGNAL_VOLTAGE_180:
 700                 scfg_node = of_find_matching_node(NULL, scfg_device_ids);
 701                 if (scfg_node)
 702                         scfg_base = of_iomap(scfg_node, 0);
 703                 if (scfg_base) {
 704                         sdhciovselcr = SDHCIOVSELCR_TGLEN |
 705                                        SDHCIOVSELCR_VSELVAL;
 706                         iowrite32be(sdhciovselcr,
 707                                 scfg_base + SCFG_SDHCIOVSELCR);
 708
 709                         val |= ESDHC_VOLT_SEL;
 710                         sdhci_writel(host, val, ESDHC_PROCTL);
 711                         mdelay(5);
 712
 713                         sdhciovselcr = SDHCIOVSELCR_TGLEN |
 714                                        SDHCIOVSELCR_SDHC_VS;
 715                         iowrite32be(sdhciovselcr,
 716                                 scfg_base + SCFG_SDHCIOVSELCR);
 717                         iounmap(scfg_base);
 718                 } else {
 719                         val |= ESDHC_VOLT_SEL;
 720                         sdhci_writel(host, val, ESDHC_PROCTL);
 721                 }
 722                 return 0;
 723         default:
 724                 return 0;
 725         }
 726 }
 727
 728 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 729 {
 730         struct sdhci_host *host = mmc_priv(mmc);
 731         u32 val;
 732
 733         /* Use tuning block for tuning procedure */
 734         esdhc_clock_enable(host, false);
 735         val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
 736         val |= ESDHC_FLUSH_ASYNC_FIFO;
 737         sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
 738
 739         val = sdhci_readl(host, ESDHC_TBCTL);
 740         val |= ESDHC_TB_EN;
 741         sdhci_writel(host, val, ESDHC_TBCTL);
 742         esdhc_clock_enable(host, true);
 743
 744         return sdhci_execute_tuning(mmc, opcode);
 745 }
 746
 747 #ifdef CONFIG_PM_SLEEP
 748 static u32 esdhc_proctl;
 749 static int esdhc_of_suspend(struct device *dev)
 750 {
 751         struct sdhci_host *host = dev_get_drvdata(dev);
 752
 753         esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
 754
 755         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 756                 mmc_retune_needed(host->mmc);
 757
 758         return sdhci_suspend_host(host);
 759 }
 760
 761 static int esdhc_of_resume(struct device *dev)
 762 {
 763         struct sdhci_host *host = dev_get_drvdata(dev);
 764         int ret = sdhci_resume_host(host);
 765
 766         if (ret == 0) {
 767                 /* Isn't this already done by sdhci_resume_host() ? --rmk */
 768                 esdhc_of_enable_dma(host);
 769                 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
 770         }
 771         return ret;
 772 }
 773 #endif
 774
 775 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
 776                         esdhc_of_suspend,
 777                         esdhc_of_resume);
 778
 779 static const struct sdhci_ops sdhci_esdhc_be_ops = {
 780         .read_l = esdhc_be_readl,
 781         .read_w = esdhc_be_readw,
 782         .read_b = esdhc_be_readb,
 783         .write_l = esdhc_be_writel,
 784         .write_w = esdhc_be_writew,
 785         .write_b = esdhc_be_writeb,
 786         .set_clock = esdhc_of_set_clock,
 787         .enable_dma = esdhc_of_enable_dma,
 788         .get_max_clock = esdhc_of_get_max_clock,
 789         .get_min_clock = esdhc_of_get_min_clock,
 790         .adma_workaround = esdhc_of_adma_workaround,
 791         .set_bus_width = esdhc_pltfm_set_bus_width,
 792         .reset = esdhc_reset,
 793         .set_uhs_signaling = sdhci_set_uhs_signaling,
 794 };
 795
 796 static const struct sdhci_ops sdhci_esdhc_le_ops = {
 797         .read_l = esdhc_le_readl,
 798         .read_w = esdhc_le_readw,
 799         .read_b = esdhc_le_readb,
 800         .write_l = esdhc_le_writel,
 801         .write_w = esdhc_le_writew,
 802         .write_b = esdhc_le_writeb,
 803         .set_clock = esdhc_of_set_clock,
 804         .enable_dma = esdhc_of_enable_dma,
 805         .get_max_clock = esdhc_of_get_max_clock,
 806         .get_min_clock = esdhc_of_get_min_clock,
 807         .adma_workaround = esdhc_of_adma_workaround,
 808         .set_bus_width = esdhc_pltfm_set_bus_width,
 809         .reset = esdhc_reset,
 810         .set_uhs_signaling = sdhci_set_uhs_signaling,
 811 };
 812
 813 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
 814         .quirks = ESDHC_DEFAULT_QUIRKS |
 815 #ifdef CONFIG_PPC
 816                   SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 817 #endif
 818                   SDHCI_QUIRK_NO_CARD_NO_RESET |
 819                   SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 820         .ops = &sdhci_esdhc_be_ops,
 821 };
 822
 823 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
 824         .quirks = ESDHC_DEFAULT_QUIRKS |
 825                   SDHCI_QUIRK_NO_CARD_NO_RESET |
 826                   SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 827         .ops = &sdhci_esdhc_le_ops,
 828 };
 829
 830 static struct soc_device_attribute soc_incorrect_hostver[] = {
 831         { .family = "QorIQ T4240", .revision = "1.0", },
 832         { .family = "QorIQ T4240", .revision = "2.0", },
 833         { },
 834 };
 835
 836 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
 837 {
 838         const struct of_device_id *match;
 839         struct sdhci_pltfm_host *pltfm_host;
 840         struct sdhci_esdhc *esdhc;
 841         struct device_node *np;
 842         struct clk *clk;
 843         u32 val;
 844         u16 host_ver;
 845
 846         pltfm_host = sdhci_priv(host);
 847         esdhc = sdhci_pltfm_priv(pltfm_host);
 848
 849         host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
 850         esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
 851                              SDHCI_VENDOR_VER_SHIFT;
 852         esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
 853         if (soc_device_match(soc_incorrect_hostver))
 854                 esdhc->quirk_incorrect_hostver = true;
 855         else
 856                 esdhc->quirk_incorrect_hostver = false;
 857
 858         match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
 859         if (match)
 860                 esdhc->clk_fixup = match->data;
 861         np = pdev->dev.of_node;
 862         clk = of_clk_get(np, 0);
 863         if (!IS_ERR(clk)) {
 864                 /*
 865                  * esdhc->peripheral_clock would be assigned with a value
 866                  * which is eSDHC base clock when use periperal clock.
 867                  * For ls1046a, the clock value got by common clk API is
 868                  * peripheral clock while the eSDHC base clock is 1/2
 869                  * peripheral clock.
 870                  */
 871                 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
 872                         esdhc->peripheral_clock = clk_get_rate(clk) / 2;
 873                 else
 874                         esdhc->peripheral_clock = clk_get_rate(clk);
 875
 876                 clk_put(clk);
 877         }
 878
 879         if (esdhc->peripheral_clock) {
 880                 esdhc_clock_enable(host, false);
 881                 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
 882                 val |= ESDHC_PERIPHERAL_CLK_SEL;
 883                 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
 884                 esdhc_clock_enable(host, true);
 885         }
 886 }
 887
 888 static int sdhci_esdhc_probe(struct platform_device *pdev)
 889 {
 890         struct sdhci_host *host;
 891         struct device_node *np;
 892         struct sdhci_pltfm_host *pltfm_host;
 893         struct sdhci_esdhc *esdhc;
 894         int ret;
 895
 896         np = pdev->dev.of_node;
 897
 898         if (of_property_read_bool(np, "little-endian"))
 899                 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
 900                                         sizeof(struct sdhci_esdhc));
 901         else
 902                 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
 903                                         sizeof(struct sdhci_esdhc));
 904
 905         if (IS_ERR(host))
 906                 return PTR_ERR(host);
 907
 908         host->mmc_host_ops.start_signal_voltage_switch =
 909                 esdhc_signal_voltage_switch;
 910         host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
 911         host->tuning_delay = 1;
 912
 913         esdhc_init(pdev, host);
 914
 915         sdhci_get_of_property(pdev);
 916
 917         pltfm_host = sdhci_priv(host);
 918         esdhc = sdhci_pltfm_priv(pltfm_host);
 919         if (esdhc->vendor_ver == VENDOR_V_22)
 920                 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
 921
 922         if (esdhc->vendor_ver > VENDOR_V_22)
 923                 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
 924
 925         if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
 926                 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
 927                 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 928         }
 929
 930         if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
 931             of_device_is_compatible(np, "fsl,p5020-esdhc") ||
 932             of_device_is_compatible(np, "fsl,p4080-esdhc") ||
 933             of_device_is_compatible(np, "fsl,p1020-esdhc") ||
 934             of_device_is_compatible(np, "fsl,t1040-esdhc"))
 935                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 936
 937         if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
 938                 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 939
 940         if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
 941                 /*
 942                  * Freescale messed up with P2020 as it has a non-standard
 943                  * host control register
 944                  */
 945                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
 946         }
 947
 948         /* call to generic mmc_of_parse to support additional capabilities */
 949         ret = mmc_of_parse(host->mmc);
 950         if (ret)
 951                 goto err;
 952
 953         mmc_of_parse_voltage(np, &host->ocr_mask);
 954
 955         ret = sdhci_add_host(host);
 956         if (ret)
 957                 goto err;
 958
 959         return 0;
 960  err:
 961         sdhci_pltfm_free(pdev);
 962         return ret;
 963 }
 964
 965 static struct platform_driver sdhci_esdhc_driver = {
 966         .driver = {
 967                 .name = "sdhci-esdhc",
 968                 .of_match_table = sdhci_esdhc_of_match,
 969                 .pm = &esdhc_of_dev_pm_ops,
 970         },
 971         .probe = sdhci_esdhc_probe,
 972         .remove = sdhci_pltfm_unregister,
 973 };
 974
 975 module_platform_driver(sdhci_esdhc_driver);
 976
 977 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
 978 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
 979               "Anton Vorontsov <avorontsov@ru.mvista.com>");
 980 MODULE_LICENSE("GPL v2");