drivers/mmc/host/sdhci-pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __SDHCI_PCI_H
   3 #define __SDHCI_PCI_H
   4
   5 /*
   6  * PCI device IDs, sub IDs
   7  */
   8
   9 #define PCI_DEVICE_ID_O2_SDS0           0x8420
  10 #define PCI_DEVICE_ID_O2_SDS1           0x8421
  11 #define PCI_DEVICE_ID_O2_FUJIN2         0x8520
  12 #define PCI_DEVICE_ID_O2_SEABIRD0       0x8620
  13 #define PCI_DEVICE_ID_O2_SEABIRD1       0x8621
  14
  15 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0   0x8809
  16 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1   0x880a
  17 #define PCI_DEVICE_ID_INTEL_BYT_EMMC    0x0f14
  18 #define PCI_DEVICE_ID_INTEL_BYT_SDIO    0x0f15
  19 #define PCI_DEVICE_ID_INTEL_BYT_SD      0x0f16
  20 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2   0x0f50
  21 #define PCI_DEVICE_ID_INTEL_BSW_EMMC    0x2294
  22 #define PCI_DEVICE_ID_INTEL_BSW_SDIO    0x2295
  23 #define PCI_DEVICE_ID_INTEL_BSW_SD      0x2296
  24 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC   0x1190
  25 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0   0x08f9
  26 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1   0x08fa
  27 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2   0x08fb
  28 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0   0x08e5
  29 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1   0x08e6
  30 #define PCI_DEVICE_ID_INTEL_QRK_SD      0x08A7
  31 #define PCI_DEVICE_ID_INTEL_SPT_EMMC    0x9d2b
  32 #define PCI_DEVICE_ID_INTEL_SPT_SDIO    0x9d2c
  33 #define PCI_DEVICE_ID_INTEL_SPT_SD      0x9d2d
  34 #define PCI_DEVICE_ID_INTEL_DNV_EMMC    0x19db
  35 #define PCI_DEVICE_ID_INTEL_CDF_EMMC    0x18db
  36 #define PCI_DEVICE_ID_INTEL_BXT_SD      0x0aca
  37 #define PCI_DEVICE_ID_INTEL_BXT_EMMC    0x0acc
  38 #define PCI_DEVICE_ID_INTEL_BXT_SDIO    0x0ad0
  39 #define PCI_DEVICE_ID_INTEL_BXTM_SD     0x1aca
  40 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC   0x1acc
  41 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO   0x1ad0
  42 #define PCI_DEVICE_ID_INTEL_APL_SD      0x5aca
  43 #define PCI_DEVICE_ID_INTEL_APL_EMMC    0x5acc
  44 #define PCI_DEVICE_ID_INTEL_APL_SDIO    0x5ad0
  45 #define PCI_DEVICE_ID_INTEL_GLK_SD      0x31ca
  46 #define PCI_DEVICE_ID_INTEL_GLK_EMMC    0x31cc
  47 #define PCI_DEVICE_ID_INTEL_GLK_SDIO    0x31d0
  48 #define PCI_DEVICE_ID_INTEL_CNP_EMMC    0x9dc4
  49 #define PCI_DEVICE_ID_INTEL_CNP_SD      0x9df5
  50 #define PCI_DEVICE_ID_INTEL_CNPH_SD     0xa375
  51 #define PCI_DEVICE_ID_INTEL_ICP_EMMC    0x34c4
  52 #define PCI_DEVICE_ID_INTEL_ICP_SD      0x34f8
  53 #define PCI_DEVICE_ID_INTEL_CML_EMMC    0x02c4
  54 #define PCI_DEVICE_ID_INTEL_CML_SD      0x02f5
  55
  56 #define PCI_DEVICE_ID_SYSKONNECT_8000   0x8000
  57 #define PCI_DEVICE_ID_VIA_95D0          0x95d0
  58 #define PCI_DEVICE_ID_REALTEK_5250      0x5250
  59
  60 #define PCI_SUBDEVICE_ID_NI_7884        0x7884
  61 #define PCI_SUBDEVICE_ID_NI_78E3        0x78e3
  62
  63 #define PCI_VENDOR_ID_ARASAN            0x16e6
  64 #define PCI_DEVICE_ID_ARASAN_PHY_EMMC   0x0670
  65
  66 #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202
  67
  68 /*
  69  * PCI device class and mask
  70  */
  71
  72 #define SYSTEM_SDHCI                    (PCI_CLASS_SYSTEM_SDHCI << 8)
  73 #define PCI_CLASS_MASK                  0xFFFF00
  74
  75 /*
  76  * Macros for PCI device-description
  77  */
  78
  79 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
  80 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
  81 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
  82
  83 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
  84         .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
  85         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
  86         .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  87 }
  88
  89 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
  90         .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
  91         .subvendor = _PCI_VEND(subvend), \
  92         .subdevice = _PCI_SUBDEV(subvend, subdev), \
  93         .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  94 }
  95
  96 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
  97         .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
  98         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
  99         .class = (cl), .class_mask = (cl_msk), \
 100         .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
 101 }
 102
 103 /*
 104  * PCI registers
 105  */
 106
 107 #define PCI_SDHCI_IFPIO                 0x00
 108 #define PCI_SDHCI_IFDMA                 0x01
 109 #define PCI_SDHCI_IFVENDOR              0x02
 110
 111 #define PCI_SLOT_INFO                   0x40    /* 8 bits */
 112 #define  PCI_SLOT_INFO_SLOTS(x)         ((x >> 4) & 7)
 113 #define  PCI_SLOT_INFO_FIRST_BAR_MASK   0x07
 114
 115 #define MAX_SLOTS                       8
 116
 117 struct sdhci_pci_chip;
 118 struct sdhci_pci_slot;
 119
 120 struct sdhci_pci_fixes {
 121         unsigned int            quirks;
 122         unsigned int            quirks2;
 123         bool                    allow_runtime_pm;
 124         bool                    own_cd_for_runtime_pm;
 125
 126         int                     (*probe) (struct sdhci_pci_chip *);
 127
 128         int                     (*probe_slot) (struct sdhci_pci_slot *);
 129         int                     (*add_host) (struct sdhci_pci_slot *);
 130         void                    (*remove_slot) (struct sdhci_pci_slot *, int);
 131
 132 #ifdef CONFIG_PM_SLEEP
 133         int                     (*suspend) (struct sdhci_pci_chip *);
 134         int                     (*resume) (struct sdhci_pci_chip *);
 135 #endif
 136 #ifdef CONFIG_PM
 137         int                     (*runtime_suspend) (struct sdhci_pci_chip *);
 138         int                     (*runtime_resume) (struct sdhci_pci_chip *);
 139 #endif
 140
 141         const struct sdhci_ops  *ops;
 142         size_t                  priv_size;
 143 };
 144
 145 struct sdhci_pci_slot {
 146         struct sdhci_pci_chip   *chip;
 147         struct sdhci_host       *host;
 148         struct sdhci_pci_data   *data;
 149
 150         int                     rst_n_gpio;
 151         int                     cd_gpio;
 152         int                     cd_irq;
 153
 154         int                     cd_idx;
 155         bool                    cd_override_level;
 156
 157         void (*hw_reset)(struct sdhci_host *host);
 158         unsigned long           private[0] ____cacheline_aligned;
 159 };
 160
 161 struct sdhci_pci_chip {
 162         struct pci_dev          *pdev;
 163
 164         unsigned int            quirks;
 165         unsigned int            quirks2;
 166         bool                    allow_runtime_pm;
 167         bool                    pm_retune;
 168         bool                    rpm_retune;
 169         const struct sdhci_pci_fixes *fixes;
 170
 171         int                     num_slots;      /* Slots on controller */
 172         struct sdhci_pci_slot   *slots[MAX_SLOTS]; /* Pointers to host slots */
 173 };
 174
 175 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
 176 {
 177         return (void *)slot->private;
 178 }
 179
 180 #ifdef CONFIG_PM_SLEEP
 181 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
 182 #endif
 183 int sdhci_pci_enable_dma(struct sdhci_host *host);
 184 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
 185 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
 186 #ifdef CONFIG_PM_SLEEP
 187 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
 188 #endif
 189
 190 extern const struct sdhci_pci_fixes sdhci_arasan;
 191 extern const struct sdhci_pci_fixes sdhci_snps;
 192
 193 #endif /* __SDHCI_PCI_H */