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watchdog/core: Rename some softlockup_* functions
[linux/fpc-iii.git] / drivers / iommu / amd_iommu_init.c
blob382de42b835939e167604053060e9944e19131ba
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/kmemleak.h>
32 #include <linux/mem_encrypt.h>
33 #include <asm/pci-direct.h>
34 #include <asm/iommu.h>
35 #include <asm/gart.h>
36 #include <asm/x86_init.h>
37 #include <asm/iommu_table.h>
38 #include <asm/io_apic.h>
39 #include <asm/irq_remapping.h>
40
41 #include <linux/crash_dump.h>
42 #include "amd_iommu_proto.h"
43 #include "amd_iommu_types.h"
44 #include "irq_remapping.h"
45
46 /*
47 * definitions for the ACPI scanning code
48 */
49 #define IVRS_HEADER_LENGTH 48
50
51 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
52 #define ACPI_IVMD_TYPE_ALL 0x20
53 #define ACPI_IVMD_TYPE 0x21
54 #define ACPI_IVMD_TYPE_RANGE 0x22
55
56 #define IVHD_DEV_ALL 0x01
57 #define IVHD_DEV_SELECT 0x02
58 #define IVHD_DEV_SELECT_RANGE_START 0x03
59 #define IVHD_DEV_RANGE_END 0x04
60 #define IVHD_DEV_ALIAS 0x42
61 #define IVHD_DEV_ALIAS_RANGE 0x43
62 #define IVHD_DEV_EXT_SELECT 0x46
63 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
64 #define IVHD_DEV_SPECIAL 0x48
65 #define IVHD_DEV_ACPI_HID 0xf0
66
67 #define UID_NOT_PRESENT 0
68 #define UID_IS_INTEGER 1
69 #define UID_IS_CHARACTER 2
70
71 #define IVHD_SPECIAL_IOAPIC 1
72 #define IVHD_SPECIAL_HPET 2
73
74 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
75 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
76 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
77 #define IVHD_FLAG_ISOC_EN_MASK 0x08
78
79 #define IVMD_FLAG_EXCL_RANGE 0x08
80 #define IVMD_FLAG_UNITY_MAP 0x01
81
82 #define ACPI_DEVFLAG_INITPASS 0x01
83 #define ACPI_DEVFLAG_EXTINT 0x02
84 #define ACPI_DEVFLAG_NMI 0x04
85 #define ACPI_DEVFLAG_SYSMGT1 0x10
86 #define ACPI_DEVFLAG_SYSMGT2 0x20
87 #define ACPI_DEVFLAG_LINT0 0x40
88 #define ACPI_DEVFLAG_LINT1 0x80
89 #define ACPI_DEVFLAG_ATSDIS 0x10000000
90
91 #define LOOP_TIMEOUT 100000
92 /*
93 * ACPI table definitions
94 *
95 * These data structures are laid over the table to parse the important values
96 * out of it.
97 */
98
99 extern const struct iommu_ops amd_iommu_ops;
100
101 /*
102 * structure describing one IOMMU in the ACPI table. Typically followed by one
103 * or more ivhd_entrys.
104 */
105 struct ivhd_header {
106 u8 type;
107 u8 flags;
108 u16 length;
109 u16 devid;
110 u16 cap_ptr;
111 u64 mmio_phys;
112 u16 pci_seg;
113 u16 info;
114 u32 efr_attr;
115
116 /* Following only valid on IVHD type 11h and 40h */
117 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
118 u64 res;
119 } __attribute__((packed));
120
121 /*
122 * A device entry describing which devices a specific IOMMU translates and
123 * which requestor ids they use.
124 */
125 struct ivhd_entry {
126 u8 type;
127 u16 devid;
128 u8 flags;
129 u32 ext;
130 u32 hidh;
131 u64 cid;
132 u8 uidf;
133 u8 uidl;
134 u8 uid;
135 } __attribute__((packed));
136
137 /*
138 * An AMD IOMMU memory definition structure. It defines things like exclusion
139 * ranges for devices and regions that should be unity mapped.
140 */
141 struct ivmd_header {
142 u8 type;
143 u8 flags;
144 u16 length;
145 u16 devid;
146 u16 aux;
147 u64 resv;
148 u64 range_start;
149 u64 range_length;
150 } __attribute__((packed));
151
152 bool amd_iommu_dump;
153 bool amd_iommu_irq_remap __read_mostly;
154
155 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
156
157 static bool amd_iommu_detected;
158 static bool __initdata amd_iommu_disabled;
159 static int amd_iommu_target_ivhd_type;
160
161 u16 amd_iommu_last_bdf; /* largest PCI device id we have
162 to handle */
163 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
164 we find in ACPI */
165 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
166
167 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
168 system */
169
170 /* Array to assign indices to IOMMUs*/
171 struct amd_iommu *amd_iommus[MAX_IOMMUS];
172
173 /* Number of IOMMUs present in the system */
174 static int amd_iommus_present;
175
176 /* IOMMUs have a non-present cache? */
177 bool amd_iommu_np_cache __read_mostly;
178 bool amd_iommu_iotlb_sup __read_mostly = true;
179
180 u32 amd_iommu_max_pasid __read_mostly = ~0;
181
182 bool amd_iommu_v2_present __read_mostly;
183 static bool amd_iommu_pc_present __read_mostly;
184
185 bool amd_iommu_force_isolation __read_mostly;
186
187 /*
188 * List of protection domains - used during resume
189 */
190 LIST_HEAD(amd_iommu_pd_list);
191 spinlock_t amd_iommu_pd_lock;
192
193 /*
194 * Pointer to the device table which is shared by all AMD IOMMUs
195 * it is indexed by the PCI device id or the HT unit id and contains
196 * information about the domain the device belongs to as well as the
197 * page table root pointer.
198 */
199 struct dev_table_entry *amd_iommu_dev_table;
200 /*
201 * Pointer to a device table which the content of old device table
202 * will be copied to. It's only be used in kdump kernel.
203 */
204 static struct dev_table_entry *old_dev_tbl_cpy;
205
206 /*
207 * The alias table is a driver specific data structure which contains the
208 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
209 * More than one device can share the same requestor id.
210 */
211 u16 *amd_iommu_alias_table;
212
213 /*
214 * The rlookup table is used to find the IOMMU which is responsible
215 * for a specific device. It is also indexed by the PCI device id.
216 */
217 struct amd_iommu **amd_iommu_rlookup_table;
218 EXPORT_SYMBOL(amd_iommu_rlookup_table);
219
220 /*
221 * This table is used to find the irq remapping table for a given device id
222 * quickly.
223 */
224 struct irq_remap_table **irq_lookup_table;
225
226 /*
227 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
228 * to know which ones are already in use.
229 */
230 unsigned long *amd_iommu_pd_alloc_bitmap;
231
232 static u32 dev_table_size; /* size of the device table */
233 static u32 alias_table_size; /* size of the alias table */
234 static u32 rlookup_table_size; /* size if the rlookup table */
235
236 enum iommu_init_state {
237 IOMMU_START_STATE,
238 IOMMU_IVRS_DETECTED,
239 IOMMU_ACPI_FINISHED,
240 IOMMU_ENABLED,
241 IOMMU_PCI_INIT,
242 IOMMU_INTERRUPTS_EN,
243 IOMMU_DMA_OPS,
244 IOMMU_INITIALIZED,
245 IOMMU_NOT_FOUND,
246 IOMMU_INIT_ERROR,
247 IOMMU_CMDLINE_DISABLED,
248 };
249
250 /* Early ioapic and hpet maps from kernel command line */
251 #define EARLY_MAP_SIZE 4
252 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
253 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
254 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
255
256 static int __initdata early_ioapic_map_size;
257 static int __initdata early_hpet_map_size;
258 static int __initdata early_acpihid_map_size;
259
260 static bool __initdata cmdline_maps;
261
262 static enum iommu_init_state init_state = IOMMU_START_STATE;
263
264 static int amd_iommu_enable_interrupts(void);
265 static int __init iommu_go_to_state(enum iommu_init_state state);
266 static void init_device_table_dma(void);
267
268 static bool amd_iommu_pre_enabled = true;
269
270 bool translation_pre_enabled(struct amd_iommu *iommu)
271 {
272 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
273 }
274 EXPORT_SYMBOL(translation_pre_enabled);
275
276 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
277 {
278 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
279 }
280
281 static void init_translation_status(struct amd_iommu *iommu)
282 {
283 u32 ctrl;
284
285 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
286 if (ctrl & (1<<CONTROL_IOMMU_EN))
287 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
288 }
289
290 static inline void update_last_devid(u16 devid)
291 {
292 if (devid > amd_iommu_last_bdf)
293 amd_iommu_last_bdf = devid;
294 }
295
296 static inline unsigned long tbl_size(int entry_size)
297 {
298 unsigned shift = PAGE_SHIFT +
299 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
300
301 return 1UL << shift;
302 }
303
304 int amd_iommu_get_num_iommus(void)
305 {
306 return amd_iommus_present;
307 }
308
309 /* Access to l1 and l2 indexed register spaces */
310
311 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
312 {
313 u32 val;
314
315 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
316 pci_read_config_dword(iommu->dev, 0xfc, &val);
317 return val;
318 }
319
320 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
321 {
322 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
323 pci_write_config_dword(iommu->dev, 0xfc, val);
324 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
325 }
326
327 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
328 {
329 u32 val;
330
331 pci_write_config_dword(iommu->dev, 0xf0, address);
332 pci_read_config_dword(iommu->dev, 0xf4, &val);
333 return val;
334 }
335
336 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
337 {
338 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
339 pci_write_config_dword(iommu->dev, 0xf4, val);
340 }
341
342 /****************************************************************************
343 *
344 * AMD IOMMU MMIO register space handling functions
345 *
346 * These functions are used to program the IOMMU device registers in
347 * MMIO space required for that driver.
348 *
349 ****************************************************************************/
350
351 /*
352 * This function set the exclusion range in the IOMMU. DMA accesses to the
353 * exclusion range are passed through untranslated
354 */
355 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
356 {
357 u64 start = iommu->exclusion_start & PAGE_MASK;
358 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
359 u64 entry;
360
361 if (!iommu->exclusion_start)
362 return;
363
364 entry = start | MMIO_EXCL_ENABLE_MASK;
365 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
366 &entry, sizeof(entry));
367
368 entry = limit;
369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
370 &entry, sizeof(entry));
371 }
372
373 /* Programs the physical address of the device table into the IOMMU hardware */
374 static void iommu_set_device_table(struct amd_iommu *iommu)
375 {
376 u64 entry;
377
378 BUG_ON(iommu->mmio_base == NULL);
379
380 entry = iommu_virt_to_phys(amd_iommu_dev_table);
381 entry |= (dev_table_size >> 12) - 1;
382 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
383 &entry, sizeof(entry));
384 }
385
386 /* Generic functions to enable/disable certain features of the IOMMU. */
387 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
388 {
389 u32 ctrl;
390
391 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
392 ctrl |= (1 << bit);
393 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
394 }
395
396 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
397 {
398 u32 ctrl;
399
400 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
401 ctrl &= ~(1 << bit);
402 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
403 }
404
405 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
406 {
407 u32 ctrl;
408
409 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
410 ctrl &= ~CTRL_INV_TO_MASK;
411 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
412 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
413 }
414
415 /* Function to enable the hardware */
416 static void iommu_enable(struct amd_iommu *iommu)
417 {
418 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
419 }
420
421 static void iommu_disable(struct amd_iommu *iommu)
422 {
423 /* Disable command buffer */
424 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
425
426 /* Disable event logging and event interrupts */
427 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
428 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
429
430 /* Disable IOMMU GA_LOG */
431 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
432 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
433
434 /* Disable IOMMU hardware itself */
435 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
436 }
437
438 /*
439 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
440 * the system has one.
441 */
442 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
443 {
444 if (!request_mem_region(address, end, "amd_iommu")) {
445 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
446 address, end);
447 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
448 return NULL;
449 }
450
451 return (u8 __iomem *)ioremap_nocache(address, end);
452 }
453
454 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
455 {
456 if (iommu->mmio_base)
457 iounmap(iommu->mmio_base);
458 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
459 }
460
461 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
462 {
463 u32 size = 0;
464
465 switch (h->type) {
466 case 0x10:
467 size = 24;
468 break;
469 case 0x11:
470 case 0x40:
471 size = 40;
472 break;
473 }
474 return size;
475 }
476
477 /****************************************************************************
478 *
479 * The functions below belong to the first pass of AMD IOMMU ACPI table
480 * parsing. In this pass we try to find out the highest device id this
481 * code has to handle. Upon this information the size of the shared data
482 * structures is determined later.
483 *
484 ****************************************************************************/
485
486 /*
487 * This function calculates the length of a given IVHD entry
488 */
489 static inline int ivhd_entry_length(u8 *ivhd)
490 {
491 u32 type = ((struct ivhd_entry *)ivhd)->type;
492
493 if (type < 0x80) {
494 return 0x04 << (*ivhd >> 6);
495 } else if (type == IVHD_DEV_ACPI_HID) {
496 /* For ACPI_HID, offset 21 is uid len */
497 return *((u8 *)ivhd + 21) + 22;
498 }
499 return 0;
500 }
501
502 /*
503 * After reading the highest device id from the IOMMU PCI capability header
504 * this function looks if there is a higher device id defined in the ACPI table
505 */
506 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
507 {
508 u8 *p = (void *)h, *end = (void *)h;
509 struct ivhd_entry *dev;
510
511 u32 ivhd_size = get_ivhd_header_size(h);
512
513 if (!ivhd_size) {
514 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
515 return -EINVAL;
516 }
517
518 p += ivhd_size;
519 end += h->length;
520
521 while (p < end) {
522 dev = (struct ivhd_entry *)p;
523 switch (dev->type) {
524 case IVHD_DEV_ALL:
525 /* Use maximum BDF value for DEV_ALL */
526 update_last_devid(0xffff);
527 break;
528 case IVHD_DEV_SELECT:
529 case IVHD_DEV_RANGE_END:
530 case IVHD_DEV_ALIAS:
531 case IVHD_DEV_EXT_SELECT:
532 /* all the above subfield types refer to device ids */
533 update_last_devid(dev->devid);
534 break;
535 default:
536 break;
537 }
538 p += ivhd_entry_length(p);
539 }
540
541 WARN_ON(p != end);
542
543 return 0;
544 }
545
546 static int __init check_ivrs_checksum(struct acpi_table_header *table)
547 {
548 int i;
549 u8 checksum = 0, *p = (u8 *)table;
550
551 for (i = 0; i < table->length; ++i)
552 checksum += p[i];
553 if (checksum != 0) {
554 /* ACPI table corrupt */
555 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
556 return -ENODEV;
557 }
558
559 return 0;
560 }
561
562 /*
563 * Iterate over all IVHD entries in the ACPI table and find the highest device
564 * id which we need to handle. This is the first of three functions which parse
565 * the ACPI table. So we check the checksum here.
566 */
567 static int __init find_last_devid_acpi(struct acpi_table_header *table)
568 {
569 u8 *p = (u8 *)table, *end = (u8 *)table;
570 struct ivhd_header *h;
571
572 p += IVRS_HEADER_LENGTH;
573
574 end += table->length;
575 while (p < end) {
576 h = (struct ivhd_header *)p;
577 if (h->type == amd_iommu_target_ivhd_type) {
578 int ret = find_last_devid_from_ivhd(h);
579
580 if (ret)
581 return ret;
582 }
583 p += h->length;
584 }
585 WARN_ON(p != end);
586
587 return 0;
588 }
589
590 /****************************************************************************
591 *
592 * The following functions belong to the code path which parses the ACPI table
593 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
594 * data structures, initialize the device/alias/rlookup table and also
595 * basically initialize the hardware.
596 *
597 ****************************************************************************/
598
599 /*
600 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
601 * write commands to that buffer later and the IOMMU will execute them
602 * asynchronously
603 */
604 static int __init alloc_command_buffer(struct amd_iommu *iommu)
605 {
606 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
607 get_order(CMD_BUFFER_SIZE));
608
609 return iommu->cmd_buf ? 0 : -ENOMEM;
610 }
611
612 /*
613 * This function resets the command buffer if the IOMMU stopped fetching
614 * commands from it.
615 */
616 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
617 {
618 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
619
620 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
621 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
622 iommu->cmd_buf_head = 0;
623 iommu->cmd_buf_tail = 0;
624
625 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
626 }
627
628 /*
629 * This function writes the command buffer address to the hardware and
630 * enables it.
631 */
632 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
633 {
634 u64 entry;
635
636 BUG_ON(iommu->cmd_buf == NULL);
637
638 entry = iommu_virt_to_phys(iommu->cmd_buf);
639 entry |= MMIO_CMD_SIZE_512;
640
641 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
642 &entry, sizeof(entry));
643
644 amd_iommu_reset_cmd_buffer(iommu);
645 }
646
647 /*
648 * This function disables the command buffer
649 */
650 static void iommu_disable_command_buffer(struct amd_iommu *iommu)
651 {
652 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
653 }
654
655 static void __init free_command_buffer(struct amd_iommu *iommu)
656 {
657 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
658 }
659
660 /* allocates the memory where the IOMMU will log its events to */
661 static int __init alloc_event_buffer(struct amd_iommu *iommu)
662 {
663 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
664 get_order(EVT_BUFFER_SIZE));
665
666 return iommu->evt_buf ? 0 : -ENOMEM;
667 }
668
669 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
670 {
671 u64 entry;
672
673 BUG_ON(iommu->evt_buf == NULL);
674
675 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
676
677 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
678 &entry, sizeof(entry));
679
680 /* set head and tail to zero manually */
681 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
682 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
683
684 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
685 }
686
687 /*
688 * This function disables the event log buffer
689 */
690 static void iommu_disable_event_buffer(struct amd_iommu *iommu)
691 {
692 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
693 }
694
695 static void __init free_event_buffer(struct amd_iommu *iommu)
696 {
697 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
698 }
699
700 /* allocates the memory where the IOMMU will log its events to */
701 static int __init alloc_ppr_log(struct amd_iommu *iommu)
702 {
703 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
704 get_order(PPR_LOG_SIZE));
705
706 return iommu->ppr_log ? 0 : -ENOMEM;
707 }
708
709 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
710 {
711 u64 entry;
712
713 if (iommu->ppr_log == NULL)
714 return;
715
716 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
717
718 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
719 &entry, sizeof(entry));
720
721 /* set head and tail to zero manually */
722 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
723 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
724
725 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
726 iommu_feature_enable(iommu, CONTROL_PPR_EN);
727 }
728
729 static void __init free_ppr_log(struct amd_iommu *iommu)
730 {
731 if (iommu->ppr_log == NULL)
732 return;
733
734 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
735 }
736
737 static void free_ga_log(struct amd_iommu *iommu)
738 {
739 #ifdef CONFIG_IRQ_REMAP
740 if (iommu->ga_log)
741 free_pages((unsigned long)iommu->ga_log,
742 get_order(GA_LOG_SIZE));
743 if (iommu->ga_log_tail)
744 free_pages((unsigned long)iommu->ga_log_tail,
745 get_order(8));
746 #endif
747 }
748
749 static int iommu_ga_log_enable(struct amd_iommu *iommu)
750 {
751 #ifdef CONFIG_IRQ_REMAP
752 u32 status, i;
753
754 if (!iommu->ga_log)
755 return -EINVAL;
756
757 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
758
759 /* Check if already running */
760 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
761 return 0;
762
763 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
764 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
765
766 for (i = 0; i < LOOP_TIMEOUT; ++i) {
767 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
768 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
769 break;
770 }
771
772 if (i >= LOOP_TIMEOUT)
773 return -EINVAL;
774 #endif /* CONFIG_IRQ_REMAP */
775 return 0;
776 }
777
778 #ifdef CONFIG_IRQ_REMAP
779 static int iommu_init_ga_log(struct amd_iommu *iommu)
780 {
781 u64 entry;
782
783 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
784 return 0;
785
786 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
787 get_order(GA_LOG_SIZE));
788 if (!iommu->ga_log)
789 goto err_out;
790
791 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
792 get_order(8));
793 if (!iommu->ga_log_tail)
794 goto err_out;
795
796 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
797 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
798 &entry, sizeof(entry));
799 entry = (iommu_virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
800 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
801 &entry, sizeof(entry));
802 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
803 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
804
805 return 0;
806 err_out:
807 free_ga_log(iommu);
808 return -EINVAL;
809 }
810 #endif /* CONFIG_IRQ_REMAP */
811
812 static int iommu_init_ga(struct amd_iommu *iommu)
813 {
814 int ret = 0;
815
816 #ifdef CONFIG_IRQ_REMAP
817 /* Note: We have already checked GASup from IVRS table.
818 * Now, we need to make sure that GAMSup is set.
819 */
820 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
821 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
822 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
823
824 ret = iommu_init_ga_log(iommu);
825 #endif /* CONFIG_IRQ_REMAP */
826
827 return ret;
828 }
829
830 static void iommu_enable_gt(struct amd_iommu *iommu)
831 {
832 if (!iommu_feature(iommu, FEATURE_GT))
833 return;
834
835 iommu_feature_enable(iommu, CONTROL_GT_EN);
836 }
837
838 /* sets a specific bit in the device table entry. */
839 static void set_dev_entry_bit(u16 devid, u8 bit)
840 {
841 int i = (bit >> 6) & 0x03;
842 int _bit = bit & 0x3f;
843
844 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
845 }
846
847 static int get_dev_entry_bit(u16 devid, u8 bit)
848 {
849 int i = (bit >> 6) & 0x03;
850 int _bit = bit & 0x3f;
851
852 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
853 }
854
855
856 static bool copy_device_table(void)
857 {
858 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
859 struct dev_table_entry *old_devtb = NULL;
860 u32 lo, hi, devid, old_devtb_size;
861 phys_addr_t old_devtb_phys;
862 struct amd_iommu *iommu;
863 u16 dom_id, dte_v, irq_v;
864 gfp_t gfp_flag;
865 u64 tmp;
866
867 if (!amd_iommu_pre_enabled)
868 return false;
869
870 pr_warn("Translation is already enabled - trying to copy translation structures\n");
871 for_each_iommu(iommu) {
872 /* All IOMMUs should use the same device table with the same size */
873 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
874 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
875 entry = (((u64) hi) << 32) + lo;
876 if (last_entry && last_entry != entry) {
877 pr_err("IOMMU:%d should use the same dev table as others!/n",
878 iommu->index);
879 return false;
880 }
881 last_entry = entry;
882
883 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
884 if (old_devtb_size != dev_table_size) {
885 pr_err("The device table size of IOMMU:%d is not expected!/n",
886 iommu->index);
887 return false;
888 }
889 }
890
891 old_devtb_phys = entry & PAGE_MASK;
892 if (old_devtb_phys >= 0x100000000ULL) {
893 pr_err("The address of old device table is above 4G, not trustworthy!/n");
894 return false;
895 }
896 old_devtb = memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
897 if (!old_devtb)
898 return false;
899
900 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
901 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
902 get_order(dev_table_size));
903 if (old_dev_tbl_cpy == NULL) {
904 pr_err("Failed to allocate memory for copying old device table!/n");
905 return false;
906 }
907
908 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
909 old_dev_tbl_cpy[devid] = old_devtb[devid];
910 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
911 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
912
913 if (dte_v && dom_id) {
914 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
915 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
916 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
917 /* If gcr3 table existed, mask it out */
918 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
919 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
920 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
921 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
922 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
923 tmp |= DTE_FLAG_GV;
924 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
925 }
926 }
927
928 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
929 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
930 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
931 if (irq_v && (int_ctl || int_tab_len)) {
932 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
933 (int_tab_len != DTE_IRQ_TABLE_LEN)) {
934 pr_err("Wrong old irq remapping flag: %#x\n", devid);
935 return false;
936 }
937
938 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
939 }
940 }
941 memunmap(old_devtb);
942
943 return true;
944 }
945
946 void amd_iommu_apply_erratum_63(u16 devid)
947 {
948 int sysmgt;
949
950 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
951 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
952
953 if (sysmgt == 0x01)
954 set_dev_entry_bit(devid, DEV_ENTRY_IW);
955 }
956
957 /* Writes the specific IOMMU for a device into the rlookup table */
958 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
959 {
960 amd_iommu_rlookup_table[devid] = iommu;
961 }
962
963 /*
964 * This function takes the device specific flags read from the ACPI
965 * table and sets up the device table entry with that information
966 */
967 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
968 u16 devid, u32 flags, u32 ext_flags)
969 {
970 if (flags & ACPI_DEVFLAG_INITPASS)
971 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
972 if (flags & ACPI_DEVFLAG_EXTINT)
973 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
974 if (flags & ACPI_DEVFLAG_NMI)
975 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
976 if (flags & ACPI_DEVFLAG_SYSMGT1)
977 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
978 if (flags & ACPI_DEVFLAG_SYSMGT2)
979 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
980 if (flags & ACPI_DEVFLAG_LINT0)
981 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
982 if (flags & ACPI_DEVFLAG_LINT1)
983 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
984
985 amd_iommu_apply_erratum_63(devid);
986
987 set_iommu_for_device(iommu, devid);
988 }
989
990 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
991 {
992 struct devid_map *entry;
993 struct list_head *list;
994
995 if (type == IVHD_SPECIAL_IOAPIC)
996 list = &ioapic_map;
997 else if (type == IVHD_SPECIAL_HPET)
998 list = &hpet_map;
999 else
1000 return -EINVAL;
1001
1002 list_for_each_entry(entry, list, list) {
1003 if (!(entry->id == id && entry->cmd_line))
1004 continue;
1005
1006 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
1007 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1008
1009 *devid = entry->devid;
1010
1011 return 0;
1012 }
1013
1014 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1015 if (!entry)
1016 return -ENOMEM;
1017
1018 entry->id = id;
1019 entry->devid = *devid;
1020 entry->cmd_line = cmd_line;
1021
1022 list_add_tail(&entry->list, list);
1023
1024 return 0;
1025 }
1026
1027 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1028 bool cmd_line)
1029 {
1030 struct acpihid_map_entry *entry;
1031 struct list_head *list = &acpihid_map;
1032
1033 list_for_each_entry(entry, list, list) {
1034 if (strcmp(entry->hid, hid) ||
1035 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1036 !entry->cmd_line)
1037 continue;
1038
1039 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
1040 hid, uid);
1041 *devid = entry->devid;
1042 return 0;
1043 }
1044
1045 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1046 if (!entry)
1047 return -ENOMEM;
1048
1049 memcpy(entry->uid, uid, strlen(uid));
1050 memcpy(entry->hid, hid, strlen(hid));
1051 entry->devid = *devid;
1052 entry->cmd_line = cmd_line;
1053 entry->root_devid = (entry->devid & (~0x7));
1054
1055 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
1056 entry->cmd_line ? "cmd" : "ivrs",
1057 entry->hid, entry->uid, entry->root_devid);
1058
1059 list_add_tail(&entry->list, list);
1060 return 0;
1061 }
1062
1063 static int __init add_early_maps(void)
1064 {
1065 int i, ret;
1066
1067 for (i = 0; i < early_ioapic_map_size; ++i) {
1068 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1069 early_ioapic_map[i].id,
1070 &early_ioapic_map[i].devid,
1071 early_ioapic_map[i].cmd_line);
1072 if (ret)
1073 return ret;
1074 }
1075
1076 for (i = 0; i < early_hpet_map_size; ++i) {
1077 ret = add_special_device(IVHD_SPECIAL_HPET,
1078 early_hpet_map[i].id,
1079 &early_hpet_map[i].devid,
1080 early_hpet_map[i].cmd_line);
1081 if (ret)
1082 return ret;
1083 }
1084
1085 for (i = 0; i < early_acpihid_map_size; ++i) {
1086 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1087 early_acpihid_map[i].uid,
1088 &early_acpihid_map[i].devid,
1089 early_acpihid_map[i].cmd_line);
1090 if (ret)
1091 return ret;
1092 }
1093
1094 return 0;
1095 }
1096
1097 /*
1098 * Reads the device exclusion range from ACPI and initializes the IOMMU with
1099 * it
1100 */
1101 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
1102 {
1103 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1104
1105 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
1106 return;
1107
1108 if (iommu) {
1109 /*
1110 * We only can configure exclusion ranges per IOMMU, not
1111 * per device. But we can enable the exclusion range per
1112 * device. This is done here
1113 */
1114 set_dev_entry_bit(devid, DEV_ENTRY_EX);
1115 iommu->exclusion_start = m->range_start;
1116 iommu->exclusion_length = m->range_length;
1117 }
1118 }
1119
1120 /*
1121 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1122 * initializes the hardware and our data structures with it.
1123 */
1124 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1125 struct ivhd_header *h)
1126 {
1127 u8 *p = (u8 *)h;
1128 u8 *end = p, flags = 0;
1129 u16 devid = 0, devid_start = 0, devid_to = 0;
1130 u32 dev_i, ext_flags = 0;
1131 bool alias = false;
1132 struct ivhd_entry *e;
1133 u32 ivhd_size;
1134 int ret;
1135
1136
1137 ret = add_early_maps();
1138 if (ret)
1139 return ret;
1140
1141 /*
1142 * First save the recommended feature enable bits from ACPI
1143 */
1144 iommu->acpi_flags = h->flags;
1145
1146 /*
1147 * Done. Now parse the device entries
1148 */
1149 ivhd_size = get_ivhd_header_size(h);
1150 if (!ivhd_size) {
1151 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1152 return -EINVAL;
1153 }
1154
1155 p += ivhd_size;
1156
1157 end += h->length;
1158
1159
1160 while (p < end) {
1161 e = (struct ivhd_entry *)p;
1162 switch (e->type) {
1163 case IVHD_DEV_ALL:
1164
1165 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1166
1167 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1168 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1169 break;
1170 case IVHD_DEV_SELECT:
1171
1172 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1173 "flags: %02x\n",
1174 PCI_BUS_NUM(e->devid),
1175 PCI_SLOT(e->devid),
1176 PCI_FUNC(e->devid),
1177 e->flags);
1178
1179 devid = e->devid;
1180 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1181 break;
1182 case IVHD_DEV_SELECT_RANGE_START:
1183
1184 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1185 "devid: %02x:%02x.%x flags: %02x\n",
1186 PCI_BUS_NUM(e->devid),
1187 PCI_SLOT(e->devid),
1188 PCI_FUNC(e->devid),
1189 e->flags);
1190
1191 devid_start = e->devid;
1192 flags = e->flags;
1193 ext_flags = 0;
1194 alias = false;
1195 break;
1196 case IVHD_DEV_ALIAS:
1197
1198 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1199 "flags: %02x devid_to: %02x:%02x.%x\n",
1200 PCI_BUS_NUM(e->devid),
1201 PCI_SLOT(e->devid),
1202 PCI_FUNC(e->devid),
1203 e->flags,
1204 PCI_BUS_NUM(e->ext >> 8),
1205 PCI_SLOT(e->ext >> 8),
1206 PCI_FUNC(e->ext >> 8));
1207
1208 devid = e->devid;
1209 devid_to = e->ext >> 8;
1210 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1211 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1212 amd_iommu_alias_table[devid] = devid_to;
1213 break;
1214 case IVHD_DEV_ALIAS_RANGE:
1215
1216 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1217 "devid: %02x:%02x.%x flags: %02x "
1218 "devid_to: %02x:%02x.%x\n",
1219 PCI_BUS_NUM(e->devid),
1220 PCI_SLOT(e->devid),
1221 PCI_FUNC(e->devid),
1222 e->flags,
1223 PCI_BUS_NUM(e->ext >> 8),
1224 PCI_SLOT(e->ext >> 8),
1225 PCI_FUNC(e->ext >> 8));
1226
1227 devid_start = e->devid;
1228 flags = e->flags;
1229 devid_to = e->ext >> 8;
1230 ext_flags = 0;
1231 alias = true;
1232 break;
1233 case IVHD_DEV_EXT_SELECT:
1234
1235 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1236 "flags: %02x ext: %08x\n",
1237 PCI_BUS_NUM(e->devid),
1238 PCI_SLOT(e->devid),
1239 PCI_FUNC(e->devid),
1240 e->flags, e->ext);
1241
1242 devid = e->devid;
1243 set_dev_entry_from_acpi(iommu, devid, e->flags,
1244 e->ext);
1245 break;
1246 case IVHD_DEV_EXT_SELECT_RANGE:
1247
1248 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1249 "%02x:%02x.%x flags: %02x ext: %08x\n",
1250 PCI_BUS_NUM(e->devid),
1251 PCI_SLOT(e->devid),
1252 PCI_FUNC(e->devid),
1253 e->flags, e->ext);
1254
1255 devid_start = e->devid;
1256 flags = e->flags;
1257 ext_flags = e->ext;
1258 alias = false;
1259 break;
1260 case IVHD_DEV_RANGE_END:
1261
1262 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1263 PCI_BUS_NUM(e->devid),
1264 PCI_SLOT(e->devid),
1265 PCI_FUNC(e->devid));
1266
1267 devid = e->devid;
1268 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1269 if (alias) {
1270 amd_iommu_alias_table[dev_i] = devid_to;
1271 set_dev_entry_from_acpi(iommu,
1272 devid_to, flags, ext_flags);
1273 }
1274 set_dev_entry_from_acpi(iommu, dev_i,
1275 flags, ext_flags);
1276 }
1277 break;
1278 case IVHD_DEV_SPECIAL: {
1279 u8 handle, type;
1280 const char *var;
1281 u16 devid;
1282 int ret;
1283
1284 handle = e->ext & 0xff;
1285 devid = (e->ext >> 8) & 0xffff;
1286 type = (e->ext >> 24) & 0xff;
1287
1288 if (type == IVHD_SPECIAL_IOAPIC)
1289 var = "IOAPIC";
1290 else if (type == IVHD_SPECIAL_HPET)
1291 var = "HPET";
1292 else
1293 var = "UNKNOWN";
1294
1295 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1296 var, (int)handle,
1297 PCI_BUS_NUM(devid),
1298 PCI_SLOT(devid),
1299 PCI_FUNC(devid));
1300
1301 ret = add_special_device(type, handle, &devid, false);
1302 if (ret)
1303 return ret;
1304
1305 /*
1306 * add_special_device might update the devid in case a
1307 * command-line override is present. So call
1308 * set_dev_entry_from_acpi after add_special_device.
1309 */
1310 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1311
1312 break;
1313 }
1314 case IVHD_DEV_ACPI_HID: {
1315 u16 devid;
1316 u8 hid[ACPIHID_HID_LEN] = {0};
1317 u8 uid[ACPIHID_UID_LEN] = {0};
1318 int ret;
1319
1320 if (h->type != 0x40) {
1321 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1322 e->type);
1323 break;
1324 }
1325
1326 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1327 hid[ACPIHID_HID_LEN - 1] = '\0';
1328
1329 if (!(*hid)) {
1330 pr_err(FW_BUG "Invalid HID.\n");
1331 break;
1332 }
1333
1334 switch (e->uidf) {
1335 case UID_NOT_PRESENT:
1336
1337 if (e->uidl != 0)
1338 pr_warn(FW_BUG "Invalid UID length.\n");
1339
1340 break;
1341 case UID_IS_INTEGER:
1342
1343 sprintf(uid, "%d", e->uid);
1344
1345 break;
1346 case UID_IS_CHARACTER:
1347
1348 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1349 uid[ACPIHID_UID_LEN - 1] = '\0';
1350
1351 break;
1352 default:
1353 break;
1354 }
1355
1356 devid = e->devid;
1357 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1358 hid, uid,
1359 PCI_BUS_NUM(devid),
1360 PCI_SLOT(devid),
1361 PCI_FUNC(devid));
1362
1363 flags = e->flags;
1364
1365 ret = add_acpi_hid_device(hid, uid, &devid, false);
1366 if (ret)
1367 return ret;
1368
1369 /*
1370 * add_special_device might update the devid in case a
1371 * command-line override is present. So call
1372 * set_dev_entry_from_acpi after add_special_device.
1373 */
1374 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1375
1376 break;
1377 }
1378 default:
1379 break;
1380 }
1381
1382 p += ivhd_entry_length(p);
1383 }
1384
1385 return 0;
1386 }
1387
1388 static void __init free_iommu_one(struct amd_iommu *iommu)
1389 {
1390 free_command_buffer(iommu);
1391 free_event_buffer(iommu);
1392 free_ppr_log(iommu);
1393 free_ga_log(iommu);
1394 iommu_unmap_mmio_space(iommu);
1395 }
1396
1397 static void __init free_iommu_all(void)
1398 {
1399 struct amd_iommu *iommu, *next;
1400
1401 for_each_iommu_safe(iommu, next) {
1402 list_del(&iommu->list);
1403 free_iommu_one(iommu);
1404 kfree(iommu);
1405 }
1406 }
1407
1408 /*
1409 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1410 * Workaround:
1411 * BIOS should disable L2B micellaneous clock gating by setting
1412 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1413 */
1414 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1415 {
1416 u32 value;
1417
1418 if ((boot_cpu_data.x86 != 0x15) ||
1419 (boot_cpu_data.x86_model < 0x10) ||
1420 (boot_cpu_data.x86_model > 0x1f))
1421 return;
1422
1423 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1424 pci_read_config_dword(iommu->dev, 0xf4, &value);
1425
1426 if (value & BIT(2))
1427 return;
1428
1429 /* Select NB indirect register 0x90 and enable writing */
1430 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1431
1432 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1433 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1434 dev_name(&iommu->dev->dev));
1435
1436 /* Clear the enable writing bit */
1437 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1438 }
1439
1440 /*
1441 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1442 * Workaround:
1443 * BIOS should enable ATS write permission check by setting
1444 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1445 */
1446 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1447 {
1448 u32 value;
1449
1450 if ((boot_cpu_data.x86 != 0x15) ||
1451 (boot_cpu_data.x86_model < 0x30) ||
1452 (boot_cpu_data.x86_model > 0x3f))
1453 return;
1454
1455 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1456 value = iommu_read_l2(iommu, 0x47);
1457
1458 if (value & BIT(0))
1459 return;
1460
1461 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1462 iommu_write_l2(iommu, 0x47, value | BIT(0));
1463
1464 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1465 dev_name(&iommu->dev->dev));
1466 }
1467
1468 /*
1469 * This function clues the initialization function for one IOMMU
1470 * together and also allocates the command buffer and programs the
1471 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1472 */
1473 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1474 {
1475 int ret;
1476
1477 spin_lock_init(&iommu->lock);
1478
1479 /* Add IOMMU to internal data structures */
1480 list_add_tail(&iommu->list, &amd_iommu_list);
1481 iommu->index = amd_iommus_present++;
1482
1483 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1484 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1485 return -ENOSYS;
1486 }
1487
1488 /* Index is fine - add IOMMU to the array */
1489 amd_iommus[iommu->index] = iommu;
1490
1491 /*
1492 * Copy data from ACPI table entry to the iommu struct
1493 */
1494 iommu->devid = h->devid;
1495 iommu->cap_ptr = h->cap_ptr;
1496 iommu->pci_seg = h->pci_seg;
1497 iommu->mmio_phys = h->mmio_phys;
1498
1499 switch (h->type) {
1500 case 0x10:
1501 /* Check if IVHD EFR contains proper max banks/counters */
1502 if ((h->efr_attr != 0) &&
1503 ((h->efr_attr & (0xF << 13)) != 0) &&
1504 ((h->efr_attr & (0x3F << 17)) != 0))
1505 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1506 else
1507 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1508 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1509 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1510 break;
1511 case 0x11:
1512 case 0x40:
1513 if (h->efr_reg & (1 << 9))
1514 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1515 else
1516 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1517 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1518 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1519 break;
1520 default:
1521 return -EINVAL;
1522 }
1523
1524 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1525 iommu->mmio_phys_end);
1526 if (!iommu->mmio_base)
1527 return -ENOMEM;
1528
1529 if (alloc_command_buffer(iommu))
1530 return -ENOMEM;
1531
1532 if (alloc_event_buffer(iommu))
1533 return -ENOMEM;
1534
1535 iommu->int_enabled = false;
1536
1537 init_translation_status(iommu);
1538 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1539 iommu_disable(iommu);
1540 clear_translation_pre_enabled(iommu);
1541 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1542 iommu->index);
1543 }
1544 if (amd_iommu_pre_enabled)
1545 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1546
1547 ret = init_iommu_from_acpi(iommu, h);
1548 if (ret)
1549 return ret;
1550
1551 ret = amd_iommu_create_irq_domain(iommu);
1552 if (ret)
1553 return ret;
1554
1555 /*
1556 * Make sure IOMMU is not considered to translate itself. The IVRS
1557 * table tells us so, but this is a lie!
1558 */
1559 amd_iommu_rlookup_table[iommu->devid] = NULL;
1560
1561 return 0;
1562 }
1563
1564 /**
1565 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1566 * @ivrs Pointer to the IVRS header
1567 *
1568 * This function search through all IVDB of the maximum supported IVHD
1569 */
1570 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1571 {
1572 u8 *base = (u8 *)ivrs;
1573 struct ivhd_header *ivhd = (struct ivhd_header *)
1574 (base + IVRS_HEADER_LENGTH);
1575 u8 last_type = ivhd->type;
1576 u16 devid = ivhd->devid;
1577
1578 while (((u8 *)ivhd - base < ivrs->length) &&
1579 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1580 u8 *p = (u8 *) ivhd;
1581
1582 if (ivhd->devid == devid)
1583 last_type = ivhd->type;
1584 ivhd = (struct ivhd_header *)(p + ivhd->length);
1585 }
1586
1587 return last_type;
1588 }
1589
1590 /*
1591 * Iterates over all IOMMU entries in the ACPI table, allocates the
1592 * IOMMU structure and initializes it with init_iommu_one()
1593 */
1594 static int __init init_iommu_all(struct acpi_table_header *table)
1595 {
1596 u8 *p = (u8 *)table, *end = (u8 *)table;
1597 struct ivhd_header *h;
1598 struct amd_iommu *iommu;
1599 int ret;
1600
1601 end += table->length;
1602 p += IVRS_HEADER_LENGTH;
1603
1604 while (p < end) {
1605 h = (struct ivhd_header *)p;
1606 if (*p == amd_iommu_target_ivhd_type) {
1607
1608 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1609 "seg: %d flags: %01x info %04x\n",
1610 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1611 PCI_FUNC(h->devid), h->cap_ptr,
1612 h->pci_seg, h->flags, h->info);
1613 DUMP_printk(" mmio-addr: %016llx\n",
1614 h->mmio_phys);
1615
1616 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1617 if (iommu == NULL)
1618 return -ENOMEM;
1619
1620 ret = init_iommu_one(iommu, h);
1621 if (ret)
1622 return ret;
1623 }
1624 p += h->length;
1625
1626 }
1627 WARN_ON(p != end);
1628
1629 return 0;
1630 }
1631
1632 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1633 u8 fxn, u64 *value, bool is_write);
1634
1635 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1636 {
1637 u64 val = 0xabcd, val2 = 0;
1638
1639 if (!iommu_feature(iommu, FEATURE_PC))
1640 return;
1641
1642 amd_iommu_pc_present = true;
1643
1644 /* Check if the performance counters can be written to */
1645 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1646 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1647 (val != val2)) {
1648 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1649 amd_iommu_pc_present = false;
1650 return;
1651 }
1652
1653 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1654
1655 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1656 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1657 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1658 }
1659
1660 static ssize_t amd_iommu_show_cap(struct device *dev,
1661 struct device_attribute *attr,
1662 char *buf)
1663 {
1664 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1665 return sprintf(buf, "%x\n", iommu->cap);
1666 }
1667 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1668
1669 static ssize_t amd_iommu_show_features(struct device *dev,
1670 struct device_attribute *attr,
1671 char *buf)
1672 {
1673 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1674 return sprintf(buf, "%llx\n", iommu->features);
1675 }
1676 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1677
1678 static struct attribute *amd_iommu_attrs[] = {
1679 &dev_attr_cap.attr,
1680 &dev_attr_features.attr,
1681 NULL,
1682 };
1683
1684 static struct attribute_group amd_iommu_group = {
1685 .name = "amd-iommu",
1686 .attrs = amd_iommu_attrs,
1687 };
1688
1689 static const struct attribute_group *amd_iommu_groups[] = {
1690 &amd_iommu_group,
1691 NULL,
1692 };
1693
1694 static int iommu_init_pci(struct amd_iommu *iommu)
1695 {
1696 int cap_ptr = iommu->cap_ptr;
1697 u32 range, misc, low, high;
1698 int ret;
1699
1700 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1701 iommu->devid & 0xff);
1702 if (!iommu->dev)
1703 return -ENODEV;
1704
1705 /* Prevent binding other PCI device drivers to IOMMU devices */
1706 iommu->dev->match_driver = false;
1707
1708 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1709 &iommu->cap);
1710 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1711 &range);
1712 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1713 &misc);
1714
1715 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1716 amd_iommu_iotlb_sup = false;
1717
1718 /* read extended feature bits */
1719 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1720 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1721
1722 iommu->features = ((u64)high << 32) | low;
1723
1724 if (iommu_feature(iommu, FEATURE_GT)) {
1725 int glxval;
1726 u32 max_pasid;
1727 u64 pasmax;
1728
1729 pasmax = iommu->features & FEATURE_PASID_MASK;
1730 pasmax >>= FEATURE_PASID_SHIFT;
1731 max_pasid = (1 << (pasmax + 1)) - 1;
1732
1733 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1734
1735 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1736
1737 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1738 glxval >>= FEATURE_GLXVAL_SHIFT;
1739
1740 if (amd_iommu_max_glx_val == -1)
1741 amd_iommu_max_glx_val = glxval;
1742 else
1743 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1744 }
1745
1746 if (iommu_feature(iommu, FEATURE_GT) &&
1747 iommu_feature(iommu, FEATURE_PPR)) {
1748 iommu->is_iommu_v2 = true;
1749 amd_iommu_v2_present = true;
1750 }
1751
1752 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1753 return -ENOMEM;
1754
1755 ret = iommu_init_ga(iommu);
1756 if (ret)
1757 return ret;
1758
1759 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1760 amd_iommu_np_cache = true;
1761
1762 init_iommu_perf_ctr(iommu);
1763
1764 if (is_rd890_iommu(iommu->dev)) {
1765 int i, j;
1766
1767 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1768 PCI_DEVFN(0, 0));
1769
1770 /*
1771 * Some rd890 systems may not be fully reconfigured by the
1772 * BIOS, so it's necessary for us to store this information so
1773 * it can be reprogrammed on resume
1774 */
1775 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1776 &iommu->stored_addr_lo);
1777 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1778 &iommu->stored_addr_hi);
1779
1780 /* Low bit locks writes to configuration space */
1781 iommu->stored_addr_lo &= ~1;
1782
1783 for (i = 0; i < 6; i++)
1784 for (j = 0; j < 0x12; j++)
1785 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1786
1787 for (i = 0; i < 0x83; i++)
1788 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1789 }
1790
1791 amd_iommu_erratum_746_workaround(iommu);
1792 amd_iommu_ats_write_check_workaround(iommu);
1793
1794 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1795 amd_iommu_groups, "ivhd%d", iommu->index);
1796 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1797 iommu_device_register(&iommu->iommu);
1798
1799 return pci_enable_device(iommu->dev);
1800 }
1801
1802 static void print_iommu_info(void)
1803 {
1804 static const char * const feat_str[] = {
1805 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1806 "IA", "GA", "HE", "PC"
1807 };
1808 struct amd_iommu *iommu;
1809
1810 for_each_iommu(iommu) {
1811 int i;
1812
1813 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1814 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1815
1816 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1817 pr_info("AMD-Vi: Extended features (%#llx):\n",
1818 iommu->features);
1819 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1820 if (iommu_feature(iommu, (1ULL << i)))
1821 pr_cont(" %s", feat_str[i]);
1822 }
1823
1824 if (iommu->features & FEATURE_GAM_VAPIC)
1825 pr_cont(" GA_vAPIC");
1826
1827 pr_cont("\n");
1828 }
1829 }
1830 if (irq_remapping_enabled) {
1831 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1832 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1833 pr_info("AMD-Vi: virtual APIC enabled\n");
1834 }
1835 }
1836
1837 static int __init amd_iommu_init_pci(void)
1838 {
1839 struct amd_iommu *iommu;
1840 int ret = 0;
1841
1842 for_each_iommu(iommu) {
1843 ret = iommu_init_pci(iommu);
1844 if (ret)
1845 break;
1846 }
1847
1848 /*
1849 * Order is important here to make sure any unity map requirements are
1850 * fulfilled. The unity mappings are created and written to the device
1851 * table during the amd_iommu_init_api() call.
1852 *
1853 * After that we call init_device_table_dma() to make sure any
1854 * uninitialized DTE will block DMA, and in the end we flush the caches
1855 * of all IOMMUs to make sure the changes to the device table are
1856 * active.
1857 */
1858 ret = amd_iommu_init_api();
1859
1860 init_device_table_dma();
1861
1862 for_each_iommu(iommu)
1863 iommu_flush_all_caches(iommu);
1864
1865 if (!ret)
1866 print_iommu_info();
1867
1868 return ret;
1869 }
1870
1871 /****************************************************************************
1872 *
1873 * The following functions initialize the MSI interrupts for all IOMMUs
1874 * in the system. It's a bit challenging because there could be multiple
1875 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1876 * pci_dev.
1877 *
1878 ****************************************************************************/
1879
1880 static int iommu_setup_msi(struct amd_iommu *iommu)
1881 {
1882 int r;
1883
1884 r = pci_enable_msi(iommu->dev);
1885 if (r)
1886 return r;
1887
1888 r = request_threaded_irq(iommu->dev->irq,
1889 amd_iommu_int_handler,
1890 amd_iommu_int_thread,
1891 0, "AMD-Vi",
1892 iommu);
1893
1894 if (r) {
1895 pci_disable_msi(iommu->dev);
1896 return r;
1897 }
1898
1899 iommu->int_enabled = true;
1900
1901 return 0;
1902 }
1903
1904 static int iommu_init_msi(struct amd_iommu *iommu)
1905 {
1906 int ret;
1907
1908 if (iommu->int_enabled)
1909 goto enable_faults;
1910
1911 if (iommu->dev->msi_cap)
1912 ret = iommu_setup_msi(iommu);
1913 else
1914 ret = -ENODEV;
1915
1916 if (ret)
1917 return ret;
1918
1919 enable_faults:
1920 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1921
1922 if (iommu->ppr_log != NULL)
1923 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1924
1925 iommu_ga_log_enable(iommu);
1926
1927 return 0;
1928 }
1929
1930 /****************************************************************************
1931 *
1932 * The next functions belong to the third pass of parsing the ACPI
1933 * table. In this last pass the memory mapping requirements are
1934 * gathered (like exclusion and unity mapping ranges).
1935 *
1936 ****************************************************************************/
1937
1938 static void __init free_unity_maps(void)
1939 {
1940 struct unity_map_entry *entry, *next;
1941
1942 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1943 list_del(&entry->list);
1944 kfree(entry);
1945 }
1946 }
1947
1948 /* called when we find an exclusion range definition in ACPI */
1949 static int __init init_exclusion_range(struct ivmd_header *m)
1950 {
1951 int i;
1952
1953 switch (m->type) {
1954 case ACPI_IVMD_TYPE:
1955 set_device_exclusion_range(m->devid, m);
1956 break;
1957 case ACPI_IVMD_TYPE_ALL:
1958 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1959 set_device_exclusion_range(i, m);
1960 break;
1961 case ACPI_IVMD_TYPE_RANGE:
1962 for (i = m->devid; i <= m->aux; ++i)
1963 set_device_exclusion_range(i, m);
1964 break;
1965 default:
1966 break;
1967 }
1968
1969 return 0;
1970 }
1971
1972 /* called for unity map ACPI definition */
1973 static int __init init_unity_map_range(struct ivmd_header *m)
1974 {
1975 struct unity_map_entry *e = NULL;
1976 char *s;
1977
1978 e = kzalloc(sizeof(*e), GFP_KERNEL);
1979 if (e == NULL)
1980 return -ENOMEM;
1981
1982 switch (m->type) {
1983 default:
1984 kfree(e);
1985 return 0;
1986 case ACPI_IVMD_TYPE:
1987 s = "IVMD_TYPEi\t\t\t";
1988 e->devid_start = e->devid_end = m->devid;
1989 break;
1990 case ACPI_IVMD_TYPE_ALL:
1991 s = "IVMD_TYPE_ALL\t\t";
1992 e->devid_start = 0;
1993 e->devid_end = amd_iommu_last_bdf;
1994 break;
1995 case ACPI_IVMD_TYPE_RANGE:
1996 s = "IVMD_TYPE_RANGE\t\t";
1997 e->devid_start = m->devid;
1998 e->devid_end = m->aux;
1999 break;
2000 }
2001 e->address_start = PAGE_ALIGN(m->range_start);
2002 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2003 e->prot = m->flags >> 1;
2004
2005 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2006 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2007 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2008 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2009 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2010 e->address_start, e->address_end, m->flags);
2011
2012 list_add_tail(&e->list, &amd_iommu_unity_map);
2013
2014 return 0;
2015 }
2016
2017 /* iterates over all memory definitions we find in the ACPI table */
2018 static int __init init_memory_definitions(struct acpi_table_header *table)
2019 {
2020 u8 *p = (u8 *)table, *end = (u8 *)table;
2021 struct ivmd_header *m;
2022
2023 end += table->length;
2024 p += IVRS_HEADER_LENGTH;
2025
2026 while (p < end) {
2027 m = (struct ivmd_header *)p;
2028 if (m->flags & IVMD_FLAG_EXCL_RANGE)
2029 init_exclusion_range(m);
2030 else if (m->flags & IVMD_FLAG_UNITY_MAP)
2031 init_unity_map_range(m);
2032
2033 p += m->length;
2034 }
2035
2036 return 0;
2037 }
2038
2039 /*
2040 * Init the device table to not allow DMA access for devices
2041 */
2042 static void init_device_table_dma(void)
2043 {
2044 u32 devid;
2045
2046 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2047 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2048 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2049 }
2050 }
2051
2052 static void __init uninit_device_table_dma(void)
2053 {
2054 u32 devid;
2055
2056 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2057 amd_iommu_dev_table[devid].data[0] = 0ULL;
2058 amd_iommu_dev_table[devid].data[1] = 0ULL;
2059 }
2060 }
2061
2062 static void init_device_table(void)
2063 {
2064 u32 devid;
2065
2066 if (!amd_iommu_irq_remap)
2067 return;
2068
2069 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2070 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2071 }
2072
2073 static void iommu_init_flags(struct amd_iommu *iommu)
2074 {
2075 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2076 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2077 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2078
2079 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2080 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2081 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2082
2083 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2084 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2085 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2086
2087 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2088 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2089 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2090
2091 /*
2092 * make IOMMU memory accesses cache coherent
2093 */
2094 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2095
2096 /* Set IOTLB invalidation timeout to 1s */
2097 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2098 }
2099
2100 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2101 {
2102 int i, j;
2103 u32 ioc_feature_control;
2104 struct pci_dev *pdev = iommu->root_pdev;
2105
2106 /* RD890 BIOSes may not have completely reconfigured the iommu */
2107 if (!is_rd890_iommu(iommu->dev) || !pdev)
2108 return;
2109
2110 /*
2111 * First, we need to ensure that the iommu is enabled. This is
2112 * controlled by a register in the northbridge
2113 */
2114
2115 /* Select Northbridge indirect register 0x75 and enable writing */
2116 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2117 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2118
2119 /* Enable the iommu */
2120 if (!(ioc_feature_control & 0x1))
2121 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2122
2123 /* Restore the iommu BAR */
2124 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2125 iommu->stored_addr_lo);
2126 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2127 iommu->stored_addr_hi);
2128
2129 /* Restore the l1 indirect regs for each of the 6 l1s */
2130 for (i = 0; i < 6; i++)
2131 for (j = 0; j < 0x12; j++)
2132 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2133
2134 /* Restore the l2 indirect regs */
2135 for (i = 0; i < 0x83; i++)
2136 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2137
2138 /* Lock PCI setup registers */
2139 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2140 iommu->stored_addr_lo | 1);
2141 }
2142
2143 static void iommu_enable_ga(struct amd_iommu *iommu)
2144 {
2145 #ifdef CONFIG_IRQ_REMAP
2146 switch (amd_iommu_guest_ir) {
2147 case AMD_IOMMU_GUEST_IR_VAPIC:
2148 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2149 /* Fall through */
2150 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2151 iommu_feature_enable(iommu, CONTROL_GA_EN);
2152 iommu->irte_ops = &irte_128_ops;
2153 break;
2154 default:
2155 iommu->irte_ops = &irte_32_ops;
2156 break;
2157 }
2158 #endif
2159 }
2160
2161 static void early_enable_iommu(struct amd_iommu *iommu)
2162 {
2163 iommu_disable(iommu);
2164 iommu_init_flags(iommu);
2165 iommu_set_device_table(iommu);
2166 iommu_enable_command_buffer(iommu);
2167 iommu_enable_event_buffer(iommu);
2168 iommu_set_exclusion_range(iommu);
2169 iommu_enable_ga(iommu);
2170 iommu_enable(iommu);
2171 iommu_flush_all_caches(iommu);
2172 }
2173
2174 /*
2175 * This function finally enables all IOMMUs found in the system after
2176 * they have been initialized.
2177 *
2178 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2179 * the old content of device table entries. Not this case or copy failed,
2180 * just continue as normal kernel does.
2181 */
2182 static void early_enable_iommus(void)
2183 {
2184 struct amd_iommu *iommu;
2185
2186
2187 if (!copy_device_table()) {
2188 /*
2189 * If come here because of failure in copying device table from old
2190 * kernel with all IOMMUs enabled, print error message and try to
2191 * free allocated old_dev_tbl_cpy.
2192 */
2193 if (amd_iommu_pre_enabled)
2194 pr_err("Failed to copy DEV table from previous kernel.\n");
2195 if (old_dev_tbl_cpy != NULL)
2196 free_pages((unsigned long)old_dev_tbl_cpy,
2197 get_order(dev_table_size));
2198
2199 for_each_iommu(iommu) {
2200 clear_translation_pre_enabled(iommu);
2201 early_enable_iommu(iommu);
2202 }
2203 } else {
2204 pr_info("Copied DEV table from previous kernel.\n");
2205 free_pages((unsigned long)amd_iommu_dev_table,
2206 get_order(dev_table_size));
2207 amd_iommu_dev_table = old_dev_tbl_cpy;
2208 for_each_iommu(iommu) {
2209 iommu_disable_command_buffer(iommu);
2210 iommu_disable_event_buffer(iommu);
2211 iommu_enable_command_buffer(iommu);
2212 iommu_enable_event_buffer(iommu);
2213 iommu_enable_ga(iommu);
2214 iommu_set_device_table(iommu);
2215 iommu_flush_all_caches(iommu);
2216 }
2217 }
2218
2219 #ifdef CONFIG_IRQ_REMAP
2220 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2221 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2222 #endif
2223 }
2224
2225 static void enable_iommus_v2(void)
2226 {
2227 struct amd_iommu *iommu;
2228
2229 for_each_iommu(iommu) {
2230 iommu_enable_ppr_log(iommu);
2231 iommu_enable_gt(iommu);
2232 }
2233 }
2234
2235 static void enable_iommus(void)
2236 {
2237 early_enable_iommus();
2238
2239 enable_iommus_v2();
2240 }
2241
2242 static void disable_iommus(void)
2243 {
2244 struct amd_iommu *iommu;
2245
2246 for_each_iommu(iommu)
2247 iommu_disable(iommu);
2248
2249 #ifdef CONFIG_IRQ_REMAP
2250 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2251 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2252 #endif
2253 }
2254
2255 /*
2256 * Suspend/Resume support
2257 * disable suspend until real resume implemented
2258 */
2259
2260 static void amd_iommu_resume(void)
2261 {
2262 struct amd_iommu *iommu;
2263
2264 for_each_iommu(iommu)
2265 iommu_apply_resume_quirks(iommu);
2266
2267 /* re-load the hardware */
2268 enable_iommus();
2269
2270 amd_iommu_enable_interrupts();
2271 }
2272
2273 static int amd_iommu_suspend(void)
2274 {
2275 /* disable IOMMUs to go out of the way for BIOS */
2276 disable_iommus();
2277
2278 return 0;
2279 }
2280
2281 static struct syscore_ops amd_iommu_syscore_ops = {
2282 .suspend = amd_iommu_suspend,
2283 .resume = amd_iommu_resume,
2284 };
2285
2286 static void __init free_iommu_resources(void)
2287 {
2288 kmemleak_free(irq_lookup_table);
2289 free_pages((unsigned long)irq_lookup_table,
2290 get_order(rlookup_table_size));
2291 irq_lookup_table = NULL;
2292
2293 kmem_cache_destroy(amd_iommu_irq_cache);
2294 amd_iommu_irq_cache = NULL;
2295
2296 free_pages((unsigned long)amd_iommu_rlookup_table,
2297 get_order(rlookup_table_size));
2298 amd_iommu_rlookup_table = NULL;
2299
2300 free_pages((unsigned long)amd_iommu_alias_table,
2301 get_order(alias_table_size));
2302 amd_iommu_alias_table = NULL;
2303
2304 free_pages((unsigned long)amd_iommu_dev_table,
2305 get_order(dev_table_size));
2306 amd_iommu_dev_table = NULL;
2307
2308 free_iommu_all();
2309
2310 #ifdef CONFIG_GART_IOMMU
2311 /*
2312 * We failed to initialize the AMD IOMMU - try fallback to GART
2313 * if possible.
2314 */
2315 gart_iommu_init();
2316
2317 #endif
2318 }
2319
2320 /* SB IOAPIC is always on this device in AMD systems */
2321 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2322
2323 static bool __init check_ioapic_information(void)
2324 {
2325 const char *fw_bug = FW_BUG;
2326 bool ret, has_sb_ioapic;
2327 int idx;
2328
2329 has_sb_ioapic = false;
2330 ret = false;
2331
2332 /*
2333 * If we have map overrides on the kernel command line the
2334 * messages in this function might not describe firmware bugs
2335 * anymore - so be careful
2336 */
2337 if (cmdline_maps)
2338 fw_bug = "";
2339
2340 for (idx = 0; idx < nr_ioapics; idx++) {
2341 int devid, id = mpc_ioapic_id(idx);
2342
2343 devid = get_ioapic_devid(id);
2344 if (devid < 0) {
2345 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2346 fw_bug, id);
2347 ret = false;
2348 } else if (devid == IOAPIC_SB_DEVID) {
2349 has_sb_ioapic = true;
2350 ret = true;
2351 }
2352 }
2353
2354 if (!has_sb_ioapic) {
2355 /*
2356 * We expect the SB IOAPIC to be listed in the IVRS
2357 * table. The system timer is connected to the SB IOAPIC
2358 * and if we don't have it in the list the system will
2359 * panic at boot time. This situation usually happens
2360 * when the BIOS is buggy and provides us the wrong
2361 * device id for the IOAPIC in the system.
2362 */
2363 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2364 }
2365
2366 if (!ret)
2367 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2368
2369 return ret;
2370 }
2371
2372 static void __init free_dma_resources(void)
2373 {
2374 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2375 get_order(MAX_DOMAIN_ID/8));
2376 amd_iommu_pd_alloc_bitmap = NULL;
2377
2378 free_unity_maps();
2379 }
2380
2381 /*
2382 * This is the hardware init function for AMD IOMMU in the system.
2383 * This function is called either from amd_iommu_init or from the interrupt
2384 * remapping setup code.
2385 *
2386 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2387 * four times:
2388 *
2389 * 1 pass) Discover the most comprehensive IVHD type to use.
2390 *
2391 * 2 pass) Find the highest PCI device id the driver has to handle.
2392 * Upon this information the size of the data structures is
2393 * determined that needs to be allocated.
2394 *
2395 * 3 pass) Initialize the data structures just allocated with the
2396 * information in the ACPI table about available AMD IOMMUs
2397 * in the system. It also maps the PCI devices in the
2398 * system to specific IOMMUs
2399 *
2400 * 4 pass) After the basic data structures are allocated and
2401 * initialized we update them with information about memory
2402 * remapping requirements parsed out of the ACPI table in
2403 * this last pass.
2404 *
2405 * After everything is set up the IOMMUs are enabled and the necessary
2406 * hotplug and suspend notifiers are registered.
2407 */
2408 static int __init early_amd_iommu_init(void)
2409 {
2410 struct acpi_table_header *ivrs_base;
2411 acpi_status status;
2412 int i, remap_cache_sz, ret = 0;
2413
2414 if (!amd_iommu_detected)
2415 return -ENODEV;
2416
2417 status = acpi_get_table("IVRS", 0, &ivrs_base);
2418 if (status == AE_NOT_FOUND)
2419 return -ENODEV;
2420 else if (ACPI_FAILURE(status)) {
2421 const char *err = acpi_format_exception(status);
2422 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2423 return -EINVAL;
2424 }
2425
2426 /*
2427 * Validate checksum here so we don't need to do it when
2428 * we actually parse the table
2429 */
2430 ret = check_ivrs_checksum(ivrs_base);
2431 if (ret)
2432 goto out;
2433
2434 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2435 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2436
2437 /*
2438 * First parse ACPI tables to find the largest Bus/Dev/Func
2439 * we need to handle. Upon this information the shared data
2440 * structures for the IOMMUs in the system will be allocated
2441 */
2442 ret = find_last_devid_acpi(ivrs_base);
2443 if (ret)
2444 goto out;
2445
2446 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2447 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2448 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2449
2450 /* Device table - directly used by all IOMMUs */
2451 ret = -ENOMEM;
2452 amd_iommu_dev_table = (void *)__get_free_pages(
2453 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2454 get_order(dev_table_size));
2455 if (amd_iommu_dev_table == NULL)
2456 goto out;
2457
2458 /*
2459 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2460 * IOMMU see for that device
2461 */
2462 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2463 get_order(alias_table_size));
2464 if (amd_iommu_alias_table == NULL)
2465 goto out;
2466
2467 /* IOMMU rlookup table - find the IOMMU for a specific device */
2468 amd_iommu_rlookup_table = (void *)__get_free_pages(
2469 GFP_KERNEL | __GFP_ZERO,
2470 get_order(rlookup_table_size));
2471 if (amd_iommu_rlookup_table == NULL)
2472 goto out;
2473
2474 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2475 GFP_KERNEL | __GFP_ZERO,
2476 get_order(MAX_DOMAIN_ID/8));
2477 if (amd_iommu_pd_alloc_bitmap == NULL)
2478 goto out;
2479
2480 /*
2481 * let all alias entries point to itself
2482 */
2483 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2484 amd_iommu_alias_table[i] = i;
2485
2486 /*
2487 * never allocate domain 0 because its used as the non-allocated and
2488 * error value placeholder
2489 */
2490 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2491
2492 spin_lock_init(&amd_iommu_pd_lock);
2493
2494 /*
2495 * now the data structures are allocated and basically initialized
2496 * start the real acpi table scan
2497 */
2498 ret = init_iommu_all(ivrs_base);
2499 if (ret)
2500 goto out;
2501
2502 /* Disable any previously enabled IOMMUs */
2503 if (!is_kdump_kernel() || amd_iommu_disabled)
2504 disable_iommus();
2505
2506 if (amd_iommu_irq_remap)
2507 amd_iommu_irq_remap = check_ioapic_information();
2508
2509 if (amd_iommu_irq_remap) {
2510 /*
2511 * Interrupt remapping enabled, create kmem_cache for the
2512 * remapping tables.
2513 */
2514 ret = -ENOMEM;
2515 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2516 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2517 else
2518 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2519 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2520 remap_cache_sz,
2521 IRQ_TABLE_ALIGNMENT,
2522 0, NULL);
2523 if (!amd_iommu_irq_cache)
2524 goto out;
2525
2526 irq_lookup_table = (void *)__get_free_pages(
2527 GFP_KERNEL | __GFP_ZERO,
2528 get_order(rlookup_table_size));
2529 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2530 1, GFP_KERNEL);
2531 if (!irq_lookup_table)
2532 goto out;
2533 }
2534
2535 ret = init_memory_definitions(ivrs_base);
2536 if (ret)
2537 goto out;
2538
2539 /* init the device table */
2540 init_device_table();
2541
2542 out:
2543 /* Don't leak any ACPI memory */
2544 acpi_put_table(ivrs_base);
2545 ivrs_base = NULL;
2546
2547 return ret;
2548 }
2549
2550 static int amd_iommu_enable_interrupts(void)
2551 {
2552 struct amd_iommu *iommu;
2553 int ret = 0;
2554
2555 for_each_iommu(iommu) {
2556 ret = iommu_init_msi(iommu);
2557 if (ret)
2558 goto out;
2559 }
2560
2561 out:
2562 return ret;
2563 }
2564
2565 static bool detect_ivrs(void)
2566 {
2567 struct acpi_table_header *ivrs_base;
2568 acpi_status status;
2569
2570 status = acpi_get_table("IVRS", 0, &ivrs_base);
2571 if (status == AE_NOT_FOUND)
2572 return false;
2573 else if (ACPI_FAILURE(status)) {
2574 const char *err = acpi_format_exception(status);
2575 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2576 return false;
2577 }
2578
2579 acpi_put_table(ivrs_base);
2580
2581 /* Make sure ACS will be enabled during PCI probe */
2582 pci_request_acs();
2583
2584 return true;
2585 }
2586
2587 /****************************************************************************
2588 *
2589 * AMD IOMMU Initialization State Machine
2590 *
2591 ****************************************************************************/
2592
2593 static int __init state_next(void)
2594 {
2595 int ret = 0;
2596
2597 switch (init_state) {
2598 case IOMMU_START_STATE:
2599 if (!detect_ivrs()) {
2600 init_state = IOMMU_NOT_FOUND;
2601 ret = -ENODEV;
2602 } else {
2603 init_state = IOMMU_IVRS_DETECTED;
2604 }
2605 break;
2606 case IOMMU_IVRS_DETECTED:
2607 ret = early_amd_iommu_init();
2608 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2609 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2610 pr_info("AMD-Vi: AMD IOMMU disabled on kernel command-line\n");
2611 free_dma_resources();
2612 free_iommu_resources();
2613 init_state = IOMMU_CMDLINE_DISABLED;
2614 ret = -EINVAL;
2615 }
2616 break;
2617 case IOMMU_ACPI_FINISHED:
2618 early_enable_iommus();
2619 x86_platform.iommu_shutdown = disable_iommus;
2620 init_state = IOMMU_ENABLED;
2621 break;
2622 case IOMMU_ENABLED:
2623 register_syscore_ops(&amd_iommu_syscore_ops);
2624 ret = amd_iommu_init_pci();
2625 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2626 enable_iommus_v2();
2627 break;
2628 case IOMMU_PCI_INIT:
2629 ret = amd_iommu_enable_interrupts();
2630 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2631 break;
2632 case IOMMU_INTERRUPTS_EN:
2633 ret = amd_iommu_init_dma_ops();
2634 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2635 break;
2636 case IOMMU_DMA_OPS:
2637 init_state = IOMMU_INITIALIZED;
2638 break;
2639 case IOMMU_INITIALIZED:
2640 /* Nothing to do */
2641 break;
2642 case IOMMU_NOT_FOUND:
2643 case IOMMU_INIT_ERROR:
2644 case IOMMU_CMDLINE_DISABLED:
2645 /* Error states => do nothing */
2646 ret = -EINVAL;
2647 break;
2648 default:
2649 /* Unknown state */
2650 BUG();
2651 }
2652
2653 return ret;
2654 }
2655
2656 static int __init iommu_go_to_state(enum iommu_init_state state)
2657 {
2658 int ret = -EINVAL;
2659
2660 while (init_state != state) {
2661 if (init_state == IOMMU_NOT_FOUND ||
2662 init_state == IOMMU_INIT_ERROR ||
2663 init_state == IOMMU_CMDLINE_DISABLED)
2664 break;
2665 ret = state_next();
2666 }
2667
2668 return ret;
2669 }
2670
2671 #ifdef CONFIG_IRQ_REMAP
2672 int __init amd_iommu_prepare(void)
2673 {
2674 int ret;
2675
2676 amd_iommu_irq_remap = true;
2677
2678 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2679 if (ret)
2680 return ret;
2681 return amd_iommu_irq_remap ? 0 : -ENODEV;
2682 }
2683
2684 int __init amd_iommu_enable(void)
2685 {
2686 int ret;
2687
2688 ret = iommu_go_to_state(IOMMU_ENABLED);
2689 if (ret)
2690 return ret;
2691
2692 irq_remapping_enabled = 1;
2693
2694 return 0;
2695 }
2696
2697 void amd_iommu_disable(void)
2698 {
2699 amd_iommu_suspend();
2700 }
2701
2702 int amd_iommu_reenable(int mode)
2703 {
2704 amd_iommu_resume();
2705
2706 return 0;
2707 }
2708
2709 int __init amd_iommu_enable_faulting(void)
2710 {
2711 /* We enable MSI later when PCI is initialized */
2712 return 0;
2713 }
2714 #endif
2715
2716 /*
2717 * This is the core init function for AMD IOMMU hardware in the system.
2718 * This function is called from the generic x86 DMA layer initialization
2719 * code.
2720 */
2721 static int __init amd_iommu_init(void)
2722 {
2723 int ret;
2724
2725 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2726 if (ret) {
2727 free_dma_resources();
2728 if (!irq_remapping_enabled) {
2729 disable_iommus();
2730 free_iommu_resources();
2731 } else {
2732 struct amd_iommu *iommu;
2733
2734 uninit_device_table_dma();
2735 for_each_iommu(iommu)
2736 iommu_flush_all_caches(iommu);
2737 }
2738 }
2739
2740 return ret;
2741 }
2742
2743 static bool amd_iommu_sme_check(void)
2744 {
2745 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2746 return true;
2747
2748 /* For Fam17h, a specific level of support is required */
2749 if (boot_cpu_data.microcode >= 0x08001205)
2750 return true;
2751
2752 if ((boot_cpu_data.microcode >= 0x08001126) &&
2753 (boot_cpu_data.microcode <= 0x080011ff))
2754 return true;
2755
2756 pr_notice("AMD-Vi: IOMMU not currently supported when SME is active\n");
2757
2758 return false;
2759 }
2760
2761 /****************************************************************************
2762 *
2763 * Early detect code. This code runs at IOMMU detection time in the DMA
2764 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2765 * IOMMUs
2766 *
2767 ****************************************************************************/
2768 int __init amd_iommu_detect(void)
2769 {
2770 int ret;
2771
2772 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2773 return -ENODEV;
2774
2775 if (!amd_iommu_sme_check())
2776 return -ENODEV;
2777
2778 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2779 if (ret)
2780 return ret;
2781
2782 amd_iommu_detected = true;
2783 iommu_detected = 1;
2784 x86_init.iommu.iommu_init = amd_iommu_init;
2785
2786 return 1;
2787 }
2788
2789 /****************************************************************************
2790 *
2791 * Parsing functions for the AMD IOMMU specific kernel command line
2792 * options.
2793 *
2794 ****************************************************************************/
2795
2796 static int __init parse_amd_iommu_dump(char *str)
2797 {
2798 amd_iommu_dump = true;
2799
2800 return 1;
2801 }
2802
2803 static int __init parse_amd_iommu_intr(char *str)
2804 {
2805 for (; *str; ++str) {
2806 if (strncmp(str, "legacy", 6) == 0) {
2807 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2808 break;
2809 }
2810 if (strncmp(str, "vapic", 5) == 0) {
2811 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2812 break;
2813 }
2814 }
2815 return 1;
2816 }
2817
2818 static int __init parse_amd_iommu_options(char *str)
2819 {
2820 for (; *str; ++str) {
2821 if (strncmp(str, "fullflush", 9) == 0)
2822 amd_iommu_unmap_flush = true;
2823 if (strncmp(str, "off", 3) == 0)
2824 amd_iommu_disabled = true;
2825 if (strncmp(str, "force_isolation", 15) == 0)
2826 amd_iommu_force_isolation = true;
2827 }
2828
2829 return 1;
2830 }
2831
2832 static int __init parse_ivrs_ioapic(char *str)
2833 {
2834 unsigned int bus, dev, fn;
2835 int ret, id, i;
2836 u16 devid;
2837
2838 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2839
2840 if (ret != 4) {
2841 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2842 return 1;
2843 }
2844
2845 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2846 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2847 str);
2848 return 1;
2849 }
2850
2851 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2852
2853 cmdline_maps = true;
2854 i = early_ioapic_map_size++;
2855 early_ioapic_map[i].id = id;
2856 early_ioapic_map[i].devid = devid;
2857 early_ioapic_map[i].cmd_line = true;
2858
2859 return 1;
2860 }
2861
2862 static int __init parse_ivrs_hpet(char *str)
2863 {
2864 unsigned int bus, dev, fn;
2865 int ret, id, i;
2866 u16 devid;
2867
2868 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2869
2870 if (ret != 4) {
2871 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2872 return 1;
2873 }
2874
2875 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2876 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2877 str);
2878 return 1;
2879 }
2880
2881 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2882
2883 cmdline_maps = true;
2884 i = early_hpet_map_size++;
2885 early_hpet_map[i].id = id;
2886 early_hpet_map[i].devid = devid;
2887 early_hpet_map[i].cmd_line = true;
2888
2889 return 1;
2890 }
2891
2892 static int __init parse_ivrs_acpihid(char *str)
2893 {
2894 u32 bus, dev, fn;
2895 char *hid, *uid, *p;
2896 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2897 int ret, i;
2898
2899 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2900 if (ret != 4) {
2901 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2902 return 1;
2903 }
2904
2905 p = acpiid;
2906 hid = strsep(&p, ":");
2907 uid = p;
2908
2909 if (!hid || !(*hid) || !uid) {
2910 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2911 return 1;
2912 }
2913
2914 i = early_acpihid_map_size++;
2915 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2916 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2917 early_acpihid_map[i].devid =
2918 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2919 early_acpihid_map[i].cmd_line = true;
2920
2921 return 1;
2922 }
2923
2924 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2925 __setup("amd_iommu=", parse_amd_iommu_options);
2926 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2927 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2928 __setup("ivrs_hpet", parse_ivrs_hpet);
2929 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2930
2931 IOMMU_INIT_FINISH(amd_iommu_detect,
2932 gart_iommu_hole_init,
2933 NULL,
2934 NULL);
2935
2936 bool amd_iommu_v2_supported(void)
2937 {
2938 return amd_iommu_v2_present;
2939 }
2940 EXPORT_SYMBOL(amd_iommu_v2_supported);
2941
2942 struct amd_iommu *get_amd_iommu(unsigned int idx)
2943 {
2944 unsigned int i = 0;
2945 struct amd_iommu *iommu;
2946
2947 for_each_iommu(iommu)
2948 if (i++ == idx)
2949 return iommu;
2950 return NULL;
2951 }
2952 EXPORT_SYMBOL(get_amd_iommu);
2953
2954 /****************************************************************************
2955 *
2956 * IOMMU EFR Performance Counter support functionality. This code allows
2957 * access to the IOMMU PC functionality.
2958 *
2959 ****************************************************************************/
2960
2961 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
2962 {
2963 struct amd_iommu *iommu = get_amd_iommu(idx);
2964
2965 if (iommu)
2966 return iommu->max_banks;
2967
2968 return 0;
2969 }
2970 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2971
2972 bool amd_iommu_pc_supported(void)
2973 {
2974 return amd_iommu_pc_present;
2975 }
2976 EXPORT_SYMBOL(amd_iommu_pc_supported);
2977
2978 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
2979 {
2980 struct amd_iommu *iommu = get_amd_iommu(idx);
2981
2982 if (iommu)
2983 return iommu->max_counters;
2984
2985 return 0;
2986 }
2987 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2988
2989 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
2990 u8 fxn, u64 *value, bool is_write)
2991 {
2992 u32 offset;
2993 u32 max_offset_lim;
2994
2995 /* Make sure the IOMMU PC resource is available */
2996 if (!amd_iommu_pc_present)
2997 return -ENODEV;
2998
2999 /* Check for valid iommu and pc register indexing */
3000 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3001 return -ENODEV;
3002
3003 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3004
3005 /* Limit the offset to the hw defined mmio region aperture */
3006 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3007 (iommu->max_counters << 8) | 0x28);
3008 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3009 (offset > max_offset_lim))
3010 return -EINVAL;
3011
3012 if (is_write) {
3013 u64 val = *value & GENMASK_ULL(47, 0);
3014
3015 writel((u32)val, iommu->mmio_base + offset);
3016 writel((val >> 32), iommu->mmio_base + offset + 4);
3017 } else {
3018 *value = readl(iommu->mmio_base + offset + 4);
3019 *value <<= 32;
3020 *value |= readl(iommu->mmio_base + offset);
3021 *value &= GENMASK_ULL(47, 0);
3022 }
3023
3024 return 0;
3025 }
3026
3027 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3028 {
3029 if (!iommu)
3030 return -EINVAL;
3031
3032 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3033 }
3034 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
3035
3036 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3037 {
3038 if (!iommu)
3039 return -EINVAL;
3040
3041 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
3042 }
3043 EXPORT_SYMBOL(amd_iommu_pc_set_reg);
Linux with added FPC-III support