drivers/irqchip/irq-mbigen.c

   1 /*
   2  * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
   3  * Author: Jun Ma <majun258@huawei.com>
   4  * Author: Yun Wu <wuyun.wu@huawei.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/interrupt.h>
  20 #include <linux/irqchip.h>
  21 #include <linux/module.h>
  22 #include <linux/msi.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28
  29 /* Interrupt numbers per mbigen node supported */
  30 #define IRQS_PER_MBIGEN_NODE            128
  31
  32 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
  33 #define RESERVED_IRQ_PER_MBIGEN_CHIP    64
  34
  35 /* The maximum IRQ pin number of mbigen chip(start from 0) */
  36 #define MAXIMUM_IRQ_PIN_NUM             1407
  37
  38 /**
  39  * In mbigen vector register
  40  * bit[21:12]:  event id value
  41  * bit[11:0]:   device id
  42  */
  43 #define IRQ_EVENT_ID_SHIFT              12
  44 #define IRQ_EVENT_ID_MASK               0x3ff
  45
  46 /* register range of each mbigen node */
  47 #define MBIGEN_NODE_OFFSET              0x1000
  48
  49 /* offset of vector register in mbigen node */
  50 #define REG_MBIGEN_VEC_OFFSET           0x200
  51
  52 /**
  53  * offset of clear register in mbigen node
  54  * This register is used to clear the status
  55  * of interrupt
  56  */
  57 #define REG_MBIGEN_CLEAR_OFFSET         0xa000
  58
  59 /**
  60  * offset of interrupt type register
  61  * This register is used to configure interrupt
  62  * trigger type
  63  */
  64 #define REG_MBIGEN_TYPE_OFFSET          0x0
  65
  66 /**
  67  * struct mbigen_device - holds the information of mbigen device.
  68  *
  69  * @pdev:               pointer to the platform device structure of mbigen chip.
  70  * @base:               mapped address of this mbigen chip.
  71  */
  72 struct mbigen_device {
  73         struct platform_device  *pdev;
  74         void __iomem            *base;
  75 };
  76
  77 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
  78 {
  79         unsigned int nid, pin;
  80
  81         hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
  82         nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
  83         pin = hwirq % IRQS_PER_MBIGEN_NODE;
  84
  85         return pin * 4 + nid * MBIGEN_NODE_OFFSET
  86                         + REG_MBIGEN_VEC_OFFSET;
  87 }
  88
  89 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
  90                                         u32 *mask, u32 *addr)
  91 {
  92         unsigned int nid, irq_ofst, ofst;
  93
  94         hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
  95         nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
  96         irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
  97
  98         *mask = 1 << (irq_ofst % 32);
  99         ofst = irq_ofst / 32 * 4;
 100
 101         *addr = ofst + nid * MBIGEN_NODE_OFFSET
 102                 + REG_MBIGEN_TYPE_OFFSET;
 103 }
 104
 105 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
 106                                         u32 *mask, u32 *addr)
 107 {
 108         unsigned int ofst = (hwirq / 32) * 4;
 109
 110         *mask = 1 << (hwirq % 32);
 111         *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
 112 }
 113
 114 static void mbigen_eoi_irq(struct irq_data *data)
 115 {
 116         void __iomem *base = data->chip_data;
 117         u32 mask, addr;
 118
 119         get_mbigen_clear_reg(data->hwirq, &mask, &addr);
 120
 121         writel_relaxed(mask, base + addr);
 122
 123         irq_chip_eoi_parent(data);
 124 }
 125
 126 static int mbigen_set_type(struct irq_data *data, unsigned int type)
 127 {
 128         void __iomem *base = data->chip_data;
 129         u32 mask, addr, val;
 130
 131         if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
 132                 return -EINVAL;
 133
 134         get_mbigen_type_reg(data->hwirq, &mask, &addr);
 135
 136         val = readl_relaxed(base + addr);
 137
 138         if (type == IRQ_TYPE_LEVEL_HIGH)
 139                 val |= mask;
 140         else
 141                 val &= ~mask;
 142
 143         writel_relaxed(val, base + addr);
 144
 145         return 0;
 146 }
 147
 148 static struct irq_chip mbigen_irq_chip = {
 149         .name =                 "mbigen-v2",
 150         .irq_mask =             irq_chip_mask_parent,
 151         .irq_unmask =           irq_chip_unmask_parent,
 152         .irq_eoi =              mbigen_eoi_irq,
 153         .irq_set_type =         mbigen_set_type,
 154         .irq_set_affinity =     irq_chip_set_affinity_parent,
 155 };
 156
 157 static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
 158 {
 159         struct irq_data *d = irq_get_irq_data(desc->irq);
 160         void __iomem *base = d->chip_data;
 161         u32 val;
 162
 163         base += get_mbigen_vec_reg(d->hwirq);
 164         val = readl_relaxed(base);
 165
 166         val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
 167         val |= (msg->data << IRQ_EVENT_ID_SHIFT);
 168
 169         /* The address of doorbell is encoded in mbigen register by default
 170          * So,we don't need to program the doorbell address at here
 171          */
 172         writel_relaxed(val, base);
 173 }
 174
 175 static int mbigen_domain_translate(struct irq_domain *d,
 176                                     struct irq_fwspec *fwspec,
 177                                     unsigned long *hwirq,
 178                                     unsigned int *type)
 179 {
 180         if (is_of_node(fwspec->fwnode)) {
 181                 if (fwspec->param_count != 2)
 182                         return -EINVAL;
 183
 184                 if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
 185                         (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
 186                         return -EINVAL;
 187                 else
 188                         *hwirq = fwspec->param[0];
 189
 190                 /* If there is no valid irq type, just use the default type */
 191                 if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
 192                         (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
 193                         *type = fwspec->param[1];
 194                 else
 195                         return -EINVAL;
 196
 197                 return 0;
 198         }
 199         return -EINVAL;
 200 }
 201
 202 static int mbigen_irq_domain_alloc(struct irq_domain *domain,
 203                                         unsigned int virq,
 204                                         unsigned int nr_irqs,
 205                                         void *args)
 206 {
 207         struct irq_fwspec *fwspec = args;
 208         irq_hw_number_t hwirq;
 209         unsigned int type;
 210         struct mbigen_device *mgn_chip;
 211         int i, err;
 212
 213         err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
 214         if (err)
 215                 return err;
 216
 217         err = platform_msi_domain_alloc(domain, virq, nr_irqs);
 218         if (err)
 219                 return err;
 220
 221         mgn_chip = platform_msi_get_host_data(domain);
 222
 223         for (i = 0; i < nr_irqs; i++)
 224                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 225                                       &mbigen_irq_chip, mgn_chip->base);
 226
 227         return 0;
 228 }
 229
 230 static struct irq_domain_ops mbigen_domain_ops = {
 231         .translate      = mbigen_domain_translate,
 232         .alloc          = mbigen_irq_domain_alloc,
 233         .free           = irq_domain_free_irqs_common,
 234 };
 235
 236 static int mbigen_device_probe(struct platform_device *pdev)
 237 {
 238         struct mbigen_device *mgn_chip;
 239         struct platform_device *child;
 240         struct irq_domain *domain;
 241         struct device_node *np;
 242         struct device *parent;
 243         struct resource *res;
 244         u32 num_pins;
 245
 246         mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
 247         if (!mgn_chip)
 248                 return -ENOMEM;
 249
 250         mgn_chip->pdev = pdev;
 251
 252         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 253         mgn_chip->base = devm_ioremap_resource(&pdev->dev, res);
 254         if (IS_ERR(mgn_chip->base))
 255                 return PTR_ERR(mgn_chip->base);
 256
 257         for_each_child_of_node(pdev->dev.of_node, np) {
 258                 if (!of_property_read_bool(np, "interrupt-controller"))
 259                         continue;
 260
 261                 parent = platform_bus_type.dev_root;
 262                 child = of_platform_device_create(np, NULL, parent);
 263                 if (!child)
 264                         return -ENOMEM;
 265
 266                 if (of_property_read_u32(child->dev.of_node, "num-pins",
 267                                          &num_pins) < 0) {
 268                         dev_err(&pdev->dev, "No num-pins property\n");
 269                         return -EINVAL;
 270                 }
 271
 272                 domain = platform_msi_create_device_domain(&child->dev, num_pins,
 273                                                            mbigen_write_msg,
 274                                                            &mbigen_domain_ops,
 275                                                            mgn_chip);
 276                 if (!domain)
 277                         return -ENOMEM;
 278         }
 279
 280         platform_set_drvdata(pdev, mgn_chip);
 281         return 0;
 282 }
 283
 284 static const struct of_device_id mbigen_of_match[] = {
 285         { .compatible = "hisilicon,mbigen-v2" },
 286         { /* END */ }
 287 };
 288 MODULE_DEVICE_TABLE(of, mbigen_of_match);
 289
 290 static struct platform_driver mbigen_platform_driver = {
 291         .driver = {
 292                 .name           = "Hisilicon MBIGEN-V2",
 293                 .owner          = THIS_MODULE,
 294                 .of_match_table = mbigen_of_match,
 295         },
 296         .probe                  = mbigen_device_probe,
 297 };
 298
 299 module_platform_driver(mbigen_platform_driver);
 300
 301 MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
 302 MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
 303 MODULE_LICENSE("GPL");
 304 MODULE_DESCRIPTION("Hisilicon MBI Generator driver");